1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 #include "hal_config.h" 22 #include "clock_ll.h" 23 24 25 //set dco clock division 26 #define clock_hal_set_dco_1_div(hal) clock_ll_set_dco_clk_1_div((hal)->hw) 27 #define clock_hal_set_dco_2_div(hal) clock_ll_set_dco_clk_2_div((hal)->hw) 28 #define clock_hal_set_dco_4_div(hal) clock_ll_set_dco_clk_4_div((hal)->hw) 29 #define clock_hal_set_dco_8_div(hal) clock_ll_set_dco_clk_8_div((hal)->hw) 30 31 #define clock_hal_set_26m_1_div(hal) clock_ll_set_26m_clk_1_div((hal)->hw) 32 #define clock_hal_set_26m_2_div(hal) clock_ll_set_26m_clk_2_div((hal)->hw) 33 #define clock_hal_set_26m_4_div(hal) clock_ll_set_26m_clk_4_div((hal)->hw) 34 #define clock_hal_set_26m_8_div(hal) clock_ll_set_26m_clk_8_div((hal)->hw) 35 36 37 38 //set peripheral clock source 39 #define clock_hal_uart_set_clk_26m(hal, id) clock_ll_set_uart_clk_26m((hal)->hw, id) 40 #define clock_hal_uart_set_clk_dco(hal, id) clock_ll_set_uart_clk_dco((hal)->hw, id) 41 42 #define clock_hal_i2c_set_clk_26m(hal, id) clock_ll_set_i2c_clk_26m((hal)->hw, id) 43 #define clock_hal_i2c_set_clk_dco(hal, id) clock_ll_set_i2c_clk_dco((hal)->hw, id) 44 45 #define clock_hal_irda_set_clk_26m(hal) clock_ll_set_irda_clk_26m((hal)->hw) 46 #define clock_hal_irda_set_clk_dco(hal) clock_ll_set_irda_clk_dco((hal)->hw) 47 48 #define clock_hal_spi_set_clk_26m(hal, id) clock_ll_set_spi_clk_26m((hal)->hw, id) 49 #define clock_hal_spi_set_clk_dco(hal, id) clock_ll_set_spi_clk_dco((hal)->hw, id) 50 51 #define clock_hal_saradc_set_clk_26m(hal) clock_ll_set_saradc_clk_26m((hal)->hw) 52 #define clock_hal_saradc_set_clk_dco(hal) clock_ll_set_saradc_clk_dco((hal)->hw) 53 54 #define clock_hal_pwms_set_clk_26m(hal) clock_ll_set_pwms_clk_26m((hal)->hw) 55 #define clock_hal_pwms_set_clk_dco(hal) clock_ll_set_pwms_clk_dco((hal)->hw) 56 57 #define clock_hal_enable_pwm_lpo_clk(hal, chan) clock_ll_enable_pwm_lpo_clk((hal)->hw, chan) 58 #define clock_hal_disable_pwm_lpo_clk(hal, chan) clock_ll_disable_pwm_lpo_clk((hal)->hw, chan) 59 60 #define clock_hal_sdio_set_clk_26m(hal) clock_ll_set_sdio_clk_26m((hal)->hw) 61 #define clock_hal_sdio_set_clk_dco(hal) clock_ll_set_sdio_clk_dco((hal)->hw) 62 63 #define clock_hal_saradc_enable_audio_pll(hal) clock_ll_set_saradc_enable_audio_pll((hal)->hw) 64 #define clock_hal_saradc_disable_audio_pll(hal) clock_ll_set_saradc_disable_audio_pll((hal)->hw) 65 66 #define clock_hal_qspi_set_clk_26m(hal) clock_ll_set_qspi_clk_26m((hal)->hw) 67 #define clock_hal_qspi_set_clk_dco(hal) clock_ll_set_qspi_clk_dco((hal)->hw) 68 #define clock_hal_qspi_set_clk_120m(hal) clock_ll_set_qspi_clk_120m((hal)->hw) 69 #define clock_hal_qspi_set_clk_80m(hal) clock_ll_set_qspi_clk_80m((hal)->hw) 70 71 #define clock_hal_efuse_set_clk_26m(hal) clock_ll_set_efuse_clk_26m((hal)->hw) 72 #define clock_hal_efuse_set_clk_dco(hal) clock_ll_set_efuse_clk_dco((hal)->hw) 73 74 #define clock_hal_cec_set_clk_26m(hal) clock_ll_set_cec_clk_26m((hal)->hw) 75 #define clock_hal_cec_set_clk_dco(hal) clock_ll_set_cec_clk_dco((hal)->hw) 76 77 #define clock_hal_set_i2s_1_div(hal) clock_ll_set_i2s_mclk_1_div((hal)->hw) 78 #define clock_hal_set_i2s_2_div(hal) clock_ll_set_i2s_mclk_2_div((hal)->hw) 79 #define clock_hal_set_i2s_4_div(hal) clock_ll_set_i2s_mclk_4_div((hal)->hw) 80 #define clock_hal_set_i2s_8_div(hal) clock_ll_set_i2s_mclk_8_div((hal)->hw) 81 #define clock_hal_set_i2s_16_div(hal) clock_ll_set_i2s_mclk_16_div((hal)->hw) 82 #define clock_hal_set_i2s_32_div(hal) clock_ll_set_i2s_mclk_32_div((hal)->hw) 83 84 #define clock_hal_get_uart_clk(hal ,id) clock_ll_get_uart_clk((hal)->hw, id) 85 86 #if CONFIG_SOC_BK7236A 87 #define clock_hal_jpeg_set_96m(hal) icu_ll_jpeg_set_96m((hal)->hw) 88 #define clock_hal_jpeg_set_120m(hal) icu_ll_jpeg_set_120m((hal)->hw) 89 #define clock_hal_jpeg_set_160m(hal) icu_ll_jpeg_set_160m((hal)->hw) 90 #define clock_hal_jpeg_set_240m(hal) icu_ll_jpeg_set_240m((hal)->hw) 91 #endif 92 93 #ifdef __cplusplus 94 } 95 #endif 96