1 /*
2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 /******************************************************************************
18 * @file core_804.h
19 * @brief CSI 804 Core Peripheral Access Layer Header File
20 * @version V1.0
21 * @date 02. June 2017
22 ******************************************************************************/
23 #ifndef __CORE_804_H_GENERIC
24 #define __CORE_804_H_GENERIC
25 #include <stdint.h>
26 #include "csi_config.h"
27
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31
32 /*******************************************************************************
33 * CSI definitions
34 ******************************************************************************/
35 /**
36 \ingroup Ck804
37 @{
38 */
39
40 /* CSI CK804 definitions */
41 #define __CK804_CSI_VERSION_MAIN (0x04U) /* !< [31:16] CSI HAL main version */
42 #define __CK804_CSI_VERSION_SUB (0x1EU) /* !< [15:0] CSI HAL sub version */
43 #define __CK804_CSI_VERSION ((__CK804_CSI_VERSION_MAIN << 16U) | \
44 __CK804_CSI_VERSION_SUB ) /* !< CSI HAL version number */
45
46 #ifndef __CK80X
47 #define __CK80X (0x03U) /* !< CK80X Core */
48 #endif
49
50 /* __FPU_USED indicates whether an FPU is used or not. */
51 #define __FPU_USED 1U
52
53 #if defined ( __GNUC__ )
54 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
55 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
56 #endif
57 #endif
58
59 #ifdef __cplusplus
60 }
61 #endif
62
63 #ifndef __CSI_GENERIC
64
65 #ifndef __CORE_CK804_H_DEPENDANT
66 #define __CORE_CK804_H_DEPENDANT
67
68 #ifdef __cplusplus
69 extern "C" {
70 #endif
71
72 /* check device defines and use defaults */
73 #ifndef __CK804_REV
74 #define __CK804_REV 0x0000U
75 #endif
76
77 #ifndef __VIC_PRIO_BITS
78 #define __VIC_PRIO_BITS 2U
79 #endif
80
81 #ifndef __Vendor_SysTickConfig
82 #define __Vendor_SysTickConfig 1U
83 #endif
84
85 #ifndef __GSR_GCR_PRESENT
86 #define __GSR_GCR_PRESENT 0U
87 #endif
88
89 #ifndef __MPU_PRESENT
90 #define __MPU_PRESENT 1U
91 #endif
92
93 #ifndef __ICACHE_PRESENT
94 #define __ICACHE_PRESENT 1U
95 #endif
96
97 #ifndef __DCACHE_PRESENT
98 #define __DCACHE_PRESENT 1U
99 #endif
100
101 #include <csi_gcc.h>
102
103 /* IO definitions (access restrictions to peripheral registers) */
104 /**
105 \defgroup CSI_glob_defs CSI Global Defines
106
107 <strong>IO Type Qualifiers</strong> are used
108 \li to specify the access to peripheral variables.
109 \li for automatic generation of peripheral register debug information.
110 */
111 #ifdef __cplusplus
112 #define __I volatile /* !< Defines 'read only' permissions */
113 #else
114 #define __I volatile const /* !< Defines 'read only' permissions */
115 #endif
116 #define __O volatile /* !< Defines 'write only' permissions */
117 #define __IO volatile /* !< Defines 'read / write' permissions */
118
119 /* following defines should be used for structure members */
120 #define __IM volatile const /* ! Defines 'read only' structure member permissions */
121 #define __OM volatile /* ! Defines 'write only' structure member permissions */
122 #define __IOM volatile /* ! Defines 'read / write' structure member permissions */
123
124 /* @} end of group CK804 */
125
126 /*******************************************************************************
127 * Register Abstraction
128 Core Register contain:
129 - Core Register
130 - Core VIC Register
131 - Core Cache Register
132 - Core CoreTIM Register
133 ******************************************************************************/
134 /**
135 \defgroup CSI_core_register Defines and Type Definitions
136 \brief Type definitions and defines for CK80X processor based devices.
137 */
138
139 /**
140 \ingroup CSI_core_register
141 \defgroup CSI_CORE Status and Control Registers
142 \brief Core Register type definitions.
143 @{
144 */
145
146 /**
147 \brief Access Processor Status Register(PSR)struct definition.
148 */
149 typedef union {
150 struct {
151 uint32_t C : 1; /* !< bit: 0 Conditional code/Carry flag */
152 uint32_t _reserved0 : 5; /* !< bit: 2.. 5 Reserved */
153 uint32_t IE : 1; /* !< bit: 6 Interrupt effective control bit */
154 uint32_t IC : 1; /* !< bit: 7 Interrupt control bit */
155 uint32_t EE : 1; /* !< bit: 8 Abnormally effective control bit */
156 uint32_t MM : 1; /* !< bit: 9 Unsymmetrical masking bit */
157 uint32_t _reserved1 : 6; /* !< bit: 10..15 Reserved */
158 uint32_t VEC : 8; /* !< bit: 16..23 Abnormal event vector value */
159 uint32_t _reserved2 : 1; /* !< bit: 24 Reserved */
160 uint32_t SV : 1; /* !< bit: 25 Stacked valid */
161 uint32_t SD : 1; /* !< bit: 26 Stacked dirty */
162 uint32_t SC : 1; /* !< bit: 27 Secure call bit */
163 uint32_t HS : 1; /* !< bit: 28 Hardware stacked bit */
164 uint32_t SP : 1; /* !< bit: 29 Secure pending bit */
165 uint32_t T : 1; /* !< bit: 30 TEE mode bit */
166 uint32_t S : 1; /* !< bit: 31 Superuser mode set bit */
167 } b; /* !< Structure Access by bit */
168 uint32_t w; /* !< Type Access by whole register */
169 } PSR_Type;
170
171 /* PSR Register Definitions */
172 #define PSR_S_Pos 31U /*!< PSR: S Position */
173 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
174
175 #define PSR_T_Pos 30U /*!< PSR: T Position */
176 #define PSR_T_Msk (1UL << PSR_T_Pos) /*!< PSR: T Mask */
177
178 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
179 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
180
181 #define PSR_MM_Pos 9U /*!< PSR: MM Position */
182 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
183
184 #define PSR_EE_Pos 8U /*!< PSR: EE Position */
185 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
186
187 #define PSR_IC_Pos 7U /*!< PSR: IC Position */
188 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
189
190 #define PSR_IE_Pos 6U /*!< PSR: IE Position */
191 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
192
193 #define PSR_C_Pos 0U /*!< PSR: C Position */
194 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
195
196 /**
197 \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
198 */
199 typedef union {
200 struct {
201 uint32_t MP : 1; /*! < bit: 0.. 1 memory protection settings */
202 uint32_t _reserved0 : 6; /*! < bit: 2.. 6 Reserved */
203 uint32_t BE : 1; /*! < bit: 7 Endian mode */
204 uint32_t SCK : 3; /*! < bit: 8..10 the clock ratio of the system and the processor */
205 uint32_t _reserved1 : 2; /*! < bit: 11..12 Reserved */
206 uint32_t BE_V2 : 1; /*! < bit: 13 V2 Endian mode */
207 uint32_t _reserved2 : 18; /*! < bit: 14..31 Reserved */
208 } b; /* !< Structure Access by bit */
209 uint32_t w; /* !< Type Access by whole register */
210 } CCR_Type;
211
212 /* CCR Register Definitions */
213 #define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
214 #define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
215
216 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
217 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
218
219 #define CCR_BE_Pos 7U /*!< CCR: BE Position */
220 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
221
222 #define CCR_MP_Pos 0U /*!< CCR: MP Position */
223 #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
224
225 /**
226 \brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
227 */
228 typedef union {
229 struct {
230 uint32_t X0 : 1; /* !< bit: 0 Non executable attribute setting */
231 uint32_t X1 : 1; /* !< bit: 1 Non executable attribute setting */
232 uint32_t X2 : 1; /* !< bit: 2 Non executable attribute setting */
233 uint32_t X3 : 1; /* !< bit: 3 Non executable attribute setting */
234 uint32_t X4 : 1; /* !< bit: 4 Non executable attribute setting */
235 uint32_t X5 : 1; /* !< bit: 5 Non executable attribute setting */
236 uint32_t X6 : 1; /* !< bit: 6 Non executable attribute setting */
237 uint32_t X7 : 1; /* !< bit: 7 Non executable attribute setting */
238 uint32_t AP0 : 2; /* !< bit: 8.. 9 access permissions settings bit */
239 uint32_t AP1 : 2; /* !< bit: 10..11 access permissions settings bit */
240 uint32_t AP2 : 2; /* !< bit: 12..13 access permissions settings bit */
241 uint32_t AP3 : 2; /* !< bit: 14..15 access permissions settings bit */
242 uint32_t AP4 : 2; /* !< bit: 16..17 access permissions settings bit */
243 uint32_t AP5 : 2; /* !< bit: 18..19 access permissions settings bit */
244 uint32_t AP6 : 2; /* !< bit: 20..21 access permissions settings bit */
245 uint32_t AP7 : 2; /* !< bit: 22..23 access permissions settings bit */
246 uint32_t S0 : 1; /* !< bit: 24 Security property settings */
247 uint32_t S1 : 1; /* !< bit: 25 Security property settings */
248 uint32_t S2 : 1; /* !< bit: 26 Security property settings */
249 uint32_t S3 : 1; /* !< bit: 27 Security property settings */
250 uint32_t S4 : 1; /* !< bit: 28 Security property settings */
251 uint32_t S5 : 1; /* !< bit: 29 Security property settings */
252 uint32_t S6 : 1; /* !< bit: 30 Security property settings */
253 uint32_t S7 : 1; /* !< bit: 31 Security property settings */
254 } b; /* !< Structure Access by bit */
255 uint32_t w; /* !< Type Access by whole register */
256 } CAPR_Type;
257
258 /* CAPR Register Definitions */
259 #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
260 #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
261
262 #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
263 #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
264
265 #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
266 #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
267
268 #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
269 #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
270
271 #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
272 #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
273
274 #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
275 #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
276
277 #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
278 #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
279
280 #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
281 #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
282
283 #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
284 #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
285
286 #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
287 #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
288
289 #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
290 #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
291
292 #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
293 #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
294
295 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
296 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
297
298 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
299 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
300
301 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
302 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
303
304 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
305 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
306
307 #define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
308 #define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
309
310 #define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
311 #define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
312
313 #define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
314 #define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
315
316 #define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
317 #define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
318
319 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
320 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
321
322 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
323 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
324
325 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
326 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
327
328 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
329 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
330
331 /**
332 \brief Consortium definition for accessing control register(PACR, CR<20,0>).
333 */
334 typedef union {
335 struct {
336 uint32_t E : 1; /* !< bit: 0 Effective setting of protected area */
337 uint32_t size : 5; /* !< bit: 1.. 5 Size of protected area */
338 uint32_t _reserved0 : 6; /* !< bit: 6.. 11 Reserved */
339 uint32_t base_addr : 20; /* !< bit: 10..31 The high position of the address of a protected area */
340 } b; /* !< Structure Access by bit */
341 uint32_t w; /* !< Type Access by whole register */
342 } PACR_Type;
343
344 /* PACR Register Definitions */
345 #define PACR_BASE_ADDR_Pos 12U /* !< PACR: base_addr Position */
346 #define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /* !< PACR: base_addr Mask */
347
348 #define PACR_SIZE_Pos 1U /* !< PACR: Size Position */
349 #define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /* !< PACR: Size Mask */
350
351 #define PACR_E_Pos 0U /* !< PACR: E Position */
352 #define PACR_E_Msk (0x1UL << PACR_E_Pos) /* !< PACR: E Mask */
353
354 /**
355 \brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
356 */
357 typedef union {
358 struct {
359 uint32_t RID : 3; /* !< bit: 0.. 2 Protected area index value */
360 uint32_t _reserved0 : 29; /* !< bit: 3..31 Reserved */
361 } b; /* !< Structure Access by bit */
362 uint32_t w; /* !< Type Access by whole register */
363 } PRSR_Type;
364
365 /* PRSR Register Definitions */
366 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
367 #define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
368
369 /**
370 \brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
371 */
372 typedef union {
373 struct {
374 uint32_t _reserved0 : 1; /* !< bit: 0 Reserved */
375 uint32_t BE : 1; /* !< bit: 1 System bus support burst transer */
376 uint32_t IPE : 1; /* !< bit: 2 Instruction prefetch function enable */
377 uint32_t RPE : 1; /* !< bit: 3 Function return instruction RTS will speculate execution */
378 uint32_t IAE : 1; /* !< bit: 4 Interrupt response acceleration enable */
379 uint32_t _reserved1 : 9; /* !< bit: 5..13 Reserved */
380 uint32_t ISE : 1; /* !< bit: 14 Interrupt SP enable */
381 uint32_t HS_EXP : 1; /* !< bit: 15 Exception bit for TEE world switch */
382 uint32_t SRST_VAL : 16; /* !< bit: 16..31 Software reset decision value */
383 } b;
384 uint32_t w;
385 } CHR_Type;
386
387 /* CHR Register Definitions */
388 #define CHR_BE_Pos 1U /*!< CHR: BE Position */
389 #define CHR_BE_Msk (1UL << CHR_BE_Pos) /*!< CHR: BE Mask */
390 #define CHR_IPE_Pos 1U /*!< CHR: IPE Position */
391 #define CHR_IPE_Msk (1UL << CHR_IPE_Pos) /*!< CHR: IPE Mask */
392 #define CHR_RPE_Pos 1U /*!< CHR: RPE Position */
393 #define CHR_RPE_Msk (1UL << CHR_RPE_Pos) /*!< CHR: RPE Mask */
394 #define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
395 #define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
396 #define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
397 #define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
398 #define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
399 #define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
400 #define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
401 #define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
402
403 /* @} end of group CSI_CORE */
404
405 /**
406 \ingroup CSI_core_register
407 \defgroup CSI_VIC Vectored Interrupt Controller (VIC)
408 \brief Type definitions for the VIC Registers
409 @{
410 */
411
412 /**
413 \brief Access to the structure of a vector interrupt controller.
414 */
415 typedef struct {
416 __IOM uint32_t ISER[4U]; /* !< Offset: 0x000 (R/W) Interrupt set enable register */
417 uint32_t RESERVED0[12U];
418 __IOM uint32_t IWER[4U]; /* !< Offset: 0x040 (R/W) Interrupt wake-up set register */
419 uint32_t RESERVED1[12U];
420 __IOM uint32_t ICER[4U]; /* !< Offset: 0x080 (R/W) Interrupt clear enable register */
421 uint32_t RESERVED2[12U];
422 __IOM uint32_t IWDR[4U]; /* !< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
423 uint32_t RESERVED3[12U];
424 __IOM uint32_t ISPR[4U]; /* !< Offset: 0x100 (R/W) Interrupt set pend register */
425 uint32_t RESERVED4[12U];
426 __IOM uint32_t ISSR[4U]; /* !< Offset: 0x140 (R/W) Security interrupt set register */
427 uint32_t RESERVED5[12U];
428 __IOM uint32_t ICPR[4U]; /* !< Offset: 0x180 (R/W) Interrupt clear pend register */
429 uint32_t RESERVED6[12U];
430 __IOM uint32_t ICSR[4U]; /* !< Offset: 0x1c0 (R/W) Security interrupt clear register */
431 uint32_t RESERVED7[12U];
432 __IOM uint32_t IABR[4U]; /* !< Offset: 0x200 (R/W) Interrupt answer stateregister */
433 uint32_t RESERVED8[60U];
434 __IOM uint32_t IPR[32U]; /* !< Offset: 0x300 (R/W) Interrupt priority register */
435 uint32_t RESERVED9[480U];
436 __IM uint32_t ISR; /* !< Offset: 0xB00 (R/ ) Interrupt state register */
437 __IOM uint32_t IPTR; /* !< Offset: 0xB04 (R/W) Interrupt priority thershold register */
438 __IOM uint32_t TSPEND; /* !< Offset: 0xB08 (R/W) Task pending register */
439 __IOM uint32_t TSABR; /* !< Offset: 0xB0c (R/W) Tspend acknowledge register */
440 __IOM uint32_t TSPR; /* !< Offset: 0xB10 (R/W) Tspend priority register */
441 } VIC_Type;
442
443 /* @} end of group CSI_VIC */
444
445 /**
446 \ingroup CSI_core_register
447 \defgroup CSI_CACHE
448 \brief Type definitions for the cache Registers
449 @{
450 */
451
452 /**
453 \brief On chip cache structure.
454 */
455 typedef struct {
456 __IOM uint32_t CER; /* !< Offset: 0x000 (R/W) Cache enable register */
457 __IOM uint32_t CIR; /* !< Offset: 0x004 (R/W) Cache invalid register */
458 __IOM uint32_t CRCR[4U]; /* !< Offset: 0x008 (R/W) Cache Configuration register */
459 uint32_t RSERVED0[1015U];
460 __IOM uint32_t CPFCR; /* !< Offset: 0xFF4 (R/W) Cache performance analisis control register */
461 __IOM uint32_t CPFATR; /* !< Offset: 0xFF8 (R/W) Cache access times register */
462 __IOM uint32_t CPFMTR; /* !< Offset: 0xFFC (R/W) Cache missing times register */
463 } CACHE_Type;
464
465 /* CACHE Register Definitions */
466 #define CACHE_CER_EN_Pos 0U /* !< CACHE CER: EN Position */
467 #define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /* !< CACHE CER: EN Mask */
468
469 #define CACHE_CER_CFIG_Pos 1U /* !< CACHE CER: CFIG Position */
470 #define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /* !< CACHE CER: CFIG Mask */
471
472 #define CACHE_CER_WB_Pos 2U /* !< CACHE CER: WB Position */
473 #define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /* !< CACHE CER: WB Mask */
474
475 #define CACHE_CER_DCW_Pos 4U /* !< CACHE CER: DCW Position */
476 #define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /* !< CACHE CER: DCW Mask */
477
478 #define CACHE_CER_WA_Pos 5U /* !< CACHE CER: WA Position */
479 #define CACHE_CER_WA_Msk (0x1UL << CACHE_CER_WA_Pos) /* !< CACHE CER: WA Mask */
480
481 #define CACHE_CIR_INV_ALL_Pos 0U /* !< CACHE CIR: INV_ALL Position */
482 #define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /* !< CACHE CIR: INV_ALL Mask */
483
484 #define CACHE_CIR_INV_ONE_Pos 1U /* !< CACHE CIR: INV_ONE Position */
485 #define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /* !< CACHE CIR: INV_ONE Mask */
486
487 #define CACHE_CIR_CLR_ALL_Pos 2U /* !< CACHE CIR: CLR_ALL Position */
488 #define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /* !< CACHE CIR: CLR_ALL Mask */
489
490 #define CACHE_CIR_CLR_ONE_Pos 3U /* !< CACHE CIR: CLR_ONE Position */
491 #define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /* !< CACHE CIR: CLR_ONE Mask */
492
493 #define CACHE_CIR_INV_ADDR_Pos 4U /* !< CACHE CIR: INV_ADDR Position */
494 #define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos)
495 /* !< CACHE CIR: INV_ADDR Mask */
496
497 #define CACHE_CRCR_EN_Pos 0U /* !< CACHE CRCR: EN Position */
498 #define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /* !< CACHE CRCR: EN Mask */
499
500 #define CACHE_CRCR_SIZE_Pos 1U /* !< CACHE CRCR: Size Position */
501 #define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /* !< CACHE CRCR: Size Mask */
502
503 #define CACHE_CRCR_SE_Pos 6U /* !< CACHE CRCR: SE Position */
504 #define CACHE_CRCR_SE_Msk (0x1UL << CACHE_CRCR_SE_Pos) /* !< CACHE CRCR: SE Mask */
505
506 #define CACHE_CRCR_BASE_ADDR_Pos 10U /* !< CACHE CRCR: base addr Position */
507 #define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos)
508 /* !< CACHE CRCR: base addr Mask */
509
510 #define CACHE_CPFCR_PFEN_Pos 0U /* !< CACHE CPFCR: PFEN Position */
511 #define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /* !< CACHE CPFCR: PFEN Mask */
512
513 #define CACHE_CPFCR_PFRST_Pos 1U /* !< CACHE CPFCR: PFRST Position */
514 #define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /* !< CACHE CPFCR: PFRST Mask */
515
516 #define CACHE_CRCR_4K 0xB /* 01011 */
517 #define CACHE_CRCR_8K 0xC /* 01100 */
518 #define CACHE_CRCR_16K 0xD /* 01101 */
519 #define CACHE_CRCR_32K 0xE /* 01110 */
520 #define CACHE_CRCR_64K 0xF /* 01111 */
521 #define CACHE_CRCR_128K 0x10 /* 10000 */
522 #define CACHE_CRCR_256K 0x11 /* 10001 */
523 #define CACHE_CRCR_512K 0x12 /* 10010 */
524 #define CACHE_CRCR_1M 0x13 /* 10011 */
525 #define CACHE_CRCR_2M 0x14 /* 10100 */
526 #define CACHE_CRCR_4M 0x15 /* 10101 */
527 #define CACHE_CRCR_8M 0x16 /* 10110 */
528 #define CACHE_CRCR_16M 0x17 /* 10111 */
529 #define CACHE_CRCR_32M 0x18 /* 11000 */
530 #define CACHE_CRCR_64M 0x19 /* 11001 */
531 #define CACHE_CRCR_128M 0x1A /* 11010 */
532 #define CACHE_CRCR_256M 0x1B /* 11011 */
533 #define CACHE_CRCR_512M 0x1C /* 11100 */
534 #define CACHE_CRCR_1G 0x1D /* 11101 */
535 #define CACHE_CRCR_2G 0x1E /* 11110 */
536 #define CACHE_CRCR_4G 0x1F /* 11111 */
537
538 /* @} end of group CSI_CACHE */
539
540 /**
541 \ingroup CSI_core_register
542 \defgroup CSI_SysTick System Tick Timer (CORET)
543 \brief Type definitions for the System Timer Registers.
544 @{
545 */
546
547 /**
548 \brief The data structure of the access system timer.
549 */
550 typedef struct {
551 __IOM uint32_t CTRL; /* !< Offset: 0x000 (R/W) Control register */
552 __IOM uint32_t LOAD; /* !< Offset: 0x004 (R/W) Backfill register */
553 __IOM uint32_t VAL; /* !< Offset: 0x008 (R/W) Current register */
554 __IM uint32_t CALIB; /* !< Offset: 0x00C (R/ ) Calibration register */
555 } CORET_Type;
556
557 /* CORET Control / Status Register Definitions */
558 #define CORET_CTRL_COUNTFLAG_Pos 16U /* !< CORET CTRL: COUNTFLAG Position */
559 #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /* !< CORET CTRL: COUNTFLAG Mask */
560
561 #define CORET_CTRL_CLKSOURCE_Pos 2U /* !< CORET CTRL: CLKSOURCE Position */
562 #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /* !< CORET CTRL: CLKSOURCE Mask */
563
564 #define CORET_CTRL_TICKINT_Pos 1U /* !< CORET CTRL: TICKINT Position */
565 #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /* !< CORET CTRL: TICKINT Mask */
566
567 #define CORET_CTRL_ENABLE_Pos 0U /* !< CORET CTRL: ENABLE Position */
568 #define CORET_CTRL_ENABLE_Msk (1UL /* << CORET_CTRL_ENABLE_Pos */) /* !< CORET CTRL: ENABLE Mask */
569
570 /* CORET Reload Register Definitions */
571 #define CORET_LOAD_RELOAD_Pos 0U /* !< CORET LOAD: RELOAD Position */
572 #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /* << CORET_LOAD_RELOAD_Pos */) /* !< CORET LOAD: RELOAD Mask */
573
574 /* CORET Current Register Definitions */
575 #define CORET_VAL_CURRENT_Pos 0U /* !< CORET VAL: CURRENT Position */
576 #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /* << CORET_VAL_CURRENT_Pos */) /* !< CORET VAL: CURRENT Mask */
577
578 /* CORET Calibration Register Definitions */
579 #define CORET_CALIB_NOREF_Pos 31U /* !< CORET CALIB: NOREF Position */
580 #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /* !< CORET CALIB: NOREF Mask */
581
582 #define CORET_CALIB_SKEW_Pos 30U /* !< CORET CALIB: SKEW Position */
583 #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /* !< CORET CALIB: SKEW Mask */
584
585 #define CORET_CALIB_TENMS_Pos 0U /* !< CORET CALIB: TENMS Position */
586 #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /* << CORET_CALIB_TENMS_Pos */) /* !< CORET CALIB: TENMS Mask */
587
588 /* @} end of group CSI_SysTick */
589
590 /**
591 \ingroup CSI_core_register
592 \defgroup CSI_DCC
593 \brief Type definitions for the DCC.
594 @{
595 */
596
597 /**
598 \brief Access to the data structure of DCC.
599 */
600 typedef struct {
601 uint32_t RESERVED0[13U];
602 __IOM uint32_t HCR; /*! < Offset: 0x034 (R/W) */
603 __IM uint32_t EHSR; /*! < Offset: 0x03C (R/ ) */
604 uint32_t RESERVED1[6U];
605 union {
606 __IM uint32_t DERJW; /* !< Offset: 0x058 (R/ ) Data exchange register CPU read */
607 __OM uint32_t DERJR; /* !< Offset: 0x058 ( /W) Data exchange register CPU writer */
608 };
609 } DCC_Type;
610
611 #define DCC_HCR_JW_Pos 18U /* !< DCC HCR: jw_int_en Position */
612 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /* !< DCC HCR: jw_int_en Mask */
613
614 #define DCC_HCR_JR_Pos 19U /* !< DCC HCR: jr_int_en Position */
615 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /* !< DCC HCR: jr_int_en Mask */
616
617 #define DCC_EHSR_JW_Pos 1U /* !< DCC EHSR: jw_vld Position */
618 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /* !< DCC EHSR: jw_vld Mask */
619
620 #define DCC_EHSR_JR_Pos 2U /* !< DCC EHSR: jr_vld Position */
621 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /* !< DCC EHSR: jr_vld Mask */
622
623 /* @} end of group CSI_DCC */
624
625 /**
626 \ingroup CSI_core_register
627 \defgroup CSI_core_bitfield Core register bit field macros
628 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
629 @{
630 */
631
632 /**
633 \brief Mask and shift a bit field value for use in a register bit range.
634 \param[in] field Name of the register bit field.
635 \param[in] value Value of the bit field.
636 \return Masked and shifted value.
637 */
638 #define _VAL2FLD(field, value) (((value) << field ## _Pos) & field ## _Msk)
639
640 /**
641 \brief Mask and shift a register value to extract a bit filed value.
642 \param[in] field Name of the register bit field.
643 \param[in] value Value of register.
644 \return Masked and shifted bit field value.
645 */
646 #define _FLD2VAL(field, value) (((value) & field ## _Msk) >> field ## _Pos)
647
648 /* @} end of group CSI_core_bitfield */
649
650 /**
651 \ingroup CSI_core_register
652 \defgroup CSI_core_base Core Definitions
653 \brief Definitions for base addresses, unions, and structures.
654 @{
655 */
656
657 /* Memory mapping of CK804 Hardware */
658 #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
659 #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
660 #define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
661 #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
662 #define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
663
664 #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
665 #define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
666 #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
667 #define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
668
669 /* @} */
670
671 /*******************************************************************************
672 * Hardware Abstraction Layer
673 Core Function Interface contains:
674 - Core VIC Functions
675 - Core CORET Functions
676 - Core Register Access Functions
677 ******************************************************************************/
678 /**
679 \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
680 */
681
682 /* ########################## VIC functions #################################### */
683 /**
684 \ingroup CSI_Core_FunctionInterface
685 \defgroup CSI_Core_VICFunctions VIC Functions
686 \brief Functions that manage interrupts and exceptions via the VIC.
687 @{
688 */
689
690 /* The following MACROS handle generation of the register offset and byte masks */
691 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
692 #define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
693 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
694
695 extern uint32_t __Vectors[];
696 extern uint32_t irq_vectors[];
697
698 /* Forward declaration */
699 __STATIC_INLINE void csi_icache_invalid (void);
700
701 /**
702 \brief Enable External Interrupt
703 \details Enable a device-specific interrupt in the VIC interrupt controller.
704 \param [in] IRQn External interrupt number. Value cannot be negative.
705 */
csi_vic_enable_irq(int32_t IRQn)706 __STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
707 {
708 int32_t IRQn_tmp = IRQn;
709 IRQn_tmp &= 0x7FUL;
710
711 VIC->ISER[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
712 #ifdef CONFIG_SYSTEM_SECURE
713 VIC->ISSR[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
714 #endif
715 }
716
717 /**
718 \brief Disable External Interrupt
719 \details Disable a device-specific interrupt in the VIC interrupt controller.
720 \param [in] IRQn External interrupt number. Value cannot be negative.
721 */
csi_vic_disable_irq(int32_t IRQn)722 __STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
723 {
724 int32_t IRQn_tmp = IRQn;
725 IRQn_tmp &= 0x7FUL;
726
727 VIC->ICER[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
728 }
729
730 /**
731 \brief Enable External Secure Interrupt
732 \details Enable a secure device-specific interrupt in the VIC interrupt controller.
733 \param [in] IRQn External interrupt number. Value cannot be negative.
734 */
csi_vic_enable_sirq(int32_t IRQn)735 __STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
736 {
737 int32_t IRQn_tmp = IRQn;
738 IRQn_tmp &= 0x7FUL;
739
740 VIC->ISSR[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
741 }
742
743 /**
744 \brief Disable External Secure Interrupt
745 \details Disable a secure device-specific interrupt in the VIC interrupt controller.
746 \param [in] IRQn External interrupt number. Value cannot be negative.
747 */
csi_vic_disable_sirq(int32_t IRQn)748 __STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
749 {
750 int32_t IRQn_tmp = IRQn;
751 IRQn_tmp &= 0x7FUL;
752
753 VIC->ICSR[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
754 }
755
756 /**
757 \brief Check Interrupt is Enabled or not
758 \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
759 \param [in] IRQn Interrupt number.
760 \return 0 Interrupt status is not enabled.
761 \return 1 Interrupt status is enabled.
762 */
csi_vic_get_enabled_irq(int32_t IRQn)763 __STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
764 {
765 int32_t IRQn_tmp = IRQn;
766 IRQn_tmp &= 0x7FUL;
767
768 return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn_tmp)] &
769 (1UL << (((uint32_t)(int32_t)IRQn_tmp % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL)); // 32:byte alignment
770 }
771
772 /**
773 \brief Check Interrupt is Pending or not
774 \details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
775 \param [in] IRQn Interrupt number.
776 \return 0 Interrupt status is not pending.
777 \return 1 Interrupt status is pending.
778 */
csi_vic_get_pending_irq(int32_t IRQn)779 __STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
780 {
781 int32_t IRQn_tmp = IRQn;
782 IRQn_tmp &= 0x7FUL;
783
784 return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn_tmp)] &
785 (1UL << (((uint32_t)(int32_t)IRQn_tmp % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL)); // 32:byte alignment
786 }
787
788 /**
789 \brief Set Pending Interrupt
790 \details Set the pending bit of an external interrupt.
791 \param [in] IRQn Interrupt number. Value cannot be negative.
792 */
csi_vic_set_pending_irq(int32_t IRQn)793 __STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
794 {
795 int32_t IRQn_tmp = IRQn;
796 IRQn_tmp &= 0x7FUL;
797
798 VIC->ISPR[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
799 }
800
801 /**
802 \brief Clear Pending Interrupt
803 \details Clear the pending bit of an external interrupt.
804 \param [in] IRQn External interrupt number. Value cannot be negative.
805 */
csi_vic_clear_pending_irq(int32_t IRQn)806 __STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
807 {
808 int32_t IRQn_tmp = IRQn;
809 IRQn_tmp &= 0x7FUL;
810
811 VIC->ICPR[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
812 }
813
814 /**
815 \brief Check Interrupt is Wakeup or not
816 \details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
817 \param [in] IRQn Interrupt number.
818 \return 0 Interrupt is not set as wake up interrupt.
819 \return 1 Interrupt is set as wake up interrupt.
820 */
csi_vic_get_wakeup_irq(int32_t IRQn)821 __STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
822 {
823 int32_t IRQn_tmp = IRQn;
824 IRQn_tmp &= 0x7FUL;
825
826 return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn_tmp)] &
827 (1UL << (((uint32_t)(int32_t)IRQn_tmp % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL)); // 32:byte alignment
828 }
829
830 /**
831 \brief Set Wake up Interrupt
832 \details Set the wake up bit of an external interrupt.
833 \param [in] IRQn Interrupt number. Value cannot be negative.
834 */
csi_vic_set_wakeup_irq(int32_t IRQn)835 __STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
836 {
837 int32_t IRQn_tmp = IRQn;
838 IRQn_tmp &= 0x7FUL;
839
840 VIC->IWER[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
841 }
842
843 /**
844 \brief Clear Wake up Interrupt
845 \details Clear the wake up bit of an external interrupt.
846 \param [in] IRQn External interrupt number. Value cannot be negative.
847 */
csi_vic_clear_wakeup_irq(int32_t IRQn)848 __STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
849 {
850 int32_t IRQn_tmp = IRQn;
851 IRQn_tmp &= 0x7FUL;
852
853 VIC->IWDR[_IR_IDX(IRQn_tmp)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn_tmp % 32)); // 32:byte alignment
854 }
855
856 /**
857 \brief Get Interrupt is Active or not
858 \details Read the active register in the VIC and returns the active bit for the device specific interrupt.
859 \param [in] IRQn Device specific interrupt number.
860 \return 0 Interrupt status is not active.
861 \return 1 Interrupt status is active.
862 \note IRQn must not be negative.
863 */
csi_vic_get_active(int32_t IRQn)864 __STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
865 {
866 int32_t IRQn_tmp = IRQn;
867 IRQn_tmp &= 0x7FUL;
868
869 return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn_tmp)] &
870 (1UL << (((uint32_t)(int32_t)IRQn_tmp % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL)); // 32:byte alignment
871 }
872
873 /**
874 \brief Set Threshold register
875 \details set the threshold register in the VIC.
876 \param [in] VectThreshold specific vector threshold.
877 \param [in] PrioThreshold specific priority threshold.
878 */
csi_vic_set_threshold(uint32_t VectThreshold,uint32_t PrioThreshold)879 __STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
880 {
881 uint32_t VectThresholdValue = VectThreshold;
882 VectThresholdValue &= 0x7FUL;
883
884 if (VectThresholdValue <= 31) { // 31:byte alignment
885 VIC->IPTR = 0x80000000 | (((VectThresholdValue + 32) & 0xFF) << 8) | // 32:byte alignment, 8:byte alignment
886 ((PrioThreshold & 0x3) << 6); // 6:byte alignment
887 }
888
889 if (VectThresholdValue > 31 && VectThresholdValue < 96) { // 31:byte alignment, 96:byte alignment
890 VIC->IPTR = 0x80000000 | (((VectThresholdValue + 32) & 0xFF) << 8) | // 32:byte alignment, 8:byte alignment
891 ((PrioThreshold & 0x7) << 5); // 5:byte alignment
892 }
893
894 if (VectThresholdValue > 95) { // 95:byte alignment
895 VIC->IPTR = 0x80000000 | (((VectThresholdValue + 32) & 0xFF) << 8) | // 32:byte alignment, 8:byte alignment
896 ((PrioThreshold & 0xF) << 4); // 4:byte alignment
897 }
898 }
899
900 /**
901 \brief Set Interrupt Priority
902 \details Set the priority of an interrupt.
903 \note The priority cannot be set for every core interrupt.
904 \param [in] IRQn Interrupt number.
905 \param [in] priority Priority to set.
906 */
csi_vic_set_prio(int32_t IRQn,uint32_t priority)907 __STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
908 {
909 VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
910 (((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
911 }
912
913 /**
914 \brief Get Interrupt Priority
915 \details Read the priority of an interrupt.
916 The interrupt number can be positive to specify an external (device specific) interrupt,
917 or negative to specify an internal (core) interrupt.
918 \param [in] IRQn Interrupt number.
919 \return Interrupt Priority.
920 Value is aligned automatically to the implemented priority bits of the microcontroller.
921 */
csi_vic_get_prio(int32_t IRQn)922 __STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
923 {
924 return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
925 }
926
927 /**
928 \brief Set interrupt handler
929 \details Set the interrupt handler according to the interrupt num, the handler will be filled in __Vectors[].
930 \param [in] IRQn Interrupt number.
931 \param [in] handler Interrupt handler.
932 */
csi_vic_set_vector(int32_t IRQn,uint32_t handler)933 __STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
934 {
935 OsSetVector(IRQn, handler);
936
937 csi_icache_invalid();
938 }
939
940 /**
941 \brief Get interrupt handler
942 \details Get the address of interrupt handler function.
943 \param [in] IRQn Interrupt number.
944 */
csi_vic_get_vector(int32_t IRQn)945 __STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
946 {
947 if (IRQn >= 0 && IRQn < 128) {
948 return (uint32_t)irq_vectors[32 + IRQn];
949 }
950
951 return 0;
952 }
953
954 /* @} end of CSI_Core_VICFunctions */
955
956 /* ################################## SysTick function ############################################ */
957 /**
958 \ingroup CSI_Core_FunctionInterface
959 \defgroup CSI_Core_SysTickFunctions SysTick Functions
960 \brief Functions that configure the System.
961 @{
962 */
963
964 /**
965 \brief CORE timer Configuration
966 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
967 Counter is in free running mode to generate periodic interrupts.
968 \param [in] ticks Number of ticks between two interrupts.
969 \param [in] IRQn core timer Interrupt number.
970 \return 0 Function succeeded.
971 \return 1 Function failed.
972 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
973 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
974 must contain a vendor-specific implementation of this function.
975 */
csi_coret_config(uint32_t ticks,int32_t IRQn)976 __STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
977 {
978 if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
979 return (1UL); /* Reload value impossible */
980 }
981
982 CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
983 CORET->VAL = 0UL; /* Load the CORET Counter Value */
984 CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
985 CORET_CTRL_TICKINT_Msk |
986 CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
987 return (0UL); /* Function successful */
988 }
989
990 /**
991 \brief get CORE timer reload value
992 \return CORE timer counter value.
993 */
csi_coret_get_load(void)994 __STATIC_INLINE uint32_t csi_coret_get_load(void)
995 {
996 return CORET->LOAD;
997 }
998
999 /**
1000 \brief get CORE timer counter value
1001 \return CORE timer counter value.
1002 */
csi_coret_get_value(void)1003 __STATIC_INLINE uint32_t csi_coret_get_value(void)
1004 {
1005 return CORET->VAL;
1006 }
1007
1008 /* @} end of CSI_Core_SysTickFunctions */
1009
1010 /* ##################################### DCC function ########################################### */
1011 /**
1012 \ingroup CSI_Core_FunctionInterface
1013 \defgroup CSI_core_DebugFunctions HAD Functions
1014 \brief Functions that access the HAD debug interface.
1015 @{
1016 */
1017
1018 /**
1019 \brief HAD Send Character
1020 \details Transmits a character via the HAD channel 0, and
1021 \li Just returns when no debugger is connected that has booked the output.
1022 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1023 \param [in] ch Character to transmit.
1024 \returns Character to transmit.
1025 */
csi_had_send_char(uint32_t ch)1026 __STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
1027 {
1028 DCC->DERJR = (uint8_t)ch;
1029
1030 return (ch);
1031 }
1032
1033 /**
1034 \brief HAD Receive Character
1035 \details Inputs a character via the external variable \ref HAD_RxBuffer.
1036 \return Received character.
1037 \return -1 No character pending.
1038 */
csi_had_receive_char(void)1039 __STATIC_INLINE int32_t csi_had_receive_char(void)
1040 {
1041 int32_t ch = -1; /* no character available */
1042
1043 if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
1044 ch = DCC->DERJW;
1045 }
1046
1047 return (ch);
1048 }
1049
1050 /**
1051 \brief HAD Check Character
1052 \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
1053 \return 0 No character available.
1054 \return 1 Character available.
1055 */
csi_had_check_char(void)1056 __STATIC_INLINE int32_t csi_had_check_char(void)
1057 {
1058 return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
1059 }
1060
1061 /* @} end of CSI_core_DebugFunctions */
1062
1063 /* ########################## Cache functions #################################### */
1064 /**
1065 \ingroup CSI_Core_FunctionInterface
1066 \defgroup CSI_Core_CacheFunctions Cache Functions
1067 \brief Functions that configure Instruction and Data cache.
1068 @{
1069 */
1070
1071 /**
1072 \brief Enable I-Cache
1073 \details Turns on I-Cache
1074 */
csi_icache_enable(void)1075 __STATIC_INLINE void csi_icache_enable (void)
1076 {
1077 #if (__ICACHE_PRESENT == 1U)
1078 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1079 CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
1080 #endif
1081 }
1082
1083 /**
1084 \brief Disable I-Cache
1085 \details Turns off I-Cache
1086 */
csi_icache_disable(void)1087 __STATIC_INLINE void csi_icache_disable (void)
1088 {
1089 #if (__ICACHE_PRESENT == 1U)
1090 CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
1091 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1092 #endif
1093 }
1094
1095 /**
1096 \brief Invalidate I-Cache
1097 \details Invalidates I-Cache
1098 */
csi_icache_invalid(void)1099 __STATIC_INLINE void csi_icache_invalid (void)
1100 {
1101 #if (__ICACHE_PRESENT == 1U)
1102 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1103 #endif
1104 }
1105
1106 /**
1107 \brief Enable D-Cache
1108 \details Turns on D-Cache
1109 \note I-Cache also turns on.
1110 */
csi_dcache_enable(void)1111 __STATIC_INLINE void csi_dcache_enable (void)
1112 {
1113 #if (__DCACHE_PRESENT == 1U)
1114 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1115 CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk);
1116 #endif
1117 }
1118
1119 /**
1120 \brief Disable D-Cache
1121 \details Turns off D-Cache
1122 \note I-Cache also turns off.
1123 */
csi_dcache_disable(void)1124 __STATIC_INLINE void csi_dcache_disable (void)
1125 {
1126 #if (__DCACHE_PRESENT == 1U)
1127 CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
1128 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1129 #endif
1130 }
1131
1132 /**
1133 \brief Invalidate D-Cache
1134 \details Invalidates D-Cache
1135 \note I-Cache also invalid
1136 */
csi_dcache_invalid(void)1137 __STATIC_INLINE void csi_dcache_invalid (void)
1138 {
1139 #if (__DCACHE_PRESENT == 1U)
1140 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1141 #endif
1142 }
1143
1144 /**
1145 \brief Clean D-Cache
1146 \details Cleans D-Cache
1147 \note I-Cache also cleans
1148 */
csi_dcache_clean(void)1149 __STATIC_INLINE void csi_dcache_clean (void)
1150 {
1151 #if (__DCACHE_PRESENT == 1U)
1152 CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
1153 #endif
1154 }
1155
1156 /**
1157 \brief Clean & Invalidate D-Cache
1158 \details Cleans and Invalidates D-Cache
1159 \note I-Cache also flush.
1160 */
csi_dcache_clean_invalid(void)1161 __STATIC_INLINE void csi_dcache_clean_invalid (void)
1162 {
1163 #if (__DCACHE_PRESENT == 1U)
1164 CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
1165 #endif
1166 }
1167
1168 /**
1169 \brief D-Cache Invalidate by address
1170 \details Invalidates D-Cache for the given address
1171 \param[in] addr address (aligned to 16-byte boundary)
1172 \param[in] dsize size of memory block (in number of bytes)
1173 */
csi_dcache_invalid_range(uint32_t * addr,int32_t dsize)1174 __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
1175 {
1176 #if (__DCACHE_PRESENT == 1U)
1177 int32_t op_size = dsize;
1178 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1179 int32_t linesize = 16;
1180
1181 op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
1182
1183 while (op_size >= 128) {
1184 CACHE->CIR = op_addr;
1185 op_addr += linesize;
1186 CACHE->CIR = op_addr;
1187 op_addr += linesize;
1188 CACHE->CIR = op_addr;
1189 op_addr += linesize;
1190 CACHE->CIR = op_addr;
1191 op_addr += linesize;
1192 CACHE->CIR = op_addr;
1193 op_addr += linesize;
1194 CACHE->CIR = op_addr;
1195 op_addr += linesize;
1196 CACHE->CIR = op_addr;
1197 op_addr += linesize;
1198 CACHE->CIR = op_addr;
1199 op_addr += linesize;
1200
1201 op_size -= 128;
1202 }
1203
1204 while (op_size > 0) {
1205 CACHE->CIR = op_addr;
1206 op_addr += linesize;
1207 op_size -= linesize;
1208 }
1209 #endif
1210 }
1211
1212 /**
1213 \brief D-Cache Clean by address
1214 \details Cleans D-Cache for the given address
1215 \param[in] addr address (aligned to 16-byte boundary)
1216 \param[in] dsize size of memory block (in number of bytes)
1217 */
csi_dcache_clean_range(uint32_t * addr,int32_t dsize)1218 __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
1219 {
1220 #if (__DCACHE_PRESENT == 1)
1221 int32_t op_size = dsize;
1222 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1223 int32_t linesize = 16;
1224
1225 op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
1226
1227 while (op_size >= 128) {
1228 CACHE->CIR = op_addr;
1229 op_addr += linesize;
1230 CACHE->CIR = op_addr;
1231 op_addr += linesize;
1232 CACHE->CIR = op_addr;
1233 op_addr += linesize;
1234 CACHE->CIR = op_addr;
1235 op_addr += linesize;
1236 CACHE->CIR = op_addr;
1237 op_addr += linesize;
1238 CACHE->CIR = op_addr;
1239 op_addr += linesize;
1240 CACHE->CIR = op_addr;
1241 op_addr += linesize;
1242 CACHE->CIR = op_addr;
1243 op_addr += linesize;
1244
1245 op_size -= 128;
1246 }
1247
1248 while (op_size > 0) {
1249 CACHE->CIR = op_addr;
1250 op_addr += linesize;
1251 op_size -= linesize;
1252 }
1253 #endif
1254 }
1255
1256 /**
1257 \brief D-Cache Clean and Invalidate by address
1258 \details Cleans and invalidates D_Cache for the given address
1259 \param[in] addr address (aligned to 16-byte boundary)
1260 \param[in] dsize size of memory block (in number of bytes)
1261 */
csi_dcache_clean_invalid_range(uint32_t * addr,int32_t dsize)1262 __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
1263 {
1264 #if (__DCACHE_PRESENT == 1U)
1265 int32_t op_size = dsize;
1266 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1267 int32_t linesize = 16;
1268
1269 op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
1270
1271 while (op_size >= 128) {
1272 CACHE->CIR = op_addr;
1273 op_addr += linesize;
1274 CACHE->CIR = op_addr;
1275 op_addr += linesize;
1276 CACHE->CIR = op_addr;
1277 op_addr += linesize;
1278 CACHE->CIR = op_addr;
1279 op_addr += linesize;
1280 CACHE->CIR = op_addr;
1281 op_addr += linesize;
1282 CACHE->CIR = op_addr;
1283 op_addr += linesize;
1284 CACHE->CIR = op_addr;
1285 op_addr += linesize;
1286 CACHE->CIR = op_addr;
1287 op_addr += linesize;
1288
1289 op_size -= 128;
1290 }
1291
1292 while (op_size > 0) {
1293 CACHE->CIR = op_addr;
1294 op_addr += linesize;
1295 op_size -= linesize;
1296 }
1297 #endif
1298 }
1299
1300 /**
1301 \brief setup cacheable range Cache
1302 \details setup Cache range
1303 */
csi_cache_set_range(uint32_t index,uint32_t baseAddr,uint32_t se,uint32_t size,uint32_t enable)1304 __STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t se, \
1305 uint32_t size, uint32_t enable)
1306 {
1307 CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
1308 (_VAL2FLD(CACHE_CRCR_SE, se)) |
1309 (_VAL2FLD(CACHE_CRCR_SIZE, size)) |
1310 (_VAL2FLD(CACHE_CRCR_EN, enable)));
1311 }
1312
1313 /**
1314 \brief Enable cache profile
1315 \details Turns on Cache profile
1316 */
csi_cache_enable_profile(void)1317 __STATIC_INLINE void csi_cache_enable_profile (void)
1318 {
1319 CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
1320 }
1321
1322 /**
1323 \brief Disable cache profile
1324 \details Turns off Cache profile
1325 */
csi_cache_disable_profile(void)1326 __STATIC_INLINE void csi_cache_disable_profile (void)
1327 {
1328 CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
1329 }
1330
1331 /**
1332 \brief Reset cache profile
1333 \details Reset Cache profile
1334 */
csi_cache_reset_profile(void)1335 __STATIC_INLINE void csi_cache_reset_profile (void)
1336 {
1337 CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
1338 }
1339
1340 /**
1341 \brief cache access times
1342 \details Cache access times
1343 \note every 256 access add 1.
1344 \return cache access times, actual times should be multiplied by 256
1345 */
csi_cache_get_access_time(void)1346 __STATIC_INLINE uint32_t csi_cache_get_access_time (void)
1347 {
1348 return CACHE->CPFATR;
1349 }
1350
1351 /**
1352 \brief cache miss times
1353 \details Cache miss times
1354 \note every 256 miss add 1.
1355 \return cache miss times, actual times should be multiplied by 256
1356 */
csi_cache_get_miss_time(void)1357 __STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
1358 {
1359 return CACHE->CPFMTR;
1360 }
1361
1362 /* @} end of CSI_Core_CacheFunctions */
1363
1364 /* ########################## MPU functions #################################### */
1365 /**
1366 \ingroup CSI_Core_FunctionInterface
1367 \defgroup CSI_Core_MPUFunctions MPU Functions
1368 \brief Functions that configure MPU.
1369 @{
1370 */
1371
1372 typedef enum {
1373 REGION_SIZE_4KB = 0xB,
1374 REGION_SIZE_8KB = 0xC,
1375 REGION_SIZE_16KB = 0xD,
1376 REGION_SIZE_32KB = 0xE,
1377 REGION_SIZE_64KB = 0xF,
1378 REGION_SIZE_128KB = 0x10,
1379 REGION_SIZE_256KB = 0x11,
1380 REGION_SIZE_512KB = 0x12,
1381 REGION_SIZE_1MB = 0x13,
1382 REGION_SIZE_2MB = 0x14,
1383 REGION_SIZE_4MB = 0x15,
1384 REGION_SIZE_8MB = 0x16,
1385 REGION_SIZE_16MB = 0x17,
1386 REGION_SIZE_32MB = 0x18,
1387 REGION_SIZE_64MB = 0x19,
1388 REGION_SIZE_128MB = 0x1A,
1389 REGION_SIZE_256MB = 0x1B,
1390 REGION_SIZE_512MB = 0x1C,
1391 REGION_SIZE_1GB = 0x1D,
1392 REGION_SIZE_2GB = 0x1E,
1393 REGION_SIZE_4GB = 0x1F
1394 } region_size_e;
1395
1396 typedef enum {
1397 AP_BOTH_INACCESSIBLE = 0,
1398 AP_SUPER_RW_USER_INACCESSIBLE,
1399 AP_SUPER_RW_USER_RDONLY,
1400 AP_BOTH_RW
1401 } access_permission_e;
1402
1403 typedef struct {
1404 uint32_t nx : 1; /* instruction fetched excution */
1405 access_permission_e ap : 2; /* super user and normal user access. */
1406 uint32_t s : 1; /* security */
1407 } mpu_region_attr_t;
1408
1409 /**
1410 \brief enable mpu.
1411 \details
1412 */
csi_mpu_enable(void)1413 __STATIC_INLINE void csi_mpu_enable(void)
1414 {
1415 __set_CCR(__get_CCR() | CCR_MP_Msk);
1416 }
1417
1418 /**
1419 \brief disable mpu.
1420 \details
1421 */
csi_mpu_disable(void)1422 __STATIC_INLINE void csi_mpu_disable(void)
1423 {
1424 __set_CCR(__get_CCR() & (~CCR_MP_Msk));
1425 }
1426
1427 /**
1428 \brief configure memory protected region.
1429 \details
1430 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1431 \param [in] base_addr base address must be aligned with page size.
1432 \param [in] size \ref region_size_e. memory protected region size.
1433 \param [in] attr \ref region_size_t. memory protected region attribute.
1434 \param [in] enable enable or disable memory protected region.
1435 */
csi_mpu_config_region(uint32_t idx,uint32_t base_addr,region_size_e size,mpu_region_attr_t attr,uint32_t enable)1436 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
1437 mpu_region_attr_t attr, uint32_t enable)
1438 {
1439 if (idx > 7) {
1440 return;
1441 }
1442
1443 CAPR_Type capr;
1444 PACR_Type pacr;
1445 PRSR_Type prsr;
1446
1447 capr.w = __get_CAPR();
1448 pacr.w = __get_PACR();
1449 prsr.w = __get_PRSR();
1450
1451 pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
1452
1453 prsr.b.RID = idx;
1454 __set_PRSR(prsr.w);
1455
1456 if (size != REGION_SIZE_4KB) {
1457 pacr.w &= ~(((1u << (size -11)) - 1) << 12); // 12:byte alignment, 11:byte alignment
1458 }
1459
1460 pacr.b.size = size;
1461
1462 capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24))); // 2:byte, 8:byte, 24:byte
1463 capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | // 2:byte , 8:byte alignment
1464 (attr.s << (idx + 24))); // 24:byte alignment
1465 pacr.w &= ~(((1u << (size -11)) - 1) << 12); // 12:byte alignment, 11:byte alignment
1466 __set_CAPR(capr.w);
1467
1468 pacr.b.E = enable;
1469 __set_PACR(pacr.w);
1470 }
1471
1472 /**
1473 \brief enable mpu region by idx.
1474 \details
1475 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1476 */
csi_mpu_enable_region(uint32_t idx)1477 __STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
1478 {
1479 if (idx > 7) {
1480 return;
1481 }
1482
1483 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
1484 __set_PACR(__get_PACR() | PACR_E_Msk);
1485 }
1486
1487 /**
1488 \brief disable mpu region by idx.
1489 \details
1490 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1491 */
csi_mpu_disable_region(uint32_t idx)1492 __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
1493 {
1494 if (idx > 7) {
1495 return;
1496 }
1497
1498 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | (idx << PRSR_RID_Pos));
1499 __set_PACR(__get_PACR() & (~PACR_E_Msk));
1500 }
1501
1502 /* @} end of CSI_Core_MMUFunctions */
1503
1504 /* ################################## IRQ Functions ############################################ */
1505
1506 /**
1507 \brief Save the Irq context
1508 \details save the psr result before disable irq.
1509 \param [in] irq_num External interrupt number. Value cannot be negative.
1510 */
csi_irq_save(void)1511 __STATIC_INLINE uint32_t csi_irq_save(void)
1512 {
1513 uint32_t result;
1514 result = __get_PSR();
1515 __disable_irq();
1516 return(result);
1517 }
1518
1519 /**
1520 \brief Restore the Irq context
1521 \details restore saved primask state.
1522 \param [in] irq_state psr irq state.
1523 */
csi_irq_restore(uint32_t irq_state)1524 __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
1525 {
1526 __set_PSR(irq_state);
1527 }
1528
1529 /* @} end of IRQ Functions */
1530
1531 /**
1532 \brief System Reset
1533 \details Initiates a system reset request to reset the MCU.
1534 */
csi_system_reset(void)1535 __STATIC_INLINE void csi_system_reset(void)
1536 {
1537 CHR_Type chr;
1538
1539 chr.w = __get_CHR();
1540 #ifdef __RESET_CONST
1541 chr.b.SRST_VAL = __RESET_CONST;
1542 #else
1543 chr.b.SRST_VAL = 0xABCD;
1544 #endif
1545
1546 __DSB(); /* Ensure all outstanding memory accesses included
1547 buffered write are completed before reset */
1548 __set_CHR(chr.w);
1549
1550 __DSB(); /* Ensure completion of memory access */
1551
1552 for (;;) { /* wait until reset */
1553 __NOP();
1554 }
1555 }
1556
1557 /* ################################## Old Interfaces ############################################ */
1558
1559 /* These interfaces are deprecated */
1560 #define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
1561 #define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
1562 #define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
1563 #define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
1564 #define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
1565 #define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
1566 #define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
1567 #define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
1568 #define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
1569 #define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
1570 #define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
1571 #define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
1572 #define NVIC_SystemReset() csi_system_reset()
1573
1574 #define SysTick_Config(ticks) csi_coret_config(ticks, SYS_TICK_IRQn)
1575 #define CORET_Config(ticks) csi_coret_config(ticks, SYS_TICK_IRQn)
1576
1577 #define SCB_EnableICache() csi_icache_enable()
1578 #define SCB_DisableICache() csi_icache_disable()
1579 #define SCB_InvalidateICache() csi_icache_invalid()
1580 #define SCB_EnableDCache() csi_dcache_enable()
1581 #define SCB_DisableDCache() csi_dcache_disable()
1582 #define SCB_InvalidateDCache() csi_dcache_invalid()
1583 #define SCB_CleanDCache() csi_dcache_clean()
1584 #define SCB_CleanInvalidateDCache() csi_dcache_clean_invalid()
1585 #define SCB_InvalidateDCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize)
1586 #define SCB_CleanDCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
1587 #define SCB_CleanInvalidateDCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
1588 #define SCB_Cacheable_Range(index, baseAddr, size, enable) csi_cache_set_range(index, baseAddr, size, enable)
1589 #define SCB_EnableCacheProfile() csi_cache_enable_profile()
1590 #define SCB_DisableCacheProfile() csi_cache_disable_profile()
1591 #define SCB_ResetCacheProfile() csi_cache_reset_profile()
1592 #define SCB_CacheAccessTime() csi_cache_get_access_time()
1593 #define SCB_CacheMissTime() csi_cache_get_miss_time()
1594 #define SCB_EnableCache() csi_icache_enable();csi_dcache_enable()
1595 #define SCB_DisableCache() csi_icache_disable();csi_dcache_disable()
1596 #define SCB_InvalidateCache() csi_icache_invalid();csi_dcache_invalid()
1597 #define SCB_CleanCache() csi_dcache_clean()
1598 #define SCB_CleanInvalidateCache() csi_icache_invalid();csi_dcache_clean();csi_dcache_invalid()
1599 #define SCB_InvalidateCache_by_Addr(addr, dsize) csi_dcache_invalid_range(addr, dsize);csi_icache_invalid()
1600 #define SCB_CleanCache_by_Addr(addr, dsize) csi_dcache_clean_range(addr, dsize)
1601 #define SCB_CleanInvalidateCache_by_Addr(addr, dsize) csi_dcache_clean_invalid_range(addr, dsize)
1602
1603 #ifdef __cplusplus
1604 }
1605 #endif
1606
1607 #endif /* __CORE_804_H_DEPENDANT */
1608
1609 #endif /* __CSI_GENERIC */
1610
1611 #endif