1 /* 2 * Copyright (C) 2022 Beken Corporation 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __CORE_V5_H__ 17 #define __CORE_V5_H__ 18 19 #define MSTATUS_UIE 0x00000001 20 #define MSTATUS_SIE 0x00000002 21 #define MSTATUS_HIE 0x00000004 22 #define MSTATUS_MIE 0x00000008 23 #define MSTATUS_UPIE 0x00000010 24 #define MSTATUS_SPIE 0x00000020 25 #define MSTATUS_HPIE 0x00000040 26 #define MSTATUS_MPIE 0x00000080 27 #define MSTATUS_SPP 0x00000100 28 #define MSTATUS_HPP 0x00000600 29 #define MSTATUS_MPP 0x00001800 30 #define MSTATUS_FS 0x00006000 31 #define MSTATUS_XS 0x00018000 32 #define MSTATUS_MPRV 0x00020000 33 #define MSTATUS_PUM 0x00040000 34 #define MSTATUS_MXR 0x00080000 35 #define MSTATUS_VM 0x1F000000 36 #define MSTATUS32_SD 0x80000000 37 #define MSTATUS64_SD 0x8000000000000000 38 39 #if __riscv_xlen == 64 40 #define MCAUSE_INT 0x8000000000000000UL 41 #define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL 42 #else 43 #define MCAUSE_INT 0x80000000UL 44 #define MCAUSE_CAUSE 0x7FFFFFFFUL 45 #endif 46 47 #define IRQ_S_SOFT 1 48 #define IRQ_H_SOFT 2 49 #define IRQ_M_SOFT 3 50 #define IRQ_S_TIMER 5 51 #define IRQ_H_TIMER 6 52 #define IRQ_M_TIMER 7 53 #define IRQ_S_EXT 9 54 #define IRQ_H_EXT 10 55 #define IRQ_M_EXT 11 56 #define IRQ_COP 12 57 #define IRQ_HOST 13 58 59 /* Machine mode MCAUSE */ 60 #define TRAP_M_I_ACC_FAULT 1 /* Instruction access fault */ 61 #define TRAP_M_L_ACC_FAULT 5 /* Data load access fault */ 62 #define TRAP_M_S_ACC_FAULT 7 /* Data store access fault */ 63 #define TRAP_U_ECALL 8 64 #define TRAP_S_ECALL 9 65 #define TRAP_H_ECALL 10 66 #define TRAP_M_ECALL 11 67 #define TRAP_M_I_PAGE_FAULT 12 /* Instruction page fault */ 68 #define TRAP_M_L_PAGE_FAULT 13 /* Data load page fault */ 69 #define TRAP_M_S_PAGE_FAULT 15 /* Data store page fault */ 70 #define TRAP_M_STACKOVF 32 71 #define TRAP_M_STACKUDF 33 72 #define TRAP_M_USER_ASSERT 0x77 73 #define TRAP_M_USER_NP 0x88 74 #define TRAP_M_USER_OTHER 0x99 75 76 77 /* Supervisor mode SCAUSE */ 78 #define TRAP_S_I_ACC_FAULT 1 /* Instruction access fault */ 79 #define TRAP_S_L_ACC_FAULT 5 /* Data load access fault */ 80 #define TRAP_S_S_ACC_FAULT 7 /* Data store access fault */ 81 #define TRAP_S_I_PAGE_FAULT 12 /* Instruction page fault */ 82 #define TRAP_S_L_PAGE_FAULT 13 /* Data load page fault */ 83 #define TRAP_S_S_PAGE_FAULT 15 /* Data store page fault */ 84 85 #define MIP_SSIP (1 << IRQ_S_SOFT) 86 #define MIP_HSIP (1 << IRQ_H_SOFT) 87 #define MIP_MSIP (1 << IRQ_M_SOFT) 88 #define MIP_STIP (1 << IRQ_S_TIMER) 89 #define MIP_HTIP (1 << IRQ_H_TIMER) 90 #define MIP_MTIP (1 << IRQ_M_TIMER) 91 #define MIP_SEIP (1 << IRQ_S_EXT) 92 #define MIP_HEIP (1 << IRQ_H_EXT) 93 #define MIP_MEIP (1 << IRQ_M_EXT) 94 95 #if __riscv_xlen == 64 96 # define SLL32 sllw 97 # define STORE sd 98 # define LOAD ld 99 # define LWU lwu 100 # define LOG_REGBYTES 3 101 #else 102 # define SLL32 sll 103 # define STORE sw 104 # define LOAD lw 105 # define LWU lw 106 # define LOG_REGBYTES 2 107 #endif 108 #ifndef REGBYTES 109 #define REGBYTES (1 << LOG_REGBYTES) 110 #endif 111 112 #if __riscv_flen == 64 113 # define FPSTORE fsd 114 # define FPLOAD fld 115 # define LOG_FPREGBYTES 3 116 #else 117 # define FPSTORE fsw 118 # define FPLOAD flw 119 # define LOG_FPREGBYTES 2 120 #endif 121 #define FPREGBYTES (1 << LOG_FPREGBYTES) 122 123 #define STR(S) #S 124 #define XSTR(S) STR(S) 125 126 #define PUSH XSTR(STORE) 127 #define POP XSTR(LOAD) 128 #define REGSIZE XSTR(REGBYTES) 129 #define FPPUSH XSTR(FPSTORE) 130 #define FPPOP XSTR(FPLOAD) 131 #define FPREGSIZE XSTR(FPREGBYTES) 132 133 #ifndef __ASSEMBLER__ 134 135 #include <nds_intrinsic.h> 136 137 #define read_csr(reg) __nds__csrr(reg) 138 #define write_csr(reg, val) __nds__csrw(val, reg) 139 #define swap_csr(reg, val) __nds__csrrw(val, reg) 140 #define set_csr(reg, bit) __nds__csrrs(bit, reg) 141 #define clear_csr(reg, bit) __nds__csrrc(bit, reg) 142 143 #endif 144 145 #endif // __CORE_V5_H__ 146