1 // Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdint.h>
16 #include <string.h>
17 #include <stdbool.h>
18
19 #include "esp_attr.h"
20 #include "esp_err.h"
21
22 #include "esp_log.h"
23 #include "esp_system.h"
24
25 #include "esp_rom_uart.h"
26
27 #include "esp_clk_internal.h"
28 #include "esp_rom_efuse.h"
29 #include "esp_rom_sys.h"
30 #include "sdkconfig.h"
31
32 #if CONFIG_IDF_TARGET_ESP32
33 #include "soc/dport_reg.h"
34 #include "esp32/rtc.h"
35 #include "esp32/cache_err_int.h"
36 #include "esp32/rom/cache.h"
37 #include "esp32/rom/rtc.h"
38 #include "esp32/spiram.h"
39 #elif CONFIG_IDF_TARGET_ESP32S2
40 #include "esp32s2/rtc.h"
41 #include "esp32s2/brownout.h"
42 #include "esp32s2/cache_err_int.h"
43 #include "esp32s2/rom/cache.h"
44 #include "esp32s2/rom/rtc.h"
45 #include "esp32s2/spiram.h"
46 #include "esp32s2/dport_access.h"
47 #include "esp32s2/memprot.h"
48 #elif CONFIG_IDF_TARGET_ESP32S3
49 #include "esp32s3/rtc.h"
50 #include "esp32s3/brownout.h"
51 #include "esp32s3/cache_err_int.h"
52 #include "esp32s3/rom/cache.h"
53 #include "esp32s3/rom/rtc.h"
54 #include "esp32s3/spiram.h"
55 #include "esp32s3/dport_access.h"
56 #include "esp32s3/memprot.h"
57 #include "soc/assist_debug_reg.h"
58 #include "soc/cache_memory.h"
59 #include "soc/system_reg.h"
60 #elif CONFIG_IDF_TARGET_ESP32C3
61 #include "esp32c3/rtc.h"
62 #include "esp32c3/cache_err_int.h"
63 #include "esp32c3/rom/cache.h"
64 #include "esp32c3/rom/rtc.h"
65 #include "soc/cache_memory.h"
66 #include "esp32c3/memprot.h"
67 #endif
68
69 #include "bootloader_flash_config.h"
70 #include "esp_private/crosscore_int.h"
71 #include "esp_flash_encrypt.h"
72
73 #include "hal/rtc_io_hal.h"
74 #include "hal/gpio_hal.h"
75 #include "hal/wdt_hal.h"
76 #include "soc/rtc.h"
77 #include "soc/efuse_reg.h"
78 #include "soc/periph_defs.h"
79 #include "soc/cpu.h"
80 #include "soc/rtc.h"
81 #include "soc/spinlock.h"
82
83 #if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX
84 #include "trax.h"
85 #endif
86
87 #include "bootloader_mem.h"
88
89 #if CONFIG_APP_BUILD_TYPE_ELF_RAM
90 #if CONFIG_IDF_TARGET_ESP32
91 #include "esp32/rom/spi_flash.h"
92 #elif CONFIG_IDF_TARGET_ESP32S2
93 #include "esp32s2/rom/spi_flash.h"
94 #elif CONFIG_IDF_TARGET_ESP32S3
95 #include "esp32s3/rom/spi_flash.h"
96 #elif CONFIG_IDF_TARGET_ESP32C3
97 #include "esp32c3/rom/spi_flash.h"
98 #endif
99 #endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
100
101 #include "esp_private/startup_internal.h"
102 #include "esp_private/system_internal.h"
103
104 extern int _bss_start;
105 extern int _bss_end;
106 extern int _rtc_bss_start;
107 extern int _rtc_bss_end;
108
109 extern int _vector_table;
110
111 static const char *TAG = "cpu_start";
112
113 #if CONFIG_IDF_TARGET_ESP32
114 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
115 extern int _ext_ram_bss_start;
116 extern int _ext_ram_bss_end;
117 #endif
118 #ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
119 extern int _iram_bss_start;
120 extern int _iram_bss_end;
121 #endif
122 #endif // CONFIG_IDF_TARGET_ESP32
123
124 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
125 static volatile bool s_cpu_up[SOC_CPU_CORES_NUM] = { false };
126 static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
127
128 static volatile bool s_resume_cores;
129 #endif
130
131 // If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false.
132 bool g_spiram_ok = true;
133
134 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
startup_resume_other_cores(void)135 void startup_resume_other_cores(void)
136 {
137 s_resume_cores = true;
138 }
139
call_start_cpu1(void)140 void IRAM_ATTR call_start_cpu1(void)
141 {
142 cpu_hal_set_vecbase(&_vector_table);
143
144 ets_set_appcpu_boot_addr(0);
145
146 bootloader_init_mem();
147
148 #if CONFIG_ESP_CONSOLE_UART_NONE
149 esp_rom_install_channel_putc(1, NULL);
150 esp_rom_install_channel_putc(2, NULL);
151 #else // CONFIG_ESP_CONSOLE_UART_NONE
152 esp_rom_install_uart_printf();
153 esp_rom_uart_set_as_console(CONFIG_ESP_CONSOLE_UART_NUM);
154 #endif
155
156 #if CONFIG_IDF_TARGET_ESP32
157 DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
158 DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
159 #else
160 REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1);
161 REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1);
162 #endif
163
164 s_cpu_up[1] = true;
165 ESP_EARLY_LOGI(TAG, "App cpu up.");
166
167 //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
168 //has started, but it isn't active *on this CPU* yet.
169 esp_cache_err_int_init();
170
171 #if CONFIG_IDF_TARGET_ESP32
172 #if CONFIG_ESP32_TRAX_TWOBANKS
173 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
174 #endif
175 #endif
176
177 s_cpu_inited[1] = true;
178
179 while (!s_resume_cores) {
180 esp_rom_delay_us(100);
181 }
182
183 SYS_STARTUP_FN();
184 }
185
start_other_core(void)186 static void start_other_core(void)
187 {
188 // If not the single core variant of ESP32 - check this since there is
189 // no separate soc_caps.h for the single core variant.
190 bool is_single_core = false;
191 #if CONFIG_IDF_TARGET_ESP32
192 is_single_core = REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU);
193 #endif
194 if (!is_single_core) {
195 ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
196
197 #if CONFIG_IDF_TARGET_ESP32
198 Cache_Flush(1);
199 Cache_Read_Enable(1);
200 #endif
201 esp_cpu_unstall(1);
202
203 // Enable clock and reset APP CPU. Note that OpenOCD may have already
204 // enabled clock and taken APP CPU out of reset. In this case don't reset
205 // APP CPU again, as that will clear the breakpoints which may have already
206 // been set.
207 #if CONFIG_IDF_TARGET_ESP32
208 if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
209 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
210 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
211 DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
212 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
213 }
214 #elif CONFIG_IDF_TARGET_ESP32S3
215 if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
216 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
217 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
218 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
219 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
220 }
221 #endif
222 ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
223
224 volatile bool cpus_up = false;
225
226 while (!cpus_up) {
227 cpus_up = true;
228 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
229 cpus_up &= s_cpu_up[i];
230 }
231 esp_rom_delay_us(100);
232 }
233 }
234 }
235 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
236
intr_matrix_clear(void)237 static void intr_matrix_clear(void)
238 {
239 for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
240 intr_matrix_set(0, i, ETS_INVALID_INUM);
241 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
242 intr_matrix_set(1, i, ETS_INVALID_INUM);
243 #endif
244 }
245 }
246
247 /*
248 * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
249 * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
250 */
call_start_cpu0(void)251 void IRAM_ATTR call_start_cpu0(void)
252 {
253 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
254 RESET_REASON rst_reas[SOC_CPU_CORES_NUM];
255 #else
256 RESET_REASON rst_reas[1];
257 #endif
258
259 #ifdef __riscv
260 // Configure the global pointer register
261 // (This should be the first thing IDF app does, as any other piece of code could be
262 // relaxed by the linker to access something relative to __global_pointer$)
263 __asm__ __volatile__ (
264 ".option push\n"
265 ".option norelax\n"
266 "la gp, __global_pointer$\n"
267 ".option pop"
268 );
269 #endif
270
271 // Move exception vectors to IRAM
272 cpu_hal_set_vecbase(&_vector_table);
273
274 rst_reas[0] = rtc_get_reset_reason(0);
275 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
276 rst_reas[1] = rtc_get_reset_reason(1);
277 #endif
278
279 #ifndef CONFIG_BOOTLOADER_WDT_ENABLE
280 // from panic handler we can be reset by RWDT or TG0WDT
281 if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
282 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
283 || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
284 #endif
285 ) {
286 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
287 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
288 wdt_hal_disable(&rtc_wdt_ctx);
289 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
290 }
291 #endif
292
293 //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
294 memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
295
296 #if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY)
297 // Clear IRAM BSS
298 memset(&_iram_bss_start, 0, (&_iram_bss_end - &_iram_bss_start) * sizeof(_iram_bss_start));
299 #endif
300
301 /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
302 if (rst_reas[0] != DEEPSLEEP_RESET) {
303 memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
304 }
305
306 #if CONFIG_IDF_TARGET_ESP32S2
307 /* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
308 extern void esp_config_instruction_cache_mode(void);
309 esp_config_instruction_cache_mode();
310
311 /* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache.
312 Configure the mode of data : cache size, cache associated ways, cache line size.
313 Enable data cache, so if we don't use SPIRAM, it just works. */
314 #if CONFIG_SPIRAM_BOOT_INIT
315 extern void esp_config_data_cache_mode(void);
316 esp_config_data_cache_mode();
317 Cache_Enable_DCache(0);
318 #endif
319 #endif
320
321 #if CONFIG_IDF_TARGET_ESP32S3
322 /* Configure the mode of instruction cache : cache size, cache line size. */
323 extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
324 rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
325
326 /* If we need use SPIRAM, we should use data cache.
327 Configure the mode of data : cache size, cache line size.*/
328 Cache_Suspend_DCache();
329 extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
330 rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
331 Cache_Resume_DCache(0);
332 #endif // CONFIG_IDF_TARGET_ESP32S3
333
334 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
335 /* Configure the Cache MMU size for instruction and rodata in flash. */
336 extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
337 extern int _rodata_reserved_start;
338 uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
339 uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
340 Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
341 #endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
342
343 bootloader_init_mem();
344 #if CONFIG_SPIRAM_BOOT_INIT
345 if (esp_spiram_init() != ESP_OK) {
346 #if CONFIG_IDF_TARGET_ESP32
347 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
348 ESP_EARLY_LOGE(TAG, "Failed to init external RAM, needed for external .bss segment");
349 abort();
350 #endif
351 #endif
352
353 #if CONFIG_SPIRAM_IGNORE_NOTFOUND
354 ESP_EARLY_LOGI(TAG, "Failed to init external RAM; continuing without it.");
355 g_spiram_ok = false;
356 #else
357 ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
358 abort();
359 #endif
360 }
361 if (g_spiram_ok) {
362 esp_spiram_init_cache();
363 }
364 #endif
365
366 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
367 s_cpu_up[0] = true;
368 #endif
369
370 ESP_EARLY_LOGI(TAG, "Pro cpu up.");
371
372 #if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
373 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
374 start_other_core();
375 #else
376 ESP_EARLY_LOGI(TAG, "Single core mode");
377 #if CONFIG_IDF_TARGET_ESP32
378 DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); // stop the other core
379 #elif CONFIG_IDF_TARGET_ESP32S3
380 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
381 #endif
382 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
383 #endif // SOC_CPU_CORES_NUM > 1
384
385 #if CONFIG_SPIRAM_MEMTEST
386 if (g_spiram_ok) {
387 bool ext_ram_ok = esp_spiram_test();
388 if (!ext_ram_ok) {
389 ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
390 abort();
391 }
392 }
393 #endif
394
395 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
396 extern void instruction_flash_page_info_init(void);
397 instruction_flash_page_info_init();
398 #endif
399 #if CONFIG_SPIRAM_RODATA
400 extern void rodata_flash_page_info_init(void);
401 rodata_flash_page_info_init();
402 #endif
403
404 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
405 extern void esp_spiram_enable_instruction_access(void);
406 esp_spiram_enable_instruction_access();
407 #endif
408 #if CONFIG_SPIRAM_RODATA
409 extern void esp_spiram_enable_rodata_access(void);
410 esp_spiram_enable_rodata_access();
411 #endif
412
413 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP
414 uint32_t icache_wrap_enable = 0, dcache_wrap_enable = 0;
415 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP
416 icache_wrap_enable = 1;
417 #endif
418 #if CONFIG_ESP32S2_DATA_CACHE_WRAP
419 dcache_wrap_enable = 1;
420 #endif
421 extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable);
422 esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable);
423 #endif
424
425 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
426 memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
427 #endif
428
429 //Enable trace memory and immediately start trace.
430 #if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX
431 #if CONFIG_IDF_TARGET_ESP32
432 #if CONFIG_ESP32_TRAX_TWOBANKS
433 trax_enable(TRAX_ENA_PRO_APP);
434 #else
435 trax_enable(TRAX_ENA_PRO);
436 #endif
437 #elif CONFIG_IDF_TARGET_ESP32S2
438 trax_enable(TRAX_ENA_PRO);
439 #endif
440 trax_start_trace(TRAX_DOWNCOUNT_WORDS);
441 #endif // CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX
442
443 esp_clk_init();
444 esp_perip_clk_init();
445
446 // Now that the clocks have been set-up, set the startup time from RTC
447 // and default RTC-backed system time provider.
448 g_startup_time = esp_rtc_get_time_us();
449
450 intr_matrix_clear();
451
452 #ifdef CONFIG_ESP_CONSOLE_UART
453 uint32_t clock_hz = rtc_clk_apb_freq_get();
454 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
455 clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
456 #endif
457 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
458 esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
459 #endif
460
461 #if SOC_RTCIO_HOLD_SUPPORTED
462 rtcio_hal_unhold_all();
463 #else
464 gpio_hal_force_unhold_all();
465 #endif
466
467 esp_cache_err_int_init();
468
469 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
470 // Memprot cannot be locked during OS startup as the lock-on prevents any PMS changes until a next reboot
471 // If such a situation appears, it is likely an malicious attempt to bypass the system safety setup -> print error & reset
472 if ( esp_memprot_is_locked_any() ) {
473 ESP_EARLY_LOGE(TAG, "Memprot feature locked after the system reset! Potential safety corruption, rebooting.");
474 esp_restart_noos_dig();
475 }
476 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
477 esp_memprot_set_prot(true, true, NULL);
478 #else
479 esp_memprot_set_prot(true, false, NULL);
480 #endif
481 #endif
482
483 bootloader_flash_update_id();
484 // Read the application binary image header. This will also decrypt the header if the image is encrypted.
485 __attribute__((unused)) esp_image_header_t fhdr = {0};
486 #ifdef CONFIG_APP_BUILD_TYPE_ELF_RAM
487 fhdr.spi_mode = ESP_IMAGE_SPI_MODE_DIO;
488 fhdr.spi_speed = ESP_IMAGE_SPI_SPEED_40M;
489 fhdr.spi_size = ESP_IMAGE_FLASH_SIZE_4MB;
490
491 extern void esp_rom_spiflash_attach(uint32_t, bool);
492 esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false);
493 esp_rom_spiflash_unlock();
494 #else
495 // This assumes that DROM is the first segment in the application binary, i.e. that we can read
496 // the binary header through cache by accessing SOC_DROM_LOW address.
497 memcpy(&fhdr, (void *) SOC_DROM_LOW, sizeof(fhdr));
498 #endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
499
500 #if CONFIG_IDF_TARGET_ESP32
501 #if !CONFIG_SPIRAM_BOOT_INIT
502 // If psram is uninitialized, we need to improve some flash configuration.
503 bootloader_flash_clock_config(&fhdr);
504 bootloader_flash_gpio_config(&fhdr);
505 bootloader_flash_dummy_config(&fhdr);
506 bootloader_flash_cs_timing_config();
507 #endif //!CONFIG_SPIRAM_BOOT_INIT
508 #endif //CONFIG_IDF_TARGET_ESP32
509
510 #if CONFIG_SPI_FLASH_SIZE_OVERRIDE
511 int app_flash_size = esp_image_get_flash_size(fhdr.spi_size);
512 if (app_flash_size < 1 * 1024 * 1024) {
513 ESP_LOGE(TAG, "Invalid flash size in app image header.");
514 abort();
515 }
516 bootloader_flash_update_size(app_flash_size);
517 #endif //CONFIG_SPI_FLASH_SIZE_OVERRIDE
518
519 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
520 s_cpu_inited[0] = true;
521
522 volatile bool cpus_inited = false;
523
524 while (!cpus_inited) {
525 cpus_inited = true;
526 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
527 cpus_inited &= s_cpu_inited[i];
528 }
529 esp_rom_delay_us(100);
530 }
531 #endif
532
533 SYS_STARTUP_FN();
534 }
535