1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef _CS1000AUD_SYS_CTRL_H_ 16 #define _CS1000AUD_SYS_CTRL_H_ 17 18 #include "chip.h" 19 20 // ============================================================================= 21 // MACROS 22 // ============================================================================= 23 24 // ============================================================================= 25 // TYPES 26 // ============================================================================= 27 28 // ============================================================================= 29 // CS1000AUD_SYS_CTRL_T 30 // ----------------------------------------------------------------------------- 31 /// 32 // ============================================================================= 33 #define REG_CS1000AUD_SYSCTRL_BASE 0x50010000 34 35 typedef struct { 36 __IO uint32_t CHIP_ID; //0x00000000 37 __IO uint32_t clk_sel; //0x00000004 38 __IO uint32_t pclk_ctrl_mode; //0x00000008 39 __IO uint32_t others_clk_ctrl_mode; //0x0000000C 40 __IO uint32_t pclk_div; //0x00000010 41 __IO uint32_t msadc_clk_div; //0x00000014 42 __IO uint32_t TOUCH_CTRL; //0x00000018 43 __IO uint32_t dcdc_ref_clk_div; //0x0000001C 44 __IO uint32_t dcdc_ref_clk_ctrl0; //0x00000020 45 __IO uint32_t dcdc_ref_clk_ctrl1; //0x00000024 46 __IO uint32_t TPORTS_SEL; //0x00000028 47 __IO uint32_t MEM_CFG; //0x0000002C 48 __IO uint32_t TPORTS_SEL_2; //0x00000030 49 } HWP_CS1000AUD_SYS_CTRL_T; 50 51 static HWP_CS1000AUD_SYS_CTRL_T * const cs1000audSysctrl = ((HWP_CS1000AUD_SYS_CTRL_T *)REG_CS1000AUD_SYSCTRL_BASE); 52 53 54 //CHIP_ID 55 #define CS1000AUD_SYS_CTRL_CHIP_ID(n) (((n)&0xFFFF)<<0) 56 #define CS1000AUD_SYS_CTRL_METAL_ID(n) (((n)&0xFF)<<16) 57 #define CS1000AUD_SYS_CTRL_BOND_ID(n) (((n)&15)<<24) 58 #define CS1000AUD_SYS_CTRL_REV_ID(n) (((n)&15)<<28) 59 60 //clk_sel 61 #define CS1000AUD_SYS_CTRL_CFG_FAST_HWEN (1<<0) 62 #define CS1000AUD_SYS_CTRL_CFG_FAST_CLK_SEL (1<<1) 63 #define CS1000AUD_SYS_CTRL_CFG_CLK_PWM_SEL (1<<2) 64 #define CS1000AUD_SYS_CTRL_CFG_CLK_MSADC_INV_ANA (1<<3) 65 #define CS1000AUD_SYS_CTRL_CFG_CLK_26M_SEL (1<<4) 66 67 //pclk_ctrl_mode 68 #define CS1000AUD_SYS_CTRL_CFG_PCLK_MODE(n) (((n)&0xFFFFFFFF)<<0) 69 70 //others_clk_ctrl_mode 71 #define CS1000AUD_SYS_CTRL_CFG_OTHERS_CLK_MODE(n) (((n)&0xFFFF)<<0) 72 73 //pclk_div 74 #define CS1000AUD_SYS_CTRL_CFG_PCLK_DIV_DENOM(n) (((n)&0xFF)<<0) 75 #define CS1000AUD_SYS_CTRL_CFG_PCLK_DIV_UPDATE (1<<8) 76 77 //msadc_clk_div 78 #define CS1000AUD_SYS_CTRL_CFG_CLK_MSADC_DIV_DENOM(n) (((n)&0xFF)<<0) 79 #define CS1000AUD_SYS_CTRL_CFG_CLK_MSADC_DIV_UPDATE (1<<8) 80 81 //TOUCH_CTRL 82 #define CS1000AUD_SYS_CTRL_CFG_CLK_TOUCH_DIV_MODE(n) (((n)&3)<<0) 83 84 //dcdc_ref_clk_div 85 #define CS1000AUD_SYS_CTRL_CFG_DCDC_REF_CLK_DIV_DENOM(n) (((n)&0xFF)<<0) 86 #define CS1000AUD_SYS_CTRL_CFG_DCDC_REF_CLK_DIV_UPDATA (1<<8) 87 #define CS1000AUD_SYS_CTRL_CFG_DCDC_RF_TX_ON_EN (1<<9) 88 #define CS1000AUD_SYS_CTRL_CFG_DCDC_RF_RX_ON_EN (1<<10) 89 #define CS1000AUD_SYS_CTRL_CFG_DCDC_PU_MDLL_EN (1<<11) 90 #define CS1000AUD_SYS_CTRL_CFG_DCDC_REF_CLK_DIV_DENOM_EXT(n) (((n)&0xFF)<<12) 91 92 //dcdc_ref_clk_ctrl0 93 #define CS1000AUD_SYS_CTRL_CFG_DCDC_REF_CLK_TRIANGLE_CYCLE(n) (((n)&0xFFFF)<<0) 94 #define CS1000AUD_SYS_CTRL_CFG_DCDC_REF_CLK_TRIANGLE_AMP(n) (((n)&3)<<16) 95 #define CS1000AUD_SYS_CTRL_CFG_DCDC_REF_CLK_TRIANGLE_EN (1<<18) 96 97 //dcdc_ref_clk_ctrl1 98 #define CS1000AUD_SYS_CTRL_CFG_DCDC_RF_OFFSET(n) (((n)&15)<<0) 99 #define CS1000AUD_SYS_CTRL_CFG_DCDC_PA_OFFSET(n) (((n)&15)<<4) 100 #define CS1000AUD_SYS_CTRL_CFG_DCDC_CORE_OFFSET(n) (((n)&15)<<8) 101 #define CS1000AUD_SYS_CTRL_CFG_DCDC_RF_CLK_EN (1<<12) 102 #define CS1000AUD_SYS_CTRL_CFG_DCDC_PA_CLK_EN (1<<13) 103 #define CS1000AUD_SYS_CTRL_CFG_DCDC_CORE_CLK_EN (1<<14) 104 #define CS1000AUD_SYS_CTRL_CFG_DCDC_RF_CLK_HWEN (1<<15) 105 #define CS1000AUD_SYS_CTRL_CFG_DCDC_PA_CLK_HWEN (1<<16) 106 #define CS1000AUD_SYS_CTRL_CFG_DCDC_CORE_CLK_HWEN (1<<17) 107 #define CS1000AUD_SYS_CTRL_CFG_DCDC_RF_DIV(n) (((n)&3)<<18) 108 #define CS1000AUD_SYS_CTRL_CFG_DCDC_PA_DIV(n) (((n)&3)<<20) 109 #define CS1000AUD_SYS_CTRL_CFG_DCDC_CORE_DIV(n) (((n)&3)<<22) 110 111 //TPORTS_SEL 112 #define CS1000AUD_SYS_CTRL_CFG_TOP_TPORTS_SEL(n) (((n)&0xFF)<<0) 113 #define CS1000AUD_SYS_CTRL_CFG_CLK_TPORTS_SEL(n) (((n)&15)<<8) 114 115 //MEM_CFG 116 #define CS1000AUD_SYS_CTRL_CFG_MEM(n) (((n)&0xFFFF)<<0) 117 118 //TPORTS_SEL_2 119 #define CS1000AUD_SYS_CTRL_CFG_TOP_TPORTS_SEL_2(n) (((n)&0xFFFFFFFF)<<0) 120 121 #endif 122