1 /* 2 * Allwinner SoCs display driver. 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9 /****************************************************************************** 10 * All Winner Tech, All Right Reserved. 2014-2015 Copyright (c) 11 * 12 * File name : de_enhance.h 13 * 14 * Description : display engine 2.0 enhance basic function declaration 15 * 16 * History : 2014/04/02 vito cheng v0.1 Initial version 17 * 2014/04/29 vito cheng v0.2 Add disp_enhance_config_data 18 * struct delcaration 19 ******************************************************************************/ 20 21 #ifndef _DE_ENHANCE_H_ 22 #define _DE_ENHANCE_H_ 23 24 #include "../../include.h" 25 #include "de_fce_type.h" 26 #include "de_peak_type.h" 27 #include "de_lti_type.h" 28 #include "de_dns_type.h" 29 #include "de_fcc_type.h" 30 #include "de_bls_type.h" 31 #include "de_csc_table.h" 32 #include "de_vsu.h" 33 34 /* 8K for enahnce reg mem */ 35 #define DE_DNS_REG_MEM_SIZE (0x400) 36 #define DE_FCC_REG_MEM_SIZE (0x800) 37 #define DE_BLS_REG_MEM_SIZE (0x400) 38 #define DE_LTI_REG_MEM_SIZE (0x400) 39 #define DE_PEAK_REG_MEM_SIZE (0x400) 40 #define DE_FCE_REG_MEM_SIZE (0x800) 41 #define DE_ENHANCE_REG_MEM_SIZE \ 42 (DE_DNS_REG_MEM_SIZE + DE_FCC_REG_MEM_SIZE \ 43 + DE_BLS_REG_MEM_SIZE + DE_LTI_REG_MEM_SIZE \ 44 + DE_PEAK_REG_MEM_SIZE + DE_FCE_REG_MEM_SIZE) 45 46 #define MODE_NUM 4 47 #define PARA_NUM 6 48 #define FORMAT_NUM 2 49 #define ENHANCE_MODE_NUM 3 50 51 #define ENHANCE_MIN_OVL_WIDTH 32 52 #define ENHANCE_MIN_OVL_HEIGHT 32 53 #define ENHANCE_MIN_BLD_WIDTH 32 54 #define ENHANCE_MIN_BLD_HEIGHT 4 55 56 #define FCE_OFST 0x70000 /* FCE offset based on RTMX */ 57 #define PEAK_OFST 0x70800 /* PEAKING offset based on RTMX */ 58 #define LTI_OFST 0x71000 /* LTI offset based on RTMX */ 59 #define BLS_OFST 0x71800 /* BLS offset based on RTMX */ 60 #define FCC_OFST 0x72000 /* FCC offset based on RTMX */ 61 #define DNS_OFST 0x80000 /* DNS offset based on RTMX */ 62 #define PEAK2D_OFST 0x30 /* PEAK2D offset based on VSU */ 63 64 /* vep bypass mask */ 65 #define USER_BYPASS 0x00000001 66 #define USER_BYPASS_MASK 0xfffffffe 67 #define SIZE_BYPASS 0x00000002 68 #define SIZE_BYPASS_MASK 0xfffffffd 69 #define LAYER_BYPASS 0x00000004 70 #define LAYER_BYPASS_MASK 0xfffffffb 71 72 #define DE_CLIP(x, low, high) max(low, min(x, high)) 73 74 struct disp_enhance_layer_info { 75 /* layer framebuffer size width/height */ 76 struct disp_rectsz fb_size; 77 /* layer framebuffer crop retangle, don't care w/h at all */ 78 struct disp_rect fb_crop; 79 /* layer enable */ 80 u32 en; 81 /* layer format */ 82 u32 format; 83 }; 84 85 struct disp_enhance_chn_info { 86 /* overlay size (scale in size) */ 87 /* CAUTION: overlay size can be the output size of */ 88 /* video overlay/ de-interlace overlay/ FBD overlay */ 89 struct disp_rectsz ovl_size; 90 /* bld size (scale out size) */ 91 struct disp_rectsz bld_size; 92 /* layer info */ 93 struct disp_enhance_layer_info layer_info[MAX_LAYER_NUM_PER_CHN]; 94 }; 95 96 /* parameters of vep module */ 97 struct vep_para { 98 enum disp_manager_dirty_flags flags; 99 struct __fce_config_data fce_para; 100 struct __lti_config_data lti_para; 101 struct __peak_config_data peak_para; 102 struct __bls_config_data bls_para; 103 struct __fcc_config_data fcc_para; 104 struct __dns_config_data dns_para; 105 struct de_vsu_sharp_config peak2d_para; 106 u32 demo_enable; 107 u32 bypass; 108 u32 dev_type; 109 u32 fmt; 110 }; 111 112 /* system configuration of vep */ 113 struct vep_config_info { 114 u32 device_num; 115 u32 vep_num[DE_NUM]; 116 u32 dns_exist[DE_NUM][VI_CHN_NUM]; 117 u32 peak2d_exist[DE_NUM][VI_CHN_NUM]; 118 }; 119 120 /* algorithm variable */ 121 struct vep_alg_var { 122 u32 frame_cnt; 123 }; 124 125 /* peak function declaration */ 126 s32 de_peak_init(u32 disp, u32 chn, uintptr_t reg_base, 127 u8 __iomem **phy_addr, u8 **vir_addr, u32 *size); 128 s32 de_peak_exit(u32 disp, u32 chn); 129 s32 de_peak_get_reg_blocks(u32 disp, u32 chn, 130 struct de_reg_block **blks, u32 *blk_num); 131 s32 de_peak_enable(u32 disp, u32 chn, u32 en); 132 s32 de_peak_set_size(u32 disp, u32 chn, u32 width, 133 u32 height); 134 s32 de_peak_set_window(u32 disp, u32 chn, 135 u32 win_enable, struct de_rect_o window); 136 s32 de_peak_init_para(u32 disp, u32 chn); 137 s32 de_peak_info2para(u32 disp, u32 chn, 138 u32 fmt, u32 dev_type, 139 struct __peak_config_data *para, u32 bypass); 140 141 /* /LTI function declaration */ 142 s32 de_lti_init(u32 disp, u32 chn, uintptr_t reg_base, 143 u8 __iomem **phy_addr, u8 **vir_addr, u32 *size); 144 s32 de_lti_exit(u32 disp, u32 chn); 145 s32 de_lti_get_reg_blocks(u32 disp, u32 chn, 146 struct de_reg_block **blks, u32 *blk_num); 147 s32 de_lti_enable(u32 disp, u32 chn, u32 en); 148 s32 de_lti_set_size(u32 disp, u32 chn, u32 width, 149 u32 height); 150 s32 de_lti_set_window(u32 disp, u32 chn, 151 u32 win_enable, struct de_rect_o window); 152 s32 de_lti_init_para(u32 disp, u32 chn); 153 s32 de_lti_info2para(u32 disp, u32 chn, 154 u32 fmt, u32 dev_type, 155 struct __lti_config_data *para, u32 bypass); 156 157 /* FCE function declaration */ 158 s32 de_fce_init(u32 disp, u32 chn, uintptr_t reg_base, 159 u8 __iomem **phy_addr, u8 **vir_addr, u32 *size); 160 s32 de_fce_exit(u32 disp, u32 chn); 161 s32 de_fce_get_reg_blocks(u32 disp, u32 chn, 162 struct de_reg_block **blks, u32 *blk_num); 163 s32 de_fce_enable(u32 disp, u32 chn, u32 en); 164 s32 de_fce_set_size(u32 disp, u32 chn, u32 width, 165 u32 height); 166 s32 de_fce_set_window(u32 disp, u32 chn, 167 u32 win_enable, struct de_rect_o window); 168 s32 de_fce_init_para(u32 disp, u32 chn); 169 s32 de_fce_info2para(u32 disp, u32 chn, 170 u32 fmt, u32 dev_type, 171 struct __fce_config_data *para, u32 bypass); 172 s32 de_hist_tasklet(u32 disp, u32 chn, 173 u32 frame_cnt); 174 s32 de_ce_tasklet(u32 disp, u32 chn, 175 u32 frame_cnt); 176 s32 de_fce_set_icsc_coeff(u32 disp, u32 chn, 177 struct de_csc_info *in_info, struct de_csc_info *out_info); 178 179 /* BLS function declaration */ 180 s32 de_bls_init(u32 disp, u32 chn, uintptr_t reg_base, 181 u8 __iomem **phy_addr, u8 **vir_addr, u32 *size); 182 s32 de_bls_enable(u32 disp, u32 chn, u32 en); 183 s32 de_bls_exit(u32 disp, u32 chn); 184 s32 de_bls_get_reg_blocks(u32 disp, u32 chn, 185 struct de_reg_block **blks, u32 *blk_num); 186 s32 de_bls_set_size(u32 disp, u32 chn, u32 width, 187 u32 height); 188 s32 de_bls_set_window(u32 disp, u32 chn, 189 u32 win_enable, struct de_rect_o window); 190 s32 de_bls_init_para(u32 disp, u32 chn); 191 s32 de_bls_info2para(u32 disp, u32 chn, 192 u32 fmt, u32 dev_type, 193 struct __bls_config_data *para, u32 bypass); 194 195 /* FCC function declaration */ 196 s32 de_fcc_init(u32 disp, u32 chn, uintptr_t reg_base, 197 u8 __iomem **phy_addr, u8 **vir_addr, u32 *size); 198 s32 de_fcc_exit(u32 disp, u32 chn); 199 s32 de_fcc_get_reg_blocks(u32 disp, u32 chn, 200 struct de_reg_block **blks, u32 *blk_num); 201 s32 de_fcc_enable(u32 disp, u32 chn, u32 en); 202 s32 de_fcc_set_size(u32 disp, u32 chn, u32 width, u32 height); 203 s32 de_fcc_set_window(u32 disp, u32 chn, u32 win_en, 204 struct de_rect_o window); 205 s32 de_fcc_init_para(u32 disp, u32 chn); 206 s32 de_fcc_info2para(u32 disp, u32 chn, u32 fmt, 207 u32 dev_type, struct __fcc_config_data *para, 208 u32 bypass); 209 s32 de_fcc_set_icsc_coeff(u32 disp, u32 chn, 210 struct de_csc_info *in_info, struct de_csc_info *out_info); 211 s32 de_fcc_set_ocsc_coeff(u32 disp, u32 chn, 212 struct de_csc_info *in_info, struct de_csc_info *out_info); 213 214 215 /* DNS function declaration */ 216 s32 de_dns_init(u32 disp, u32 chn, uintptr_t reg_base, 217 u8 __iomem **phy_addr, u8 **vir_addr, u32 *size); 218 s32 de_dns_exit(u32 disp, u32 chn); 219 s32 de_dns_get_reg_blocks(u32 disp, u32 chn, 220 struct de_reg_block **blks, u32 *blk_num); 221 s32 de_dns_enable(u32 disp, u32 chn, u32 en); 222 s32 de_dns_set_size(u32 disp, u32 chn, u32 width, 223 u32 height); 224 s32 de_dns_set_window(u32 disp, u32 chn, 225 u32 win_enable, struct de_rect_o window); 226 s32 de_dns_init_para(u32 disp, u32 chn); 227 s32 de_dns_info2para(u32 disp, u32 chn, 228 u32 fmt, u32 dev_type, 229 struct __dns_config_data *para, u32 bypass); 230 s32 de_dns_tasklet(u32 disp, u32 chn, 231 u32 frame_cnt); 232 233 /* ENHANCE function declaration */ 234 s32 de_enhance_update_regs(u32 disp); 235 s32 de_enhance_init(struct disp_bsp_init_para *para); 236 s32 de_enhance_exit(void); 237 s32 de_enhance_get_reg_blocks(u32 disp, 238 struct de_reg_block **blk, u32 *blk_num); 239 s32 de_enhance_layer_apply(u32 disp, 240 struct disp_enhance_chn_info *info); 241 s32 de_enhance_apply(u32 disp, 242 struct disp_enhance_config *config); 243 s32 de_enhance_sync(u32 disp); 244 s32 de_enhance_tasklet(u32 disp); 245 246 /* module public function declaration */ 247 void de_set_bits(u32 *reg_addr, u32 bits_val, 248 u32 shift, u32 width); 249 250 #endif /* #ifndef _DE_ENHANCE_H_ */ 251