1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 // 15 #pragma once 16 17 #include <driver/int_types.h> 18 #include <common/bk_include.h> 19 #include <driver/hal/hal_aud_types.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 26 typedef void (*aud_isr_t)(void *param); 27 28 29 /** 30 * @brief AUD defines 31 * @defgroup bk_api_aud_defs macos 32 * @ingroup bk_api_aud 33 * @{ 34 */ 35 36 #define BK_ERR_AUD_NOT_INIT (BK_ERR_AUD_BASE - 1) /**< AUD driver not init */ 37 #define BK_ERR_AUD_ISR_ID (BK_ERR_AUD_BASE - 2) /**< AUD isr id is invalid */ 38 #define BK_ERR_AUD_ADC_MODE (BK_ERR_AUD_BASE - 3) /**< AUD adc work mode is invalid */ 39 40 #define AUD_HAL_REG_BASE AUD_LL_REG_BASE 41 #define AUD_DAC_FIFO_ADDR (AUD_HAL_REG_BASE + 0x33 * 4) 42 43 /** 44 * @} 45 */ 46 47 /** 48 * @brief AUD enum defines 49 * @defgroup bk_api_aud_enum AUD enums 50 * @ingroup bk_api_aud 51 * @{ 52 */ 53 54 typedef enum { 55 AUD_ISR_DTMF = 0, /**< dtmf_int_en */ 56 AUD_ISR_ADCL, /**< adcl_int_en */ 57 AUD_ISR_DACR, /**< dacr_int_en */ 58 AUD_ISR_DACL, /**< dacl_int_en */ 59 AUD_ISR_MAX /**< AUD isr id max */ 60 } aud_isr_id_t; 61 62 typedef enum { 63 AUD_ADC_WORK_MODE_NULL = 0, /**< no mode */ 64 AUD_ADC_WORK_MODE_ADC, /**< ADC mode */ 65 AUD_ADC_WORK_MODE_DTMF, /**< DTMF mode */ 66 AUD_ADC_WORK_MODE_MAX, 67 } aud_adc_work_mode_t; 68 69 typedef enum { 70 AUD_ADC_SAMP_RATE_8K = 0, /**< ADC sample rate : 8k */ 71 AUD_ADC_SAMP_RATE_16K, /**< ADC sample rate : 16k */ 72 AUD_ADC_SAMP_RATE_44K, /**< ADC sample rate : 44.1k */ 73 AUD_ADC_SAMP_RATE_48K, /**< ADC sample rate : 48k */ 74 AUD_ADC_SAMP_RATE_MAX, 75 } aud_adc_samp_rate_t; 76 77 typedef enum { 78 AUD_ADC_HPF_BYPASS_DISABLE = 0, /**< AUD ADC hpf bypass disable */ 79 AUD_ADC_HPF_BYPASS_ENABLE, /**< AUD ADC hpf bypass enable */ 80 AUD_ADC_HPF_BYPASS_MAX, 81 } aud_adc_hpf_bypass_t; 82 83 typedef enum { 84 AUD_ADC_SAMP_EDGE_RISING = 0, /**< AUD ADC sampling clock edge : rising edge */ 85 AUD_ADC_SAMP_EDGE_FALLING, /**< AUD ADC sampling clock edge : falling edge */ 86 AUD_ADC_SAMP_EDGE_MAX, 87 } aud_adc_samp_edge_t; 88 89 typedef enum { 90 AUD_ADCL_INT_DISABLE = 0, /**< AUD ADCL interrupt disable */ 91 AUD_ADCL_INT_ENABLE, /**< AUD ADCL interrupt enable */ 92 AUD_ADCL_INT_MAX, 93 } aud_adcl_int_t; 94 95 typedef enum { 96 AUD_DTMF_INT_DISABLE = 0, /**< AUD DTMF interrupt disable */ 97 AUD_DTMF_INT_ENABLE, /**< AUD DTMF interrupt enable */ 98 AUD_DTMF_INT_MAX, 99 } aud_dtmf_int_t; 100 101 typedef enum { 102 AUD_LOOP_ADC2DAC_DISABLE = 0, /**< ADC to DAC loop test disable */ 103 AUD_LOOP_ADC2DAC_ENABLE, /**< ADC to DAC loop test enable */ 104 AUD_LOOP_ADC2DAC_MAX, 105 } aud_loop_adc2dac_t; 106 107 typedef enum { 108 AUD_LOOP_DTMF2DAC_DISABLE = 0, /**< DTMF to DAC loop test disable */ 109 AUD_LOOP_DTMF2DAC_ENABLE, /**< DTMF to DAC loop test enable */ 110 AUD_LOOP_DTMF2DAC_MAX, 111 } aud_loop_dtmf2dac_t; 112 113 typedef enum { 114 AUD_AGC_NG_DISABLE = 0, /**< disable noise gating */ 115 AUD_AGC_NG_ENABLE, /**< enable noise gating */ 116 AUD_AGC_NG_MAX, 117 } aud_agc_ng_enable_t; 118 119 typedef enum { 120 AUD_AGC_NG_METHOD_MUTE = 0, /**< mute or demute : default */ 121 AUD_AGC_NG_METHOD_CREASE, /**< gradually increase or decrease gac */ 122 AUD_AGC_NG_METHOD_MAX, 123 } aud_agc_method_t; 124 125 typedef enum { 126 AUD_AGC_DECAY_TIME_128 = 0, /**< AGC decay time :128 2.7ms */ 127 AUD_AGC_DECAY_TIME_256, /**< AGC decay time :256 */ 128 AUD_AGC_DECAY_TIME_512, /**< AGC decay time :512 */ 129 AUD_AGC_DECAY_TIME_1024, /**< AGC decay time :1024 */ 130 AUD_AGC_DECAY_TIME_2048, /**< AGC decay time :2048 */ 131 AUD_AGC_DECAY_TIME_4096, /**< AGC decay time :4096 */ 132 AUD_AGC_DECAY_TIME_8192, /**< AGC decay time :8192 */ 133 AUD_AGC_DECAY_TIME_16384, /**< AGC decay time :16384 340ms*/ 134 AUD_AGC_DECAY_TIME_MAX, 135 } aud_agc_decay_time_t; 136 137 typedef enum { 138 AUD_AGC_ATTACK_TIME_8 = 0, /**< AGC attack time :8 0.1667ms */ 139 AUD_AGC_ATTACK_TIME_16, /**< AGC attack time :16 */ 140 AUD_AGC_ATTACK_TIME_32, /**< AGC attack time :32 */ 141 AUD_AGC_ATTACK_TIME_64, /**< AGC attack time :64 */ 142 AUD_AGC_ATTACK_TIME_128, /**< AGC attack time :128 */ 143 AUD_AGC_ATTACK_TIME_256, /**< AGC attack time :256 */ 144 AUD_AGC_ATTACK_TIME_512, /**< AGC attack time :512 */ 145 AUD_AGC_ATTACK_TIME_1024, /**< AGC attack time :1024 21 ms*/ 146 AUD_AGC_ATTACK_TIME_MAX, 147 } aud_agc_attack_time_t; 148 149 typedef enum { 150 AUD_AGC_IIR_COEF_1_32 = 0, /**< AGC IRR coefficient : 1/32 */ 151 AUD_AGC_IIR_COEF_1_64, /**< AGC IRR coefficient : 1/64 */ 152 AUD_AGC_IIR_COEF_1_128, /**< AGC IRR coefficient : 1/128 */ 153 AUD_AGC_IIR_COEF_1_256, /**< AGC IRR coefficient : 1/256 */ 154 AUD_AGC_IIR_COEF_1_512, /**< AGC IRR coefficient : 1/512 */ 155 AUD_AGC_IIR_COEF_1_1024, /**< AGC IRR coefficient : 1/1024 */ 156 AUD_AGC_IIR_COEF_1_2048, /**< AGC IRR coefficient : 1/2048 */ 157 AUD_AGC_IIR_COEF_1_4096, /**< AGC IRR coefficient : 1/4096 */ 158 AUD_AGC_IIR_COEF_MAX, 159 } aud_agc_iir_coef_t; 160 161 typedef enum { 162 AUD_AGC_DISABLE = 0, /**< disable AGC */ 163 AUD_AGC_ENABLE, /**< enable AGC */ 164 AUD_AGC_MAX, 165 } aud_agc_enable_t; 166 167 typedef enum { 168 AUD_GAC_MANUAL_PGA_DISABLE = 0, /**< disable AGC manual set pga */ 169 AUD_GAC_MANUAL_PGA_ENABLE, /**< enable AGC manual set pga */ 170 AUD_GAC_MANUAL_PGA_MAX, 171 } aud_agc_manual_pga_en_t; 172 173 typedef enum { 174 AUD_ADC_DISABLE = 0, /**< disable adc */ 175 AUD_ADC_ENABLE, /**< enable adc */ 176 AUD_ADC_ENABLE_MAX, 177 } aud_adc_enable_t; 178 179 typedef enum { 180 AUD_ADC_LINE_DISABLE = 0, /**< disable line in */ 181 AUD_ADC_LINE_ENABLE, /**< enable line in */ 182 AUD_ADC_LINE_ENABLE_MAX, 183 } aud_adc_line_enable_t; 184 185 typedef enum { 186 AUD_MIC_DISABLE = 0, /**< disable all mic */ 187 AUD_MIC_MIC1_ENABLE, /**< enable mic1 */ 188 AUD_MIC_MIC2_ENABLE, /**< enable mic2 */ 189 AUD_MIC_ALL_ENABLE, /**< enable all mic */ 190 AUD_MIC_MAX, 191 } aud_mic_enable_t; 192 193 typedef enum { 194 AUD_GAC_NOISE_TOUT_0 = 0, /**< AGC noise tout: 0 0ms */ 195 AUD_GAC_NOISE_TOUT_4, /**< AGC noise tout: 4 0.5ms */ 196 AUD_GAC_NOISE_TOUT_8, /**< AGC noise tout: 8 */ 197 AUD_GAC_NOISE_TOUT_16, /**< AGC noise tout: 16 */ 198 AUD_GAC_NOISE_TOUT_32, /**< AGC noise tout: 32 */ 199 AUD_GAC_NOISE_TOUT_64, /**< AGC noise tout: 64 */ 200 AUD_GAC_NOISE_TOUT_128, /**< AGC noise tout: 128 */ 201 AUD_GAC_NOISE_TOUT_256, /**< AGC noise tout: 256 32ms */ 202 AUD_GAC_NOISE_TOUT_MAX, 203 } aud_gac_noise_tout_t; 204 205 typedef enum { 206 AUD_GAC_HIGH_DUR_0 = 0, /**< AGC 0 ms，as soon as MIC_RSSI value higher than NOISE_HIGH，Noise gating work，leave off noise status */ 207 AUD_GAC_HIGH_DUR_4, /**< AGC high duration: 4 0.5ms*/ 208 AUD_GAC_HIGH_DUR_8, /**< AGC high duration: 8 */ 209 AUD_GAC_HIGH_DUR_16, /**< AGC high duration: 16 */ 210 AUD_GAC_HIGH_DUR_32, /**< AGC high duration: 32 */ 211 AUD_GAC_HIGH_DUR_64, /**< AGC high duration: 64 */ 212 AUD_GAC_HIGH_DUR_128, /**< AGC high duration: 128 */ 213 AUD_GAC_HIGH_DUR_256, /**< AGC high duration: 256 32ms */ 214 AUD_GAC_HIGH_DUR_MAX, 215 } aud_gac_high_dur_t; 216 217 typedef enum { 218 AUD_GAC_LOW_DUR_0 = 0, /**< AGC 0 ms，as soon as MIC_RSSI value lower than NOISE_HIGH，Noise gating work，leave off noise status */ 219 AUD_GAC_LOW_DUR_4, /**< AGC low duration: 4 0.5ms*/ 220 AUD_GAC_LOW_DUR_8, /**< AGC low duration: 8 */ 221 AUD_GAC_LOW_DUR_16, /**< AGC low duration: 16 */ 222 AUD_GAC_LOW_DUR_32, /**< AGC low duration: 32 */ 223 AUD_GAC_LOW_DUR_64, /**< AGC low duration: 64 */ 224 AUD_GAC_LOW_DUR_128, /**< AGC low duration: 128 */ 225 AUD_GAC_LOW_DUR_256, /**< AGC low duration: 256 32ms */ 226 AUD_GAC_LOW_DUR_MAX, 227 } aud_gac_low_dur_t; 228 229 230 /* DTMF */ 231 232 typedef enum { 233 AUD_DTMF_DISABLE = 0, /**< disable dtmf */ 234 AUD_DTMF_ENABLE, /**< enable dtmf */ 235 AUD_DTMF_ENABLE_MAX, 236 } aud_dtmf_enable_t; 237 238 typedef enum { 239 AUD_DTMF_TONE_PATTERN_DTMF = 0, /**< 0: DTMF(Active_Time) + Zeros(Pause_Time) */ 240 AUD_DTMF_TONE_PATTERN_TONE, /**< 1：Tone1(Active_Time) + Tone2(Pause_Time) */ 241 AUD_DTMF_TONE_PATTERN_MAX, 242 } aud_dtmf_tone_pattern_t; 243 244 typedef enum { 245 AUD_DTMF_TONE_MODE_SIGNAL = 0, /**< 0：signal mode */ 246 AUD_DTMF_TONE_MODE_CONTIUS, /**< 1：continuous mode */ 247 AUD_DTMF_TONE_MODE_MAX, 248 } aud_dtmf_tone_mode_t; 249 250 typedef enum { 251 AUD_DTMF_TONE_ATTU_MINUS_1 = 0, /**< Tone1 damp set: -1 db */ 252 AUD_DTMF_TONE_ATTU_MINUS_2, /**< Tone1 damp set: -2 db */ 253 AUD_DTMF_TONE_ATTU_MINUS_3, /**< Tone1 damp set: -3 db */ 254 AUD_DTMF_TONE_ATTU_MINUS_4, /**< Tone1 damp set: -4 db */ 255 AUD_DTMF_TONE_ATTU_MINUS_5, /**< Tone1 damp set: -5 db */ 256 AUD_DTMF_TONE_ATTU_MINUS_6, /**< Tone1 damp set: -6 db */ 257 AUD_DTMF_TONE_ATTU_MINUS_7, /**< Tone1 damp set: -7 db */ 258 AUD_DTMF_TONE_ATTU_MINUS_8, /**< Tone1 damp set: -8 db */ 259 AUD_DTMF_TONE_ATTU_MINUS_9, /**< Tone1 damp set: -9 db */ 260 AUD_DTMF_TONE_ATTU_MINUS_10, /**< Tone1 damp set: -10 db */ 261 AUD_DTMF_TONE_ATTU_MINUS_11, /**< Tone1 damp set: -11 db */ 262 AUD_DTMF_TONE_ATTU_MINUS_12, /**< Tone1 damp set: -12 db */ 263 AUD_DTMF_TONE_ATTU_MINUS_13, /**< Tone1 damp set: -13 db */ 264 AUD_DTMF_TONE_ATTU_MINUS_14, /**< Tone1 damp set: -14 db */ 265 AUD_DTMF_TONE_ATTU_MINUS_15, /**< Tone1 damp set: -15 db */ 266 AUD_DTMF_TONE_ATTU_MINUS_MAX, 267 } aud_dtmf_tone_attu_t; 268 269 typedef enum { 270 AUD_DTMF_TONE_DISABLE = 0, /**< 0：disable tone */ 271 AUD_DTMF_TONE_ENABLE, /**< 1：enable tone */ 272 AUD_DTMF_TONE_ENABLE_MAX, 273 } aud_dtmf_tone_enable_t; 274 275 typedef enum { 276 AUD_ADC_TRACMOD_MANUAL_DISABLE = 0, /**< 0：disable ADC fractional frequency division of manual set */ 277 AUD_ADC_TRACMOD_MANUAL_ENABLE, /**< 1：enable ADC fractional frequency division of manual set */ 278 AUD_ADC_TRACMOD_MANUAL_EN_MAX, 279 } aud_adc_fracmod_manual_en_t; 280 281 /**dac enum */ 282 typedef enum { 283 AUD_DAC_DISABLE = 0, /**< 0：disable dac */ 284 AUD_DAC_ENABLE, /**< 1：enable dac */ 285 AUD_DAC_OTHERS, 286 } aud_dac_enable_t; 287 288 typedef enum { 289 AUD_DAC_CHL_DISABLE = 0, /**< disable all dac channel */ 290 AUD_DAC_CHL_L_ENABLE, /**< enable dac left channel */ 291 AUD_DAC_CHL_R_ENABLE, /**< enable dac right channel */ 292 AUD_DAC_CHL_LR_ENABLE, /**< enable dac left and right channel */ 293 AUD_DAC_CHL_MAX, 294 } aud_dac_chl_enable_t; 295 296 typedef enum { 297 AUD_DAC_WORK_MODE_SIGNAL_END = 0, 298 AUD_DAC_WORK_MODE_DIFFEN, 299 AUD_DAC_WORK_MODE_MAX, 300 } aud_dac_work_mode_t; 301 302 typedef enum { 303 AUD_DAC_SAMP_RATE_8K = 0, /**< DAC sample rate : 8k */ 304 AUD_DAC_SAMP_RATE_11_025K, /**< DAC sample rate : 11.025k */ 305 AUD_DAC_SAMP_RATE_12K, /**< DAC sample rate : 12k */ 306 AUD_DAC_SAMP_RATE_16K, /**< DAC sample rate : 16k */ 307 AUD_DAC_SAMP_RATE_22_05K, /**< DAC sample rate : 22.05k */ 308 AUD_DAC_SAMP_RATE_24K, /**< DAC sample rate : 24k */ 309 AUD_DAC_SAMP_RATE_32K, /**< DAC sample rate : 32k */ 310 AUD_DAC_SAMP_RATE_44_1K, /**< DAC sample rate : 44.1k */ 311 AUD_DAC_SAMP_RATE_48K, /**< DAC sample rate : 48k */ 312 AUD_DAC_SAMP_RATE_MAX, 313 } aud_dac_samp_rate_t; 314 315 typedef enum { 316 AUD_DAC_SAMP_RATE_SOURCE_8K = 0, /**< DAC sample rate : 8k */ 317 AUD_DAC_SAMP_RATE_SOURCE_16K, /**< DAC sample rate : 16k */ 318 AUD_DAC_SAMP_RATE_SOURCE_44_1K, /**< DAC sample rate : 44.1k */ 319 AUD_DAC_SAMP_RATE_SOURCE_48K, /**< DAC sample rate : 48k */ 320 AUD_DAC_SAMP_RATE_SOURCE_MAX, 321 } aud_dac_samp_rate_source_t; 322 323 typedef enum 324 { 325 AUD_DAC_HPF_BYPASS_DISABLE = 0, /**< AUD DAC hpf bypass disable */ 326 AUD_DAC_HPF_BYPASS_ENABLE, /**< AUD DAC hpf bypass enable */ 327 AUD_DAC_HPF_BYPASS_OTHERS, 328 } aud_dac_hpf_bypass_t; 329 330 typedef enum { 331 AUD_DAC_CLK_INVERT_RISING = 0, /**< AUD dac output clock edge rising */ 332 AUD_DAC_CLK_INVERT_FALLING, /**< AUD dac output clock edge falling */ 333 AUD_DAC_CLK_INVERT_OTHERS, 334 } aud_dac_clk_invert_t; 335 336 typedef enum { 337 AUD_DACR_INT_DISABLE = 0, /**< AUD dac right channel interrupt disable */ 338 AUD_DACR_INT_ENABLE, /**< AUD dac right channel interrupt enable */ 339 AUD_DACL_INT_DISABLE, /**< AUD dac left channel interrupt disable */ 340 AUD_DACL_INT_ENABLE, /**< AUD dac left channel interrupt enable */ 341 AUD_DAC_INT_OTHERS, 342 } aud_dac_int_enable_t; 343 344 typedef enum { 345 AUD_DAC_FILT_DISABLE = 0, /**< AUD dac filter disable */ 346 AUD_DAC_FILT_ENABLE, /**< AUD dac filter enable */ 347 AUD_DAC_FILT_OTHERS, 348 } aud_dac_filt_enable_t; 349 350 typedef enum { 351 AUD_DAC_FRACMOD_MANUAL_DISABLE = 0, /**< disable dac fractional frequency division of manual set */ 352 AUD_DAC_FRACMOD_MANUAL_ENABLE, /**< enable ADC fractional frequency division of manual set */ 353 ADU_DAC_FRACMOD_MANUAL_OTHERS, 354 } aud_dac_fracmod_manual_t; 355 356 typedef enum { 357 /* fifo status */ 358 AUD_ADCL_NEAR_FULL_MASK = 1 << 2, /**< AUD ADC left channel FIFO near full */ 359 AUD_DTMF_NEAR_FULL_MASK = 1 << 3, /**< AUD DTMF FIFO near full */ 360 AUD_ADCL_NEAR_EMPTY_MASK = 1 << 6, /**< AUD ADC left channel FIFO near empty */ 361 AUD_DTMF_NEAR_EMPTY_MASK = 1 << 7, /**< AUD DTMF FIFO near empty */ 362 AUD_ADCL_FIFO_FULL_MASK = 1 << 10, /**< AUD ADC left channel FIFO full */ 363 AUD_DTMF_FIFO_FULL_MASK = 1 << 11, /**< AUD DTMF FIFO full */ 364 AUD_ADCL_FIFO_EMPTY_MASK = 1 << 14, /**< AUD ADC left channel FIFO empty */ 365 AUD_DTMF_FIFO_EMPTY_MASK = 1 << 15, /**< AUD DTMF FIFO empty */ 366 } aud_adc_status_mask_t; 367 368 typedef enum { 369 AUD_DACR_NEAR_FULL_MASK = 1, /**< AUD DAC right channel fifo near full */ 370 AUD_DACL_NEAR_FULL_MASK = 1 << 1, /**< AUD DAC left channel fifo near full */ 371 AUD_DACR_NEAR_EMPTY_MASK = 1 << 4, /**< AUD DAC right channel fifo near empty */ 372 AUD_DACL_NEAR_EMPTY_MASK = 1 << 5, /**< AUD DAC left channel fifo near empty */ 373 AUD_DACR_FIFO_FULL_MASK = 1 << 8, /**< AUD DAC right channel fifo full */ 374 AUD_DACL_FIFO_FULL_MASK = 1 << 9, /**< AUD DAC left channel fifo full */ 375 AUD_DACR_FIFO_EMPTY_MASK = 1 << 12, /**< AUD DAC right channel fifo empty */ 376 AUD_DACL_FIFO_EMPTY_MASK = 1 << 13, /**< AUD DAC left channel fifo empty */ 377 } aud_dac_status_mask_t; 378 379 /** 380 * @} 381 */ 382 383 /** 384 * @brief AUD struct defines 385 * @defgroup bk_api_aud_structs structs in AUD 386 * @ingroup bk_api_aud 387 * @{ 388 */ 389 390 typedef struct { 391 //aud_isr_id_t id; 392 icu_int_src_t int_src; 393 int_group_isr_t isr; 394 //dma_dev_t dma_dev; 395 } aud_int_config_t; 396 397 typedef struct { 398 /* audio_config */ 399 aud_adc_enable_t adc_enable; /**< AUD adc enable */ 400 aud_adc_line_enable_t line_enable; /**< AUD line in enable */ 401 aud_dtmf_enable_t dtmf_enable; /**< AUD dtmf enable */ 402 403 /* dtmf_config0 */ 404 aud_dtmf_tone_pattern_t tone_pattern; /**< AUD dtmf tone pattern */ 405 aud_dtmf_tone_mode_t tone_mode; /**< AUD dtmf tone mode */ 406 uint32_t tone_pause_time; /**< AUD dtmf tone pause time */ 407 uint32_t tone_active_time; /**< AUD dtmf tone active time */ 408 409 /* dtmf_config1 */ 410 uint32_t tone1_step; /**< AUD dtmf Tone1 frequency set Step = F(KHz) * 8191 */ 411 aud_dtmf_tone_attu_t tone1_attu; /**< AUD dtmf Tone1 damp set 0 ：-1 ：-15 dB */ 412 aud_dtmf_tone_enable_t tone1_enable; /**< AUD dtmf tone1 enable */ 413 414 /* dtmf_config2 */ 415 uint32_t tone2_step; /**< AUD dtmf Tone2 frequency set Step = F(KHz) * 8191 */ 416 aud_dtmf_tone_attu_t tone2_attu; /**< AUD dtmf Tone2 damp set 0 ：-1 ：-15 dB */ 417 aud_dtmf_tone_enable_t tone2_enable; /**< AUD dtmf tone2 enable */ 418 419 /* fifo_config */ 420 uint32_t dtmf_wr_threshold; /**< AUD dtmf write threshold value */ 421 aud_dtmf_int_t dtmf_int_enable; /**< AUD dtmf interrupt request enable */ 422 aud_loop_dtmf2dac_t loop_ton2dac; /**< AUD dtmf to DAC loop test enable */ 423 } aud_dtmf_config_t; 424 425 426 typedef struct { 427 /* audio mic config */ 428 aud_mic_enable_t mic_config; 429 430 /* audio_config */ 431 aud_adc_samp_rate_t samp_rate; /**< AUD adc sample rate */ 432 aud_adc_enable_t adc_enable; /**< AUD adc enable */ 433 aud_adc_line_enable_t line_enable; /**< AUD line in enable */ 434 aud_dtmf_enable_t dtmf_enable; /**< AUD dtmf enable */ 435 436 /* adc_config0 */ 437 uint32_t adc_hpf2_coef_B2; /**< AUD adc HPF2 coefficient B2 */ 438 aud_adc_hpf_bypass_t adc_hpf2_bypass_enable; /**< AUD adc hpf2 disable */ 439 aud_adc_hpf_bypass_t adc_hpf1_bypass_enable; /**< AUD adc hpf1 disable */ 440 uint32_t adc_set_gain; /**< AUD adc gain set */ 441 aud_adc_samp_edge_t adc_samp_edge; /**< ADC data sampling clock edge select rising/falling */ 442 443 /* adc_config1 */ 444 uint32_t adc_hpf2_coef_B0; /**< AUD adc HPF2 coefficient B0 */ 445 uint32_t adc_hpf2_coef_B1; /**< AUD adc HPF2 coefficient B1 */ 446 447 /* adc_config2 */ 448 uint32_t adc_hpf2_coef_A0; /**< AUD adc HPF2 coefficient A0 */ 449 uint32_t adc_hpf2_coef_A1; /**< AUD adc HPF2 coefficient A1 */ 450 451 /* fifo_config */ 452 uint32_t dtmf_wr_threshold; /**< AUD dtmf write threshold value */ 453 uint32_t adcl_wr_threshold; /**< AUD adcl write threshold value */ 454 aud_dtmf_int_t dtmf_int_enable; /**< AUD dtmf interrupt request enable */ 455 aud_adcl_int_t adcl_int_enable; /**< AUD adcl interrupt request enable */ 456 //aud_loop_dtmf2dac_t loop_ton2dac; /**< AUD dtmf to DAC loop test enable */ 457 aud_loop_adc2dac_t loop_adc2dac; /**< AUD adc to DAC loop test enable */ 458 459 /* agc_config0 */ 460 uint32_t agc_noise_thrd; /**< AUD AGC noise gating of excute，noise gating work when audio value is little */ 461 uint32_t agc_noise_high; /**< AUD AGC corresponding MIC_RSSI low 10 bit */ 462 uint32_t agc_noise_low; /**< AUD AGC corresponding MIC_RSSI low 10 bit */ 463 464 /* agc_config1 */ 465 uint32_t agc_noise_min; /**< AUD AGC {GAIN2[2:0] GAIN1[3:0]} when signal level below NOISE_LOW, when noise gating is enabled */ 466 aud_gac_noise_tout_t agc_noise_tout; /**< AUD AGC noise tout */ 467 aud_gac_high_dur_t agc_high_dur; /**< AUD AGC high noise gating work duration */ 468 aud_gac_low_dur_t agc_low_dur; /**< AUD AGC low noise gating work duration */ 469 uint32_t agc_min; /**< AUD AGC Minimum value of {GAIN2[2:0] GAIN1[3:0]} */ 470 uint32_t agc_max; /**< AUD AGC Maximum value of {GAIN2[2:0] GAIN1[3:0]} Also the default gain setting when AGC is disabled */ 471 aud_agc_method_t agc_ng_method; /**< AUD AGC noise gating method */ 472 aud_agc_ng_enable_t agc_ng_enable; /**< AUD AGC enable noise gating */ 473 474 /* agc_config2 */ 475 aud_agc_decay_time_t agc_decay_time; /**< AUD AGC agc decay time */ 476 aud_agc_attack_time_t agc_attack_time; /**< AUD AGC agc attack time */ 477 uint32_t agc_high_thrd; /**< AUD AGC coefficient high five bit of MIC_RSSI */ 478 uint32_t agc_low_thrd; /**< AUD AGC coefficient low five bit of MIC_RSSI */ 479 aud_agc_iir_coef_t agc_iir_coef; /**< AUD AGC iir coefficient select */ 480 aud_agc_enable_t agc_enable; /**< AUD AGC enable */ 481 uint32_t manual_pga_value; /**< AUD AGC manual set PGA value */ 482 aud_agc_manual_pga_en_t manual_pga_enable; /**< AUD AGC manual set PGA enable */ 483 484 /* extend_config */ 485 aud_adc_fracmod_manual_en_t adc_fracmod_manual; /**< AUD ADC fractional frequency division enable of manual set */ 486 uint32_t adc_fracmod; /**< AUD ADC fractional frequency division value N * 2^24 */ 487 } aud_adc_config_t; 488 489 typedef struct { 490 /* audio_config */ 491 aud_dac_enable_t dac_enable; /**< AUD dac enable */ 492 aud_dac_samp_rate_source_t samp_rate; /**< AUD dac sample rate */ 493 aud_dac_chl_enable_t dac_chl; /**< AUD dac channel */ 494 aud_dac_work_mode_t work_mode; /**< AUD dac work mode */ 495 496 /* dac_config0 */ 497 uint16_t dac_hpf2_coef_B2; /**< AUD dac HPF2 coefficient B2 */ 498 aud_dac_hpf_bypass_t dac_hpf2_bypass_enable; /**< AUD dac hpf2 disable */ 499 aud_dac_hpf_bypass_t dac_hpf1_bypass_enable; /**< AUD dac hpf1 disable */ 500 uint16_t dac_set_gain; /**< AUD dac gain set */ 501 aud_dac_clk_invert_t dac_clk_invert; /**< AUD dac output clock edge select */ 502 503 /* dac_config1 */ 504 uint16_t dac_hpf2_coef_B0; /**< AUD dac HPF2 coefficient B0 */ 505 uint16_t dac_hpf2_coef_B1; /**< AUD dac HPF2 coefficient B1 */ 506 507 /* dac_config2 */ 508 uint16_t dac_hpf2_coef_A1; /**< AUD dac HPF2 coefficient A1 */ 509 uint16_t dac_hpf2_coef_A2; /**< AUD dac HPF2 coefficient A2 */ 510 511 /* fifo_config */ 512 uint8_t dacr_rd_threshold; /**< AUD dacl read threshold value */ 513 uint8_t dacl_rd_threshold; /**< AUD dacr read threshold value */ 514 uint8_t dacr_int_enable; /**< AUD dacr interrupt request enable */ 515 uint8_t dacl_int_enable; /**< AUD dacl interrupt request enable */ 516 517 /* extend_config */ 518 aud_dac_filt_enable_t dac_filt_enable; /**< AUD dac filter enable */ 519 aud_dac_fracmod_manual_t dac_fracmod_manual_enable; /**< AUD dac fractional frequency division enable of manual set */ 520 uint32_t dac_fracmode_value; /**< AUD dac fractional frequency division value N * 2^24 */ 521 } aud_dac_config_t; 522 523 typedef struct { 524 int32_t flt0_A1; 525 int32_t flt0_A2; 526 int32_t flt0_B0; 527 int32_t flt0_B1; 528 int32_t flt0_B2; 529 530 int32_t flt1_A1; 531 int32_t flt1_A2; 532 int32_t flt1_B0; 533 int32_t flt1_B1; 534 int32_t flt1_B2; 535 536 int32_t flt2_A1; 537 int32_t flt2_A2; 538 int32_t flt2_B0; 539 int32_t flt2_B1; 540 int32_t flt2_B2; 541 542 int32_t flt3_A1; 543 int32_t flt3_A2; 544 int32_t flt3_B0; 545 int32_t flt3_B1; 546 int32_t flt3_B2; 547 } aud_eq_config_t; 548 549 550 /** 551 * @} 552 */ 553 554 555 #ifdef __cplusplus 556 } 557 #endif 558