1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 // 15 #pragma once 16 17 #include <driver/int_types.h> 18 #include <common/bk_include.h> 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 25 typedef void (*i2s_isr_t)(void *param); 26 27 28 /** 29 * @brief I2S defines 30 * @defgroup bk_api_i2s_defs macos 31 * @ingroup bk_api_i2s 32 * @{ 33 */ 34 35 #define BK_ERR_I2S_NOT_INIT (BK_ERR_I2S_BASE - 1) /**< I2S driver not init */ 36 #define BK_ERR_I2S_PARAM (BK_ERR_I2S_BASE - 2) /**< I2S parameter invalid */ 37 #define BK_ERR_I2S_ISR_ID (BK_ERR_I2S_BASE - 3) /**< I2S isr id invalid */ 38 39 /** 40 * @} 41 */ 42 43 /** 44 * @brief I2S enum defines 45 * @defgroup bk_api_i2s_enum I2S enums 46 * @ingroup bk_api_i2s 47 * @{ 48 */ 49 typedef enum { 50 I2S_GPIO_GROUP_0 = 0, /**< I2S gpio group 0: GPIO6, GPIO7, GPIO8, GPIO9 */ 51 I2S_GPIO_GROUP_1, /**< I2S gpio group 1: GPIO40, GPIO41, GPIO42, GPIO43 */ 52 I2S_GPIO_GROUP_MAX 53 } i2s_gpio_group_id_t; 54 55 56 typedef enum { 57 I2S_ISR_CHL1_TXUDF = 0, /**< I2S channel1 tx_udf interrupt */ 58 I2S_ISR_CHL1_RXOVF, /**< I2S channel1 rx_ovf interrupt */ 59 I2S_ISR_CHL1_TXINT, /**< I2S channel1 tx interrupt */ 60 I2S_ISR_CHL1_RXINT, /**< I2S channel1 rx interrupt */ 61 62 I2S_ISR_CHL2_TXUDF, /**< I2S channel2 tx_udf interrupt */ 63 I2S_ISR_CHL2_RXOVF, /**< I2S channel2 rx_ovf interrupt */ 64 I2S_ISR_CHL2_TXINT, /**< I2S channel2 tx interrupt */ 65 I2S_ISR_CHL2_RXINT, /**< I2S channel2 rx interrupt */ 66 67 I2S_ISR_CHL3_TXUDF, /**< I2S channel3 tx_udf interrupt */ 68 I2S_ISR_CHL3_RXOVF, /**< I2S channel3 rx_ovf interrupt */ 69 I2S_ISR_CHL3_TXINT, /**< I2S channel3 tx interrupt */ 70 I2S_ISR_CHL3_RXINT, /**< I2S channel3 rx interrupt */ 71 72 I2S_ISR_CHL4_TXUDF, /**< I2S channel4 tx_udf interrupt */ 73 I2S_ISR_CHL4_RXOVF, /**< I2S channel4 rx_ovf interrupt */ 74 I2S_ISR_CHL4_TXINT, /**< I2S channel4 tx interrupt */ 75 I2S_ISR_CHL4_RXINT, /**< I2S channel4 rx interrupt */ 76 77 I2S_ISR_MAX 78 } i2s_isr_id_t; 79 80 typedef enum { 81 I2S_DISABLE = 0, /**< I2S disable */ 82 I2S_ENABLE, /**< I2S enable */ 83 I2S_EN_MAX, 84 } i2s_en_t; 85 86 typedef enum { 87 I2S_ROLE_SLAVE = 0, /**< I2S role: slave */ 88 I2S_ROLE_MASTER, /**< I2S role: master */ 89 I2S_ROLE_MAX, 90 } i2s_role_t; 91 92 typedef enum { 93 I2S_WORK_MODE_I2S = 0, /**< I2S work mode: I2S (Philips) */ 94 I2S_WORK_MODE_LEFTJUST, /**< I2S work mode: Left Justified */ 95 I2S_WORK_MODE_RIGHTJUST, /**< I2S work mode: Right Justified */ 96 I2S_WORK_MODE_RSVD, /**< I2S work mode: reserved for future use */ 97 I2S_WORK_MODE_SHORTFAMSYNC, /**< I2S work mode: Short Frame Sync */ 98 I2S_WORK_MODE_LONGFAMSYNC, /**< I2S work mode: Long Frame Sync */ 99 I2S_WORK_MODE_NORMAL2BD, /**< I2S work mode: Normal 2B+D */ 100 I2S_WORK_MODE_DELAY2BD, /**< I2S work mode: Delay 2B+D */ 101 I2S_WORK_MODE_MAX, 102 } i2s_work_mode_t; 103 104 typedef enum { 105 I2S_LRCK_INVERT_DISABLE = 0, /**< I2S lrck invert disable */ 106 I2S_LRCK_INVERT_ENABLE, /**< I2S lrck invert enable */ 107 I2S_LRCK_INVERT_MAX, 108 } i2s_lrck_invert_en_t; 109 110 typedef enum { 111 I2S_SCK_INVERT_DISABLE = 0, /**< I2S sck invert disable */ 112 I2S_SCK_INVERT_ENABLE, /**< I2S sck invert enable */ 113 I2S_SCK_INVERT_MAX, 114 } i2s_sck_invert_en_t; 115 116 typedef enum { 117 I2S_LSB_FIRST_DISABLE = 0, /**< I2S lsb first disable */ 118 I2S_LSB_FIRST_ENABLE, /**< I2S lsb first enable */ 119 I2S_LSB_FIRST_EN_MAX, 120 } i2s_lsb_first_en_t; 121 122 typedef enum { 123 I2S_PARALLEL_DISABLE = 0, /**< I2S parallel disable */ 124 I2S_PARALLEL_ENABLE, /**< I2S parallel enable */ 125 I2S_PARALLEL_EN_MAX, 126 } i2s_parallel_en_t; 127 128 typedef enum { 129 I2S_LRCOM_STORE_LRLR = 0, /**< I2S lrcom store mode: L->R->L->R */ 130 I2S_LRCOM_STORE_16R16L, /**< I2S lrcom store mode: {16bitR,16bitL} */ 131 I2S_LRCOM_STORE_MODE_MAX, 132 } i2s_lrcom_store_mode_t; 133 134 typedef enum { 135 I2S_TXINT_LEVEL_1 = 0, /**< I2S tx_int level: 1 */ 136 I2S_TXINT_LEVEL_8, /**< I2S tx_int level: 8 */ 137 I2S_TXINT_LEVEL_16, /**< I2S tx_int level: 16 */ 138 I2S_TXINT_LEVEL_24, /**< I2S tx_int level: 24 */ 139 I2S_TXINT_LEVEL_MAX, 140 } i2s_txint_level_t; 141 142 typedef enum { 143 I2S_RXINT_LEVEL_1 = 0, /**< I2S rx_int level: 1 */ 144 I2S_RXINT_LEVEL_8, /**< I2S rx_int level: 8 */ 145 I2S_RXINT_LEVEL_16, /**< I2S rx_int level: 16 */ 146 I2S_RXINT_LEVEL_24, /**< I2S rx_int level: 24 */ 147 I2S_RXINT_LEVEL_MAX, 148 } i2s_rxint_level_t; 149 150 typedef enum { 151 I2S_INT_DISABLE = 0, /**< I2S interrupt disable */ 152 I2S_INT_ENABLE, /**< I2S interrupt enable */ 153 I2S_INT_EN_MAX, 154 } i2s_int_en_t; 155 156 typedef enum { 157 I2S_CHANNEL_1 = 0, /**< I2S channel: 1 */ 158 I2S_CHANNEL_2, /**< I2S channel: 2 */ 159 I2S_CHANNEL_3, /**< I2S channel: 3 */ 160 I2S_CHANNEL_4, /**< I2S channel: 4 */ 161 I2S_CHANNEL_MAX, 162 } i2s_channel_id_t; 163 164 typedef enum { 165 I2S_DATA_WIDTH_8 = 8, /**< I2S data width: 8 */ 166 I2S_DATA_WIDTH_16 = 16, /**< I2S data width: 16 */ 167 I2S_DATA_WIDTH_24 = 24, /**< I2S data width: 24 */ 168 I2S_DATA_WIDTH_32 = 32, /**< I2S data width: 32 */ 169 } i2s_data_width_t; 170 171 typedef enum { 172 I2S_SAMP_RATE_8000 = 0, /**< I2S sample rate: 8K */ 173 I2S_SAMP_RATE_12000, /**< I2S sample rate: 12K */ 174 I2S_SAMP_RATE_16000, /**< I2S sample rate: 16K */ 175 I2S_SAMP_RATE_24000, /**< I2S sample rate: 24K */ 176 I2S_SAMP_RATE_32000, /**< I2S sample rate: 32K */ 177 I2S_SAMP_RATE_48000, /**< I2S sample rate: 48K */ 178 I2S_SAMP_RATE_96000, /**< I2S sample rate: 96K */ 179 I2S_SAMP_RATE_8018, /**< I2S sample rate: 8.0182K */ 180 I2S_SAMP_RATE_11025, /**< I2S sample rate: 11.025K */ 181 I2S_SAMP_RATE_22050, /**< I2S sample rate: 22.050K */ 182 I2S_SAMP_RATE_44100, /**< I2S sample rate: 44.1K */ 183 I2S_SAMP_RATE_88200, /**< I2S sample rate: 88.2K */ 184 I2S_SAMP_RATE_MAX 185 } i2s_samp_rate_t; 186 187 188 /** 189 * @} 190 */ 191 192 /** 193 * @brief I2S struct defines 194 * @defgroup bk_api_i2s_structs structs in I2S 195 * @ingroup bk_api_i2s 196 * @{ 197 */ 198 typedef struct { 199 i2s_role_t role; 200 } i2s_driver_t; 201 202 203 typedef struct { 204 icu_int_src_t int_src; 205 int_group_isr_t isr; 206 } i2s_int_config_t; 207 208 typedef struct { 209 i2s_en_t i2s_en; 210 i2s_role_t role; 211 i2s_work_mode_t work_mode; 212 i2s_lrck_invert_en_t lrck_invert; 213 i2s_sck_invert_en_t sck_invert; 214 i2s_lsb_first_en_t lsb_first_en; 215 uint32_t sync_length; 216 uint32_t data_length; 217 uint32_t pcm_dlength; 218 uint32_t sample_ratio; 219 uint32_t sck_ratio; 220 i2s_parallel_en_t parallel_en; 221 i2s_lrcom_store_mode_t store_mode; 222 uint32_t sck_ratio_h4b; 223 uint32_t sample_ratio_h2b; 224 i2s_txint_level_t txint_level; 225 i2s_rxint_level_t rxint_level; 226 } i2s_config_t; 227 228 typedef struct { 229 i2s_channel_id_t channel_id; 230 i2s_int_en_t tx_udf_en; 231 i2s_int_en_t rx_ovf_en; 232 i2s_int_en_t tx_int_en; 233 i2s_int_en_t rx_int_en; 234 } i2s_int_en_config_t; 235 236 typedef struct { 237 i2s_channel_id_t channel_id; 238 bool tx_udf; 239 bool rx_ovf; 240 bool tx_int; 241 bool rx_int; 242 } i2s_int_status_t; 243 244 typedef struct { 245 i2s_data_width_t datawidth; 246 i2s_samp_rate_t samp_rate; 247 } i2s_rate_t; 248 249 typedef struct { 250 i2s_samp_rate_t samp_rate; 251 i2s_data_width_t datawidth; 252 uint32_t sys_clk; 253 uint32_t smp_ratio; 254 uint32_t bit_ratio; 255 } i2s_rate_table_node_t; 256 257 /** 258 * @} 259 */ 260 261 262 #ifdef __cplusplus 263 } 264 #endif 265