1 /*
2 Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip).
3 */
4
5 // Copyright 2013-2017 Espressif Systems (Shanghai) PTE LTD
6 //
7 // Licensed under the Apache License, Version 2.0 (the "License");
8 // you may not use this file except in compliance with the License.
9 // You may obtain a copy of the License at
10 //
11 // http://www.apache.org/licenses/LICENSE-2.0
12 //
13 // Unless required by applicable law or agreed to in writing, software
14 // distributed under the License is distributed on an "AS IS" BASIS,
15 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 // See the License for the specific language governing permissions and
17 // limitations under the License.
18
19
20 #include "sdkconfig.h"
21 #include "string.h"
22 #include "esp_attr.h"
23 #include "esp_err.h"
24 #include "esp_types.h"
25 #include "esp_log.h"
26 #include "esp_efuse.h"
27 #include "esp32/rom/spi_flash.h"
28 #include "esp32/rom/cache.h"
29 #include "esp32/rom/efuse.h"
30 #include "esp_rom_efuse.h"
31 #include "soc/dport_reg.h"
32 #include "soc/efuse_periph.h"
33 #include "soc/soc_caps.h"
34 #include "driver/gpio.h"
35 #include "hal/gpio_hal.h"
36 #include "driver/spi_common_internal.h"
37 #include "driver/periph_ctrl.h"
38 #include "bootloader_common.h"
39 #include "esp_rom_gpio.h"
40 #include "bootloader_flash_config.h"
41
42 #if CONFIG_SPIRAM
43 #include "soc/rtc.h"
44
45 //Commands for PSRAM chip
46 #define PSRAM_READ 0x03
47 #define PSRAM_FAST_READ 0x0B
48 #define PSRAM_FAST_READ_DUMMY 0x3
49 #define PSRAM_FAST_READ_QUAD 0xEB
50 #define PSRAM_FAST_READ_QUAD_DUMMY 0x5
51 #define PSRAM_WRITE 0x02
52 #define PSRAM_QUAD_WRITE 0x38
53 #define PSRAM_ENTER_QMODE 0x35
54 #define PSRAM_EXIT_QMODE 0xF5
55 #define PSRAM_RESET_EN 0x66
56 #define PSRAM_RESET 0x99
57 #define PSRAM_SET_BURST_LEN 0xC0
58 #define PSRAM_DEVICE_ID 0x9F
59
60 typedef enum {
61 PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */
62 PSRAM_CLK_MODE_DCLK = 1, /*!< Two extra clock cycles after CS is set high level */
63 } psram_clk_mode_t;
64
65 #define PSRAM_ID_KGD_M 0xff
66 #define PSRAM_ID_KGD_S 8
67 #define PSRAM_ID_KGD 0x5d
68 #define PSRAM_ID_EID_M 0xff
69 #define PSRAM_ID_EID_S 16
70
71 // Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
72 //
73 // BIT7 | BIT6 | BIT5 | SIZE(MBIT)
74 // -------------------------------------
75 // 0 | 0 | 0 | 16
76 // 0 | 0 | 1 | 32
77 // 0 | 1 | 0 | 64
78 #define PSRAM_EID_SIZE_M 0x07
79 #define PSRAM_EID_SIZE_S 5
80
81 typedef enum {
82 PSRAM_EID_SIZE_16MBITS = 0,
83 PSRAM_EID_SIZE_32MBITS = 1,
84 PSRAM_EID_SIZE_64MBITS = 2,
85 } psram_eid_size_t;
86
87 #define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
88 #define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
89 #define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
90 #define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
91
92 // For the old version 32Mbit psram, using the spicial driver */
93 #define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20)
94 #define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
95
96 // IO-pins for PSRAM.
97 // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
98 // hardcode the flash pins as well, making this code incompatible with either a setup
99 // that has the flash on non-standard pins or ESP32s with built-in flash.
100 #define PSRAM_SPIQ_SD0_IO 7
101 #define PSRAM_SPID_SD1_IO 8
102 #define PSRAM_SPIWP_SD3_IO 10
103 #define PSRAM_SPIHD_SD2_IO 9
104
105 #define FLASH_HSPI_CLK_IO 14
106 #define FLASH_HSPI_CS_IO 15
107 #define PSRAM_HSPI_SPIQ_SD0_IO 12
108 #define PSRAM_HSPI_SPID_SD1_IO 13
109 #define PSRAM_HSPI_SPIWP_SD3_IO 2
110 #define PSRAM_HSPI_SPIHD_SD2_IO 4
111
112 // PSRAM clock and cs IO should be configured based on hardware design.
113 // For ESP32-WROVER or ESP32-WROVER-B module, the clock IO is IO17, the cs IO is IO16,
114 // they are the default value for these two configs.
115 #define D0WD_PSRAM_CLK_IO CONFIG_D0WD_PSRAM_CLK_IO // Default value is 17
116 #define D0WD_PSRAM_CS_IO CONFIG_D0WD_PSRAM_CS_IO // Default value is 16
117
118 #define D2WD_PSRAM_CLK_IO CONFIG_D2WD_PSRAM_CLK_IO // Default value is 9
119 #define D2WD_PSRAM_CS_IO CONFIG_D2WD_PSRAM_CS_IO // Default value is 10
120
121 // For ESP32-PICO chip, the psram share clock with flash. The flash clock pin is fixed, which is IO6.
122 #define PICO_PSRAM_CLK_IO 6
123 #define PICO_PSRAM_CS_IO CONFIG_PICO_PSRAM_CS_IO // Default value is 10
124
125 #define PICO_V3_02_PSRAM_CLK_IO 10
126 #define PICO_V3_02_PSRAM_CS_IO 9
127
128 typedef struct {
129 uint8_t flash_clk_io;
130 uint8_t flash_cs_io;
131 uint8_t psram_clk_io;
132 uint8_t psram_cs_io;
133 uint8_t psram_spiq_sd0_io;
134 uint8_t psram_spid_sd1_io;
135 uint8_t psram_spiwp_sd3_io;
136 uint8_t psram_spihd_sd2_io;
137 } psram_io_t;
138
139 #define PSRAM_INTERNAL_IO_28 28
140 #define PSRAM_INTERNAL_IO_29 29
141 #define PSRAM_IO_MATRIX_DUMMY_40M ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M
142 #define PSRAM_IO_MATRIX_DUMMY_80M ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M
143
144 #define _SPI_CACHE_PORT 0
145 #define _SPI_FLASH_PORT 1
146 #define _SPI_80M_CLK_DIV 1
147 #define _SPI_40M_CLK_DIV 2
148
149 //For 4MB PSRAM, we need one more SPI host, select which one to use by kconfig
150 #ifdef CONFIG_SPIRAM_OCCUPY_HSPI_HOST
151 #define PSRAM_SPI_MODULE PERIPH_HSPI_MODULE
152 #define PSRAM_SPI_HOST HSPI_HOST
153 #define PSRAM_CLK_SIGNAL HSPICLK_OUT_IDX
154 #define PSRAM_SPI_NUM PSRAM_SPI_2
155 #define PSRAM_SPICLKEN DPORT_SPI2_CLK_EN
156 #elif defined CONFIG_SPIRAM_OCCUPY_VSPI_HOST
157 #define PSRAM_SPI_MODULE PERIPH_VSPI_MODULE
158 #define PSRAM_SPI_HOST VSPI_HOST
159 #define PSRAM_CLK_SIGNAL VSPICLK_OUT_IDX
160 #define PSRAM_SPI_NUM PSRAM_SPI_3
161 #define PSRAM_SPICLKEN DPORT_SPI3_CLK_EN
162 #else //set to SPI avoid HSPI and VSPI being used
163 #define PSRAM_SPI_MODULE PERIPH_SPI_MODULE
164 #define PSRAM_SPI_HOST SPI_HOST
165 #define PSRAM_CLK_SIGNAL SPICLK_OUT_IDX
166 #define PSRAM_SPI_NUM PSRAM_SPI_1
167 #define PSRAM_SPICLKEN DPORT_SPI01_CLK_EN
168 #endif
169
170 static const char* TAG = "psram";
171 typedef enum {
172 PSRAM_SPI_1 = 0x1,
173 PSRAM_SPI_2,
174 PSRAM_SPI_3,
175 PSRAM_SPI_MAX ,
176 } psram_spi_num_t;
177
178 static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
179 static psram_clk_mode_t s_clk_mode = PSRAM_CLK_MODE_DCLK;
180 static uint64_t s_psram_id = 0;
181 static bool s_2t_mode_enabled = false;
182
183 /* dummy_len_plus values defined in ROM for SPI flash configuration */
184 extern uint8_t g_rom_spiflash_dummy_len_plus[];
185 static int extra_dummy = 0;
186 typedef enum {
187 PSRAM_CMD_QPI,
188 PSRAM_CMD_SPI,
189 } psram_cmd_mode_t;
190
191 typedef struct {
192 uint16_t cmd; /*!< Command value */
193 uint16_t cmdBitLen; /*!< Command byte length*/
194 uint32_t *addr; /*!< Point to address value*/
195 uint16_t addrBitLen; /*!< Address byte length*/
196 uint32_t *txData; /*!< Point to send data buffer*/
197 uint16_t txDataBitLen; /*!< Send data byte length.*/
198 uint32_t *rxData; /*!< Point to recevie data buffer*/
199 uint16_t rxDataBitLen; /*!< Recevie Data byte length.*/
200 uint32_t dummyBitLen;
201 } psram_cmd_t;
202
203 static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
204
psram_clear_spi_fifo(psram_spi_num_t spi_num)205 static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
206 {
207 int i;
208 for (i = 0; i < 16; i++) {
209 WRITE_PERI_REG(SPI_W0_REG(spi_num)+i*4, 0);
210 }
211 }
212
213 //set basic SPI write mode
psram_set_basic_write_mode(psram_spi_num_t spi_num)214 static void psram_set_basic_write_mode(psram_spi_num_t spi_num)
215 {
216 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
217 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
218 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
219 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
220 }
221 //set QPI write mode
psram_set_qio_write_mode(psram_spi_num_t spi_num)222 static void psram_set_qio_write_mode(psram_spi_num_t spi_num)
223 {
224 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
225 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
226 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
227 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
228 }
229 //set QPI read mode
psram_set_qio_read_mode(psram_spi_num_t spi_num)230 static void psram_set_qio_read_mode(psram_spi_num_t spi_num)
231 {
232 SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
233 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
234 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
235 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
236 }
237 //set SPI read mode
psram_set_basic_read_mode(psram_spi_num_t spi_num)238 static void psram_set_basic_read_mode(psram_spi_num_t spi_num)
239 {
240 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
241 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
242 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
243 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
244 }
245
246
247 //start sending cmd/addr and optionally, receiving data
psram_cmd_recv_start(psram_spi_num_t spi_num,uint32_t * pRxData,uint16_t rxByteLen,psram_cmd_mode_t cmd_mode)248 static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t* pRxData, uint16_t rxByteLen,
249 psram_cmd_mode_t cmd_mode)
250 {
251 //get cs1
252 CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
253 SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
254
255 uint32_t mode_backup = (READ_PERI_REG(SPI_USER_REG(spi_num)) >> SPI_FWRITE_DUAL_S) & 0xf;
256 uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spi_num)) & (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M);
257 if (cmd_mode == PSRAM_CMD_SPI) {
258 psram_set_basic_write_mode(spi_num);
259 psram_set_basic_read_mode(spi_num);
260 } else if (cmd_mode == PSRAM_CMD_QPI) {
261 psram_set_qio_write_mode(spi_num);
262 psram_set_qio_read_mode(spi_num);
263 }
264
265 //Wait for SPI0 to idle
266 while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
267 DPORT_SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
268
269 // Start send data
270 SET_PERI_REG_MASK(SPI_CMD_REG(spi_num), SPI_USR);
271 while ((READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR));
272 DPORT_CLEAR_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
273
274 //recover spi mode
275 SET_PERI_REG_BITS(SPI_USER_REG(spi_num), (pRxData?SPI_FWRITE_DUAL_M:0xf), mode_backup, SPI_FWRITE_DUAL_S);
276 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M));
277 SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), rd_mode_backup);
278
279 //return cs to cs0
280 SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
281 CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
282
283 if (pRxData) {
284 int idx = 0;
285 // Read data out
286 do {
287 *pRxData++ = READ_PERI_REG(SPI_W0_REG(spi_num) + (idx << 2));
288 } while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0)));
289 }
290 }
291
292 static uint32_t backup_usr[3];
293 static uint32_t backup_usr1[3];
294 static uint32_t backup_usr2[3];
295
296 //setup spi command/addr/data/dummy in user mode
psram_cmd_config(psram_spi_num_t spi_num,psram_cmd_t * pInData)297 static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t* pInData)
298 {
299 while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
300 backup_usr[spi_num]=READ_PERI_REG(SPI_USER_REG(spi_num));
301 backup_usr1[spi_num]=READ_PERI_REG(SPI_USER1_REG(spi_num));
302 backup_usr2[spi_num]=READ_PERI_REG(SPI_USER2_REG(spi_num));
303 // Set command by user.
304 if (pInData->cmdBitLen != 0) {
305 // Max command length 16 bits.
306 SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, pInData->cmdBitLen - 1,
307 SPI_USR_COMMAND_BITLEN_S);
308 // Enable command
309 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
310 // Load command,bit15-0 is cmd value.
311 SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_VALUE, pInData->cmd, SPI_USR_COMMAND_VALUE_S);
312 } else {
313 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
314 SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S);
315 }
316 // Set Address by user.
317 if (pInData->addrBitLen != 0) {
318 SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, (pInData->addrBitLen - 1), SPI_USR_ADDR_BITLEN_S);
319 // Enable address
320 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
321 // Set address
322 WRITE_PERI_REG(SPI_ADDR_REG(spi_num), *pInData->addr);
323 } else {
324 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
325 SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, 0, SPI_USR_ADDR_BITLEN_S);
326 }
327 // Set data by user.
328 uint32_t* p_tx_val = pInData->txData;
329 if (pInData->txDataBitLen != 0) {
330 // Enable MOSI
331 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
332 // Load send buffer
333 int len = (pInData->txDataBitLen + 31) / 32;
334 if (p_tx_val != NULL) {
335 memcpy((void*)SPI_W0_REG(spi_num), p_tx_val, len * 4);
336 }
337 // Set data send buffer length.Max data length 64 bytes.
338 SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1),
339 SPI_USR_MOSI_DBITLEN_S);
340 } else {
341 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
342 SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, 0, SPI_USR_MOSI_DBITLEN_S);
343 }
344 // Set rx data by user.
345 if (pInData->rxDataBitLen != 0) {
346 // Enable MOSI
347 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
348 // Set data send buffer length.Max data length 64 bytes.
349 SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, (pInData->rxDataBitLen - 1),
350 SPI_USR_MISO_DBITLEN_S);
351 } else {
352 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
353 SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, 0, SPI_USR_MISO_DBITLEN_S);
354 }
355 if (pInData->dummyBitLen != 0) {
356 SET_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
357 SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, pInData->dummyBitLen - 1,
358 SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
359 } else {
360 CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
361 SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, 0, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
362 }
363 return 0;
364 }
365
psram_cmd_end(int spi_num)366 static void psram_cmd_end(int spi_num) {
367 while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
368 WRITE_PERI_REG(SPI_USER_REG(spi_num), backup_usr[spi_num]);
369 WRITE_PERI_REG(SPI_USER1_REG(spi_num), backup_usr1[spi_num]);
370 WRITE_PERI_REG(SPI_USER2_REG(spi_num), backup_usr2[spi_num]);
371 }
372
373 //exit QPI mode(set back to SPI mode)
psram_disable_qio_mode(psram_spi_num_t spi_num)374 static void psram_disable_qio_mode(psram_spi_num_t spi_num)
375 {
376 psram_cmd_t ps_cmd;
377 uint32_t cmd_exit_qpi;
378 cmd_exit_qpi = PSRAM_EXIT_QMODE;
379 ps_cmd.txDataBitLen = 8;
380 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
381 switch (s_psram_mode) {
382 case PSRAM_CACHE_F80M_S80M:
383 break;
384 case PSRAM_CACHE_F80M_S40M:
385 case PSRAM_CACHE_F40M_S40M:
386 default:
387 cmd_exit_qpi = PSRAM_EXIT_QMODE << 8;
388 ps_cmd.txDataBitLen = 16;
389 break;
390 }
391 }
392 ps_cmd.txData = &cmd_exit_qpi;
393 ps_cmd.cmd = 0;
394 ps_cmd.cmdBitLen = 0;
395 ps_cmd.addr = 0;
396 ps_cmd.addrBitLen = 0;
397 ps_cmd.rxData = NULL;
398 ps_cmd.rxDataBitLen = 0;
399 ps_cmd.dummyBitLen = 0;
400 psram_cmd_config(spi_num, &ps_cmd);
401 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI);
402 psram_cmd_end(spi_num);
403 }
404
405 //read psram id, should issue `psram_disable_qio_mode` before calling this
psram_read_id(psram_spi_num_t spi_num,uint64_t * dev_id)406 static void psram_read_id(psram_spi_num_t spi_num, uint64_t* dev_id)
407 {
408 uint32_t dummy_bits = 0 + extra_dummy;
409 uint32_t psram_id[2] = {0};
410 psram_cmd_t ps_cmd;
411
412 uint32_t addr = 0;
413 ps_cmd.addrBitLen = 3 * 8;
414 ps_cmd.cmd = PSRAM_DEVICE_ID;
415 ps_cmd.cmdBitLen = 8;
416 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
417 switch (s_psram_mode) {
418 case PSRAM_CACHE_F80M_S80M:
419 break;
420 case PSRAM_CACHE_F80M_S40M:
421 case PSRAM_CACHE_F40M_S40M:
422 default:
423 ps_cmd.cmdBitLen = 2; //this two bits is used to delay 2 clock cycle
424 ps_cmd.cmd = 0;
425 addr = (PSRAM_DEVICE_ID << 24) | 0;
426 ps_cmd.addrBitLen = 4 * 8;
427 break;
428 }
429 }
430 ps_cmd.addr = &addr;
431 ps_cmd.txDataBitLen = 0;
432 ps_cmd.txData = NULL;
433 ps_cmd.rxDataBitLen = 8 * 8;
434 ps_cmd.rxData = psram_id;
435 ps_cmd.dummyBitLen = dummy_bits;
436
437 psram_cmd_config(spi_num, &ps_cmd);
438 psram_clear_spi_fifo(spi_num);
439 psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI);
440 psram_cmd_end(spi_num);
441 *dev_id = (uint64_t)(((uint64_t)psram_id[1] << 32) | psram_id[0]);
442 }
443
444 //enter QPI mode
psram_enable_qio_mode(psram_spi_num_t spi_num)445 static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num)
446 {
447 psram_cmd_t ps_cmd;
448 uint32_t addr = (PSRAM_ENTER_QMODE << 24) | 0;
449
450 ps_cmd.cmdBitLen = 0;
451 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
452 switch (s_psram_mode) {
453 case PSRAM_CACHE_F80M_S80M:
454 break;
455 case PSRAM_CACHE_F80M_S40M:
456 case PSRAM_CACHE_F40M_S40M:
457 default:
458 ps_cmd.cmdBitLen = 2;
459 break;
460 }
461 }
462 ps_cmd.cmd = 0;
463 ps_cmd.addr = &addr;
464 ps_cmd.addrBitLen = 8;
465 ps_cmd.txData = NULL;
466 ps_cmd.txDataBitLen = 0;
467 ps_cmd.rxData = NULL;
468 ps_cmd.rxDataBitLen = 0;
469 ps_cmd.dummyBitLen = 0;
470 psram_cmd_config(spi_num, &ps_cmd);
471 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
472 psram_cmd_end(spi_num);
473 return ESP_OK;
474 }
475
476 #if CONFIG_SPIRAM_2T_MODE
477 // use SPI user mode to write psram
spi_user_psram_write(psram_spi_num_t spi_num,uint32_t address,uint32_t * data_buffer,uint32_t data_len)478 static void spi_user_psram_write(psram_spi_num_t spi_num, uint32_t address, uint32_t *data_buffer, uint32_t data_len)
479 {
480 uint32_t addr = (PSRAM_QUAD_WRITE << 24) | (address & 0x7fffff);
481 psram_cmd_t ps_cmd;
482 ps_cmd.cmdBitLen = 0;
483 ps_cmd.cmd = 0;
484 ps_cmd.addr = &addr;
485 ps_cmd.addrBitLen = 4 * 8;
486 ps_cmd.txDataBitLen = 32 * 8;
487 ps_cmd.txData = NULL;
488 ps_cmd.rxDataBitLen = 0;
489 ps_cmd.rxData = NULL;
490 ps_cmd.dummyBitLen = 0;
491
492 for(uint32_t i=0; i<data_len; i+=32) {
493 psram_clear_spi_fifo(spi_num);
494 addr = (PSRAM_QUAD_WRITE << 24) | ((address & 0x7fffff) + i);
495 ps_cmd.txData = data_buffer + (i / 4);
496 psram_cmd_config(spi_num, &ps_cmd);
497 psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_QPI);
498 }
499 psram_cmd_end(spi_num);
500 }
501
502 // use SPI user mode to read psram
spi_user_psram_read(psram_spi_num_t spi_num,uint32_t address,uint32_t * data_buffer,uint32_t data_len)503 static void spi_user_psram_read(psram_spi_num_t spi_num, uint32_t address, uint32_t *data_buffer, uint32_t data_len)
504 {
505 uint32_t addr = (PSRAM_FAST_READ_QUAD << 24) | (address & 0x7fffff);
506 uint32_t dummy_bits = PSRAM_FAST_READ_QUAD_DUMMY + 1;
507 psram_cmd_t ps_cmd;
508 ps_cmd.cmdBitLen = 0;
509 ps_cmd.cmd = 0;
510 ps_cmd.addr = &addr;
511 ps_cmd.addrBitLen = 4 * 8;
512 ps_cmd.txDataBitLen = 0;
513 ps_cmd.txData = NULL;
514 ps_cmd.rxDataBitLen = 32 * 8;
515 ps_cmd.dummyBitLen = dummy_bits + extra_dummy;
516
517 for(uint32_t i=0; i<data_len; i+=32) {
518 psram_clear_spi_fifo(spi_num);
519 addr = (PSRAM_FAST_READ_QUAD << 24) | ((address & 0x7fffff) + i);
520 ps_cmd.rxData = data_buffer + (i / 4);
521 psram_cmd_config(spi_num, &ps_cmd);
522 psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_QPI);
523 }
524 psram_cmd_end(spi_num);
525 }
526
527 //enable psram 2T mode
psram_2t_mode_enable(psram_spi_num_t spi_num)528 static esp_err_t IRAM_ATTR psram_2t_mode_enable(psram_spi_num_t spi_num)
529 {
530 psram_disable_qio_mode(spi_num);
531 // configure psram clock as 5 MHz
532 uint32_t div = rtc_clk_apb_freq_get() / 5000000;
533 esp_rom_spiflash_config_clk(div, spi_num);
534
535 psram_cmd_t ps_cmd;
536
537 // setp1: send cmd 0x5e
538 // send one more bit clock after send cmd
539 ps_cmd.cmd = 0x5e;
540 ps_cmd.cmdBitLen = 8;
541 ps_cmd.addrBitLen = 0;
542 ps_cmd.addr = 0;
543 ps_cmd.txDataBitLen = 0;
544 ps_cmd.txData = NULL;
545 ps_cmd.rxDataBitLen =0;
546 ps_cmd.rxData = NULL;
547 ps_cmd.dummyBitLen = 1;
548 psram_cmd_config(spi_num, &ps_cmd);
549 psram_clear_spi_fifo(spi_num);
550 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
551 psram_cmd_end(spi_num);
552
553 // setp2: send cmd 0x5f
554 // send one more bit clock after send cmd
555 ps_cmd.cmd = 0x5f;
556 psram_cmd_config(spi_num, &ps_cmd);
557 psram_clear_spi_fifo(spi_num);
558 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
559 psram_cmd_end(spi_num);
560
561 // setp3: keep cs as high level
562 // send 128 cycles clock
563 // send 1 bit high levle in ninth clock from the back to PSRAM SIO1
564 GPIO_OUTPUT_SET(D0WD_PSRAM_CS_IO, 1);
565 esp_rom_gpio_connect_out_signal(D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0);
566
567 esp_rom_gpio_connect_out_signal(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0);
568 esp_rom_gpio_connect_in_signal(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0);
569 esp_rom_gpio_connect_out_signal(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0);
570 esp_rom_gpio_connect_in_signal(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0);
571
572 uint32_t w_data_2t[4] = {0x0, 0x0, 0x0, 0x00010000};
573
574 ps_cmd.cmd = 0;
575 ps_cmd.cmdBitLen = 0;
576 ps_cmd.txDataBitLen = 128;
577 ps_cmd.txData = w_data_2t;
578 ps_cmd.dummyBitLen = 0;
579 psram_clear_spi_fifo(spi_num);
580 psram_cmd_config(spi_num, &ps_cmd);
581 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
582 psram_cmd_end(spi_num);
583
584 esp_rom_gpio_connect_out_signal(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0);
585 esp_rom_gpio_connect_in_signal(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0);
586 esp_rom_gpio_connect_out_signal(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0);
587 esp_rom_gpio_connect_in_signal(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0);
588
589 esp_rom_gpio_connect_out_signal(D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
590
591 // setp4: send cmd 0x5f
592 // send one more bit clock after send cmd
593 ps_cmd.cmd = 0x5f;
594 ps_cmd.cmdBitLen = 8;
595 ps_cmd.txDataBitLen = 0;
596 ps_cmd.txData = NULL;
597 ps_cmd.dummyBitLen = 1;
598 psram_cmd_config(spi_num, &ps_cmd);
599 psram_clear_spi_fifo(spi_num);
600 psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
601 psram_cmd_end(spi_num);
602
603 // configure psram clock back to the default value
604 switch (s_psram_mode) {
605 case PSRAM_CACHE_F80M_S40M:
606 case PSRAM_CACHE_F40M_S40M:
607 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, spi_num);
608 break;
609 case PSRAM_CACHE_F80M_S80M:
610 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, spi_num);
611 break;
612 default:
613 break;
614 }
615 psram_enable_qio_mode(spi_num);
616 return ESP_OK;
617 }
618
619 #define CHECK_DATA_LEN (1024)
620 #define CHECK_ADDR_STEP (0x100000)
621 #define SIZE_32MBIT (0x400000)
622 #define SIZE_64MBIT (0x800000)
623
psram_2t_mode_check(psram_spi_num_t spi_num)624 static esp_err_t psram_2t_mode_check(psram_spi_num_t spi_num)
625 {
626 uint8_t w_check_data[CHECK_DATA_LEN] = {0};
627 uint8_t r_check_data[CHECK_DATA_LEN] = {0};
628
629 for (uint32_t addr=0; addr<SIZE_32MBIT; addr+=CHECK_ADDR_STEP) {
630 spi_user_psram_write(spi_num, addr, (uint32_t *)w_check_data, CHECK_DATA_LEN);
631 }
632
633 memset(w_check_data, 0xff, sizeof(w_check_data));
634
635 for (uint32_t addr=SIZE_32MBIT; addr<SIZE_64MBIT; addr+=CHECK_ADDR_STEP) {
636 spi_user_psram_write(spi_num, addr, (uint32_t *)w_check_data, CHECK_DATA_LEN);
637 }
638
639 for (uint32_t addr=0; addr<SIZE_32MBIT; addr+=CHECK_ADDR_STEP) {
640 spi_user_psram_read(spi_num, addr, (uint32_t *)r_check_data, CHECK_DATA_LEN);
641 for (uint32_t j=0; j<CHECK_DATA_LEN; j++) {
642 if (r_check_data[j] != 0xff) {
643 return ESP_FAIL;
644 }
645 }
646 }
647
648 return ESP_OK;
649 }
650 #endif
651
psram_set_cs_timing(psram_spi_num_t spi_num,psram_clk_mode_t clk_mode)652 void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode)
653 {
654 if (clk_mode == PSRAM_CLK_MODE_NORM) {
655 SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
656 // Set cs time.
657 SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
658 SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
659 } else {
660 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
661 }
662 }
663
664 //spi param init for psram
psram_spi_init(psram_spi_num_t spi_num,psram_cache_mode_t mode)665 void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
666 {
667 CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_TRANS_DONE << 5);
668 // SPI_CPOL & SPI_CPHA
669 CLEAR_PERI_REG_MASK(SPI_PIN_REG(spi_num), SPI_CK_IDLE_EDGE);
670 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CK_OUT_EDGE);
671 // SPI bit order
672 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_WR_BIT_ORDER);
673 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_RD_BIT_ORDER);
674 // SPI bit order
675 CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_DOUTDIN);
676 // May be not must to do.
677 WRITE_PERI_REG(SPI_USER1_REG(spi_num), 0);
678 // SPI mode type
679 CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_SLAVE_MODE);
680 memset((void*)SPI_W0_REG(spi_num), 0, 16 * 4);
681 psram_set_cs_timing(spi_num, s_clk_mode);
682 }
683
684 //psram gpio init , different working frequency we have different solutions
psram_gpio_config(psram_io_t * psram_io,psram_cache_mode_t mode)685 static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_mode_t mode)
686 {
687 int spi_cache_dummy = 0;
688 uint32_t rd_mode_reg = READ_PERI_REG(SPI_CTRL_REG(0));
689 if (rd_mode_reg & SPI_FREAD_QIO_M) {
690 spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
691 } else if (rd_mode_reg & SPI_FREAD_DIO_M) {
692 spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
693 SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
694 } else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) {
695 spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
696 } else {
697 spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
698 }
699
700 switch (mode) {
701 case PSRAM_CACHE_F80M_S40M:
702 extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
703 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
704 g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
705 SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
706 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT);
707 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT);
708 //set drive ability for clock
709 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 3, FUN_DRV_S);
710 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 2, FUN_DRV_S);
711 break;
712 case PSRAM_CACHE_F80M_S80M:
713 extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
714 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
715 g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
716 SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
717 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT);
718 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_FLASH_PORT);
719 //set drive ability for clock
720 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 3, FUN_DRV_S);
721 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 3, FUN_DRV_S);
722 break;
723 case PSRAM_CACHE_F40M_S40M:
724 extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
725 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
726 g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
727 SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
728 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_CACHE_PORT);
729 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT);
730 //set drive ability for clock
731 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 2, FUN_DRV_S);
732 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 2, FUN_DRV_S);
733 break;
734 default:
735 break;
736 }
737 SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_USR_DUMMY); // dummy enable
738
739 // In bootloader, all the signals are already configured,
740 // We keep the following code in case the bootloader is some older version.
741 esp_rom_gpio_connect_out_signal(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0);
742 esp_rom_gpio_connect_out_signal(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0);
743 esp_rom_gpio_connect_out_signal(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0);
744 esp_rom_gpio_connect_in_signal(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0);
745 esp_rom_gpio_connect_out_signal(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0);
746 esp_rom_gpio_connect_in_signal(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0);
747 esp_rom_gpio_connect_out_signal(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0);
748 esp_rom_gpio_connect_in_signal(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0);
749 esp_rom_gpio_connect_out_signal(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0);
750 esp_rom_gpio_connect_in_signal(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
751
752 //select pin function gpio
753 if ((psram_io->flash_clk_io == SPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
754 //flash clock signal should come from IO MUX.
755 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK);
756 } else {
757 //flash clock signal should come from GPIO matrix.
758 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], PIN_FUNC_GPIO);
759 }
760 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], PIN_FUNC_GPIO);
761 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], PIN_FUNC_GPIO);
762 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], PIN_FUNC_GPIO);
763 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], PIN_FUNC_GPIO);
764 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], PIN_FUNC_GPIO);
765 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], PIN_FUNC_GPIO);
766 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], PIN_FUNC_GPIO);
767
768 uint32_t flash_id = g_rom_flashchip.device_id;
769 if (flash_id == FLASH_ID_GD25LQ32C) {
770 // Set drive ability for 1.8v flash in 80Mhz.
771 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], FUN_DRV_V, 3, FUN_DRV_S);
772 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV_V, 3, FUN_DRV_S);
773 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], FUN_DRV_V, 3, FUN_DRV_S);
774 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV_V, 3, FUN_DRV_S);
775 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], FUN_DRV_V, 3, FUN_DRV_S);
776 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], FUN_DRV_V, 3, FUN_DRV_S);
777 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], FUN_DRV_V, 3, FUN_DRV_S);
778 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], FUN_DRV_V, 3, FUN_DRV_S);
779 }
780 }
781
psram_get_size(void)782 psram_size_t psram_get_size(void)
783 {
784 if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
785 return s_2t_mode_enabled ? PSRAM_SIZE_32MBITS : PSRAM_SIZE_64MBITS;
786 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) {
787 return PSRAM_SIZE_32MBITS;
788 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) {
789 return PSRAM_SIZE_16MBITS;
790 } else {
791 return PSRAM_SIZE_MAX;
792 }
793 }
794
795 //used in UT only
psram_is_32mbit_ver0(void)796 bool psram_is_32mbit_ver0(void)
797 {
798 return PSRAM_IS_32MBIT_VER0(s_psram_id);
799 }
800
801 /*
802 * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
803 * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
804 */
psram_enable(psram_cache_mode_t mode,psram_vaddr_mode_t vaddrmode)805 esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
806 {
807 psram_io_t psram_io={0};
808 uint32_t pkg_ver = esp_efuse_get_pkg_ver();
809 if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
810 ESP_EARLY_LOGI(TAG, "This chip is ESP32-D2WD");
811 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
812 if (cfg.tieh != RTC_VDDSDIO_TIEH_1_8V) {
813 ESP_EARLY_LOGE(TAG, "VDDSDIO is not 1.8V");
814 return ESP_FAIL;
815 }
816 psram_io.psram_clk_io = D2WD_PSRAM_CLK_IO;
817 psram_io.psram_cs_io = D2WD_PSRAM_CS_IO;
818 } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
819 ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO");
820 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
821 if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
822 ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
823 return ESP_FAIL;
824 }
825 s_clk_mode = PSRAM_CLK_MODE_NORM;
826 psram_io.psram_clk_io = PICO_PSRAM_CLK_IO;
827 psram_io.psram_cs_io = PICO_PSRAM_CS_IO;
828 } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
829 ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO-V3-02");
830 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
831 if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
832 ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
833 return ESP_FAIL;
834 }
835 s_clk_mode = PSRAM_CLK_MODE_NORM;
836 psram_io.psram_clk_io = PICO_V3_02_PSRAM_CLK_IO;
837 psram_io.psram_cs_io = PICO_V3_02_PSRAM_CS_IO;
838 } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)){
839 ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WD");
840 psram_io.psram_clk_io = D0WD_PSRAM_CLK_IO;
841 psram_io.psram_cs_io = D0WD_PSRAM_CS_IO;
842 } else {
843 ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
844 abort();
845 }
846
847 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
848 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
849 psram_io.flash_clk_io = SPI_IOMUX_PIN_NUM_CLK;
850 psram_io.flash_cs_io = SPI_IOMUX_PIN_NUM_CS;
851 psram_io.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO;
852 psram_io.psram_spid_sd1_io = PSRAM_SPID_SD1_IO;
853 psram_io.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO;
854 psram_io.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO;
855 } else if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
856 psram_io.flash_clk_io = FLASH_HSPI_CLK_IO;
857 psram_io.flash_cs_io = FLASH_HSPI_CS_IO;
858 psram_io.psram_spiq_sd0_io = PSRAM_HSPI_SPIQ_SD0_IO;
859 psram_io.psram_spid_sd1_io = PSRAM_HSPI_SPID_SD1_IO;
860 psram_io.psram_spiwp_sd3_io = PSRAM_HSPI_SPIWP_SD3_IO;
861 psram_io.psram_spihd_sd2_io = PSRAM_HSPI_SPIHD_SD2_IO;
862 } else {
863 psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig);
864 psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig);
865 psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
866 psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig);
867 psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
868 psram_io.psram_spiwp_sd3_io = bootloader_flash_get_wp_pin();
869 }
870
871 assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
872 s_psram_mode = mode;
873
874 WRITE_PERI_REG(SPI_EXT3_REG(0), 0x1);
875 CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_PREP_HOLD_M);
876
877 psram_spi_init(PSRAM_SPI_1, mode);
878
879 switch (mode) {
880 case PSRAM_CACHE_F80M_S80M:
881 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
882 break;
883 case PSRAM_CACHE_F80M_S40M:
884 case PSRAM_CACHE_F40M_S40M:
885 default:
886 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
887 /* We need to delay CLK to the PSRAM with respect to the clock signal as output by the SPI peripheral.
888 We do this by routing it signal to signal 224/225, which are used as a loopback; the extra run through
889 the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in
890 silicon) as a temporary pad for this. So the signal path is:
891 SPI CLK --> GPIO28 --> signal224(in then out) --> internal GPIO29 --> signal225(in then out) --> GPIO17(PSRAM CLK)
892 */
893 esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0);
894 esp_rom_gpio_connect_in_signal(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0);
895 esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0);
896 esp_rom_gpio_connect_in_signal(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0);
897 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SIG_IN_FUNC225_IDX, 0, 0);
898 } else {
899 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
900 }
901 break;
902 }
903
904 // Rise VDDSIO for 1.8V psram.
905 bootloader_common_vddsdio_configure();
906 // GPIO related settings
907 psram_gpio_config(&psram_io, mode);
908
909 psram_spi_num_t spi_num = PSRAM_SPI_1;
910 psram_disable_qio_mode(spi_num);
911 psram_read_id(spi_num, &s_psram_id);
912 if (!PSRAM_IS_VALID(s_psram_id)) {
913 /* 16Mbit psram ID read error workaround:
914 * treat the first read id as a dummy one as the pre-condition,
915 * Send Read ID command again
916 */
917 psram_read_id(spi_num, &s_psram_id);
918 if (!PSRAM_IS_VALID(s_psram_id)) {
919 ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", (uint32_t)s_psram_id);
920 return ESP_FAIL;
921 }
922 }
923
924 if (psram_is_32mbit_ver0()) {
925 s_clk_mode = PSRAM_CLK_MODE_DCLK;
926 if (mode == PSRAM_CACHE_F80M_S80M) {
927 #ifdef CONFIG_SPIRAM_OCCUPY_NO_HOST
928 ESP_EARLY_LOGE(TAG, "This version of PSRAM needs to claim an extra SPI peripheral at 80MHz. Please either: choose lower frequency by SPIRAM_SPEED_, or select one SPI peripheral it by SPIRAM_OCCUPY_*SPI_HOST in the menuconfig.");
929 abort();
930 #else
931 /* note: If the third mode(80Mhz+80Mhz) is enabled for 32MBit 1V8 psram, one of HSPI/VSPI port will be
932 occupied by the system (according to kconfig).
933 Application code should never touch HSPI/VSPI hardware in this case. We try to stop applications
934 from doing this using the drivers by claiming the port for ourselves */
935 periph_module_enable(PSRAM_SPI_MODULE);
936 bool r=spicommon_periph_claim(PSRAM_SPI_HOST, "psram");
937 if (!r) {
938 return ESP_ERR_INVALID_STATE;
939 }
940 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, PSRAM_CLK_SIGNAL, 0, 0);
941 //use spi3 clock,but use spi1 data/cs wires
942 //We get a solid 80MHz clock from SPI3 by setting it up, starting a transaction, waiting until it
943 //is in progress, then cutting the clock (but not the reset!) to that peripheral.
944 WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_NUM), 32 << 24);
945 SET_PERI_REG_MASK(SPI_CMD_REG(PSRAM_SPI_NUM), SPI_FLASH_READ_M);
946 uint32_t spi_status;
947 while (1) {
948 spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_NUM));
949 if (spi_status != 0 && spi_status != 1) {
950 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, PSRAM_SPICLKEN);
951 break;
952 }
953 }
954 #endif
955 }
956 } else {
957 // For other psram, we don't need any extra clock cycles after cs get back to high level
958 s_clk_mode = PSRAM_CLK_MODE_NORM;
959 esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0);
960 esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0);
961 esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
962 }
963
964 // Update cs timing according to psram driving method.
965 psram_set_cs_timing(PSRAM_SPI_1, s_clk_mode);
966 psram_set_cs_timing(_SPI_CACHE_PORT, s_clk_mode);
967 psram_enable_qio_mode(PSRAM_SPI_1);
968
969 if(((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id))) {
970 #if CONFIG_SPIRAM_2T_MODE
971 #if CONFIG_SPIRAM_BANKSWITCH_ENABLE
972 ESP_EARLY_LOGE(TAG, "PSRAM 2T mode and SPIRAM bank switching can not enabled meanwhile. Please read the help text for SPIRAM_2T_MODE in the project configuration menu.");
973 abort();
974 #endif
975 /* Note: 2T mode command should not be sent twice,
976 otherwise psram would get back to normal mode. */
977 if (psram_2t_mode_check(PSRAM_SPI_1) != ESP_OK) {
978 psram_2t_mode_enable(PSRAM_SPI_1);
979 if (psram_2t_mode_check(PSRAM_SPI_1) != ESP_OK) {
980 ESP_EARLY_LOGE(TAG, "PSRAM 2T mode enable fail!");
981 return ESP_FAIL;
982 }
983 }
984 s_2t_mode_enabled = true;
985 ESP_EARLY_LOGI(TAG, "PSRAM is in 2T mode");
986 #endif
987 }
988
989 psram_cache_init(mode, vaddrmode);
990 return ESP_OK;
991 }
992
993 //register initialization for sram cache params and r/w commands
psram_cache_init(psram_cache_mode_t psram_cache_mode,psram_vaddr_mode_t vaddrmode)994 static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
995 {
996 switch (psram_cache_mode) {
997 case PSRAM_CACHE_F80M_S80M:
998 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk,80+40;
999 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4
1000 break;
1001 case PSRAM_CACHE_F80M_S40M:
1002 CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M);
1003 SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKDIV_PRE_V, 0, SPI_CLKDIV_PRE_S);
1004 SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_N, 1, SPI_CLKCNT_N_S);
1005 SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_H, 0, SPI_CLKCNT_H_S);
1006 SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_L, 1, SPI_CLKCNT_L_S);
1007 SET_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
1008 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
1009 break;
1010 case PSRAM_CACHE_F40M_S40M:
1011 default:
1012 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
1013 CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div
1014 break;
1015 }
1016
1017 CLEAR_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M); //disable dio mode for cache command
1018 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_QIO_M); //enable qio mode for cache command
1019 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable cache read command
1020 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_WCMD_M); //enable cache write command
1021 SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23, SPI_SRAM_ADDR_BITLEN_S); //write address for cache command.
1022 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
1023
1024 //config sram cache r/w command
1025 SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
1026 SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
1027 SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD,
1028 SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
1029 SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
1030 SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
1031 SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
1032 SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
1033 SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
1034 SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy; 80m--+2dummy
1035
1036 switch (psram_cache_mode) {
1037 case PSRAM_CACHE_F80M_S80M: //in this mode , no delay is needed
1038 break;
1039 case PSRAM_CACHE_F80M_S40M: //if sram is @40M, need 2 cycles of delay
1040 case PSRAM_CACHE_F40M_S40M:
1041 default:
1042 if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
1043 SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
1044 SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
1045 SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, ((PSRAM_FAST_READ_QUAD) << 8),
1046 SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB, read command value,(0x00 for delay,0xeb for cmd)
1047 SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
1048 SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
1049 SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, ((PSRAM_QUAD_WRITE) << 8),
1050 SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
1051 SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
1052 SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy; 80m--+2dummy
1053 }
1054 break;
1055 }
1056
1057 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
1058 DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
1059 if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
1060 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
1061 DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
1062 } else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
1063 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT);
1064 DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT);
1065 }
1066
1067 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
1068 //cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
1069 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMMU_SRAM_PAGE_MODE_S);
1070 DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1|DPORT_APP_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
1071 //cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
1072 DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S);
1073
1074 CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
1075 }
1076
1077 #endif // CONFIG_SPIRAM
1078