1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "sys/param.h"
16 #include "esp_timer_impl.h"
17 #include "esp_timer.h"
18 #include "esp_err.h"
19 #include "esp_system.h"
20 #include "esp_task.h"
21 #include "esp_attr.h"
22 #include "esp_intr_alloc.h"
23 #include "esp_log.h"
24 #include "esp32/clk.h"
25 #include "driver/periph_ctrl.h"
26 #include "soc/soc.h"
27 #include "soc/timer_group_reg.h"
28 #include "soc/rtc.h"
29 #include "esp_osal/esp_osal.h"
30
31 /**
32 * @file esp_timer_lac.c
33 * @brief Implementation of chip-specific part of esp_timer
34 *
35 * This implementation uses TG0 LAC timer of the ESP32. This timer is
36 * a 64-bit up-counting timer, with a programmable compare value (called 'alarm'
37 * hereafter). When the timer reaches compare value, interrupt is raised.
38 * The timer can be configured to produce an edge or a level interrupt.
39 */
40
41 /* Selects which Timer Group peripheral to use */
42 #define LACT_MODULE 0
43
44 #if LACT_MODULE == 0
45 #define INTR_SOURCE_LACT ETS_TG0_LACT_LEVEL_INTR_SOURCE
46 #define PERIPH_LACT PERIPH_TIMG0_MODULE
47 #elif LACT_MODULE == 1
48 #define INTR_SOURCE_LACT ETS_TG1_LACT_LEVEL_INTR_SOURCE
49 #define PERIPH_LACT PERIPH_TIMG1_MODULE
50 #else
51 #error "Incorrect the number of LACT module (only 0 or 1)"
52 #endif
53
54 /* Desired number of timer ticks per microsecond.
55 * This value should be small enough so that all possible APB frequencies
56 * could be divided by it without remainder.
57 * On the other hand, the smaller this value is, the longer we need to wait
58 * after setting UPDATE_REG before the timer value can be read.
59 * If TICKS_PER_US == 1, then we need to wait up to 1 microsecond, which
60 * makes esp_timer_impl_get_time function take too much time.
61 * The value TICKS_PER_US == 2 allows for most of the APB frequencies, and
62 * allows reading the counter quickly enough.
63 */
64 #define TICKS_PER_US 2
65
66 /* Shorter register names, used in this file */
67 #define CONFIG_REG (TIMG_LACTCONFIG_REG(LACT_MODULE))
68 #define RTC_STEP_REG (TIMG_LACTRTC_REG(LACT_MODULE))
69 #define ALARM_LO_REG (TIMG_LACTALARMLO_REG(LACT_MODULE))
70 #define ALARM_HI_REG (TIMG_LACTALARMHI_REG(LACT_MODULE))
71 #define COUNT_LO_REG (TIMG_LACTLO_REG(LACT_MODULE))
72 #define COUNT_HI_REG (TIMG_LACTHI_REG(LACT_MODULE))
73 #define UPDATE_REG (TIMG_LACTUPDATE_REG(LACT_MODULE))
74 #define LOAD_REG (TIMG_LACTLOAD_REG(LACT_MODULE))
75 #define LOAD_LO_REG (TIMG_LACTLOADLO_REG(LACT_MODULE))
76 #define LOAD_HI_REG (TIMG_LACTLOADHI_REG(LACT_MODULE))
77 #define INT_ENA_REG (TIMG_INT_ENA_TIMERS_REG(LACT_MODULE))
78 #define INT_ST_REG (TIMG_INT_ST_TIMERS_REG(LACT_MODULE))
79 #define INT_CLR_REG (TIMG_INT_CLR_TIMERS_REG(LACT_MODULE))
80
81 /* Helper type to convert between a 64-bit value and a pair of 32-bit values without shifts and masks */
82 typedef struct {
83 union {
84 struct {
85 uint32_t lo;
86 uint32_t hi;
87 };
88 uint64_t val;
89 };
90 } timer_64b_reg_t;
91
92 static const char* TAG = "esp_timer_impl";
93
94 /* Interrupt handle returned by the interrupt allocator */
95 static intr_handle_t s_timer_interrupt_handle;
96
97 /* Function from the upper layer to be called when the interrupt happens.
98 * Registered in esp_timer_impl_init.
99 */
100 static intr_handler_t s_alarm_handler = NULL;
101
102 /* Spinlock used to protect access to the hardware registers. */
103 portMUX_TYPE s_time_update_lock = portMUX_INITIALIZER_UNLOCKED;
104
105
esp_timer_impl_lock(void)106 void esp_timer_impl_lock(void)
107 {
108 portENTER_CRITICAL(&s_time_update_lock);
109 }
110
esp_timer_impl_unlock(void)111 void esp_timer_impl_unlock(void)
112 {
113 portEXIT_CRITICAL(&s_time_update_lock);
114 }
115
esp_timer_impl_get_counter_reg(void)116 uint64_t IRAM_ATTR esp_timer_impl_get_counter_reg(void)
117 {
118 uint32_t lo, hi;
119 uint32_t lo_start = REG_READ(COUNT_LO_REG);
120 uint32_t div = REG_GET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER);
121 /* The peripheral doesn't have a bit to indicate that the update is done, so we poll the
122 * lower 32 bit part of the counter until it changes, or a timeout expires.
123 */
124 REG_WRITE(UPDATE_REG, 1);
125 do {
126 lo = REG_READ(COUNT_LO_REG);
127 } while (lo == lo_start && div-- > 0);
128
129 /* Since this function is called without a critical section, verify that LO and HI
130 * registers are consistent. That is, if an interrupt happens between reading LO and
131 * HI registers, and esp_timer_impl_get_time is called from an ISR, then try to
132 * detect this by the change in LO register value, and re-read both registers.
133 */
134 do {
135 lo_start = lo;
136 hi = REG_READ(COUNT_HI_REG);
137 lo = REG_READ(COUNT_LO_REG);
138 } while (lo != lo_start);
139
140 timer_64b_reg_t result = {
141 .lo = lo,
142 .hi = hi
143 };
144 return result.val;
145 }
146
esp_timer_impl_get_time(void)147 int64_t IRAM_ATTR esp_timer_impl_get_time(void)
148 {
149 if (s_alarm_handler == NULL) {
150 return 0;
151 }
152 return esp_timer_impl_get_counter_reg() / TICKS_PER_US;
153 }
154
155 int64_t esp_timer_get_time(void) __attribute__((alias("esp_timer_impl_get_time")));
156
esp_timer_impl_set_alarm(uint64_t timestamp)157 void IRAM_ATTR esp_timer_impl_set_alarm(uint64_t timestamp)
158 {
159 portENTER_CRITICAL_SAFE(&s_time_update_lock);
160 int64_t offset = TICKS_PER_US * 2;
161 uint64_t now_time = esp_timer_impl_get_counter_reg();
162 timer_64b_reg_t alarm = { .val = MAX(timestamp * TICKS_PER_US, now_time + offset) };
163 do {
164 REG_CLR_BIT(CONFIG_REG, TIMG_LACT_ALARM_EN);
165 REG_WRITE(ALARM_LO_REG, alarm.lo);
166 REG_WRITE(ALARM_HI_REG, alarm.hi);
167 REG_SET_BIT(CONFIG_REG, TIMG_LACT_ALARM_EN);
168 now_time = esp_timer_impl_get_counter_reg();
169 int64_t delta = (int64_t)alarm.val - (int64_t)now_time;
170 if (delta <= 0 && REG_GET_FIELD(INT_ST_REG, TIMG_LACT_INT_ST) == 0) {
171 // new alarm is less than the counter and the interrupt flag is not set
172 offset += abs((int)delta) + TICKS_PER_US * 2;
173 alarm.val = now_time + offset;
174 } else {
175 // finish if either (alarm > counter) or the interrupt flag is already set.
176 break;
177 }
178 } while(1);
179 portEXIT_CRITICAL_SAFE(&s_time_update_lock);
180 }
181
timer_alarm_isr(void * arg)182 static void IRAM_ATTR timer_alarm_isr(void *arg)
183 {
184 /* Clear interrupt status */
185 REG_WRITE(INT_CLR_REG, TIMG_LACT_INT_CLR);
186 /* Call the upper layer handler */
187 (*s_alarm_handler)(arg);
188 }
189
esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)190 void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)
191 {
192 portENTER_CRITICAL(&s_time_update_lock);
193 assert(apb_ticks_per_us >= 3 && "divider value too low");
194 assert(apb_ticks_per_us % TICKS_PER_US == 0 && "APB frequency (in MHz) should be divisible by TICK_PER_US");
195 REG_SET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER, apb_ticks_per_us / TICKS_PER_US);
196 portEXIT_CRITICAL(&s_time_update_lock);
197 }
198
esp_timer_impl_advance(int64_t time_diff_us)199 void esp_timer_impl_advance(int64_t time_diff_us)
200 {
201 portENTER_CRITICAL(&s_time_update_lock);
202 uint64_t now = esp_timer_impl_get_time();
203 timer_64b_reg_t dst = { .val = (now + time_diff_us) * TICKS_PER_US };
204 REG_WRITE(LOAD_LO_REG, dst.lo);
205 REG_WRITE(LOAD_HI_REG, dst.hi);
206 REG_WRITE(LOAD_REG, 1);
207 portEXIT_CRITICAL(&s_time_update_lock);
208 }
209
esp_timer_impl_init(intr_handler_t alarm_handler)210 esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
211 {
212 s_alarm_handler = alarm_handler;
213
214 periph_module_enable(PERIPH_LACT);
215
216 /* Reset the state */
217 REG_WRITE(CONFIG_REG, 0);
218 REG_WRITE(LOAD_LO_REG, 0);
219 REG_WRITE(LOAD_HI_REG, 0);
220 REG_WRITE(ALARM_LO_REG, UINT32_MAX);
221 REG_WRITE(ALARM_HI_REG, UINT32_MAX);
222 REG_WRITE(LOAD_REG, 1);
223 REG_SET_BIT(INT_CLR_REG, TIMG_LACT_INT_CLR);
224
225 esp_err_t err = esp_intr_alloc(INTR_SOURCE_LACT,
226 ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_IRAM,
227 &timer_alarm_isr, NULL, &s_timer_interrupt_handle);
228
229 if (err != ESP_OK) {
230 ESP_EARLY_LOGE(TAG, "esp_intr_alloc failed (0x%0x)", err);
231 return err;
232 }
233
234 /* In theory, this needs a shared spinlock with the timer group driver.
235 * However since esp_timer_impl_init is called early at startup, this
236 * will not cause issues in practice.
237 */
238 REG_SET_BIT(INT_ENA_REG, TIMG_LACT_INT_ENA);
239
240 esp_timer_impl_update_apb_freq(esp_clk_apb_freq() / 1000000);
241
242 REG_SET_BIT(CONFIG_REG, TIMG_LACT_INCREASE |
243 TIMG_LACT_LEVEL_INT_EN |
244 TIMG_LACT_EN);
245
246 // Set the step for the sleep mode when the timer will work
247 // from a slow_clk frequency instead of the APB frequency.
248 uint32_t slowclk_ticks_per_us = esp_clk_slowclk_cal_get() * TICKS_PER_US;
249 REG_SET_FIELD(RTC_STEP_REG, TIMG_LACT_RTC_STEP_LEN, slowclk_ticks_per_us);
250
251 ESP_ERROR_CHECK( esp_intr_enable(s_timer_interrupt_handle) );
252
253 return ESP_OK;
254 }
255
esp_timer_impl_deinit(void)256 void esp_timer_impl_deinit(void)
257 {
258 REG_WRITE(CONFIG_REG, 0);
259 REG_SET_BIT(INT_CLR_REG, TIMG_LACT_INT_CLR);
260 /* TODO: also clear TIMG_LACT_INT_ENA; however see the note in esp_timer_impl_init. */
261
262 esp_intr_disable(s_timer_interrupt_handle);
263 esp_intr_free(s_timer_interrupt_handle);
264 s_timer_interrupt_handle = NULL;
265 }
266
267 /* FIXME: This value is safe for 80MHz APB frequency, should be modified to depend on clock frequency. */
esp_timer_impl_get_min_period_us(void)268 uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us(void)
269 {
270 return 50;
271 }
272
esp_timer_impl_get_alarm_reg(void)273 uint64_t esp_timer_impl_get_alarm_reg(void)
274 {
275 portENTER_CRITICAL_SAFE(&s_time_update_lock);
276 timer_64b_reg_t alarm = {
277 .lo = REG_READ(ALARM_LO_REG),
278 .hi = REG_READ(ALARM_HI_REG)
279 };
280 portEXIT_CRITICAL_SAFE(&s_time_update_lock);
281 return alarm.val;
282 }
283
284 void esp_timer_private_update_apb_freq(uint32_t apb_ticks_per_us) __attribute__((alias("esp_timer_impl_update_apb_freq")));
285 void esp_timer_private_advance(int64_t time_us) __attribute__((alias("esp_timer_impl_advance")));
286 void esp_timer_private_lock(void) __attribute__((alias("esp_timer_impl_lock")));
287 void esp_timer_private_unlock(void) __attribute__((alias("esp_timer_impl_unlock")));
288