1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <common/bk_include.h>
16 #include <components/ate.h>
17 #include <os/mem.h>
18 #include <driver/flash.h>
19 #include <os/os.h>
20 #include "bk_pm_model.h"
21 #include "flash_driver.h"
22 #include "flash_hal.h"
23 #include "sys_driver.h"
24
25 #if CONFIG_FLASH_QUAD_ENABLE
26 #include "flash_bypass.h"
27 extern UINT8 flash_get_line_mode(void);
28 extern void flash_set_line_mode(UINT8 mode);
29 #endif
30
31 typedef struct {
32 flash_hal_t hal;
33 uint32_t flash_id;
34 const flash_config_t *flash_cfg;
35 } flash_driver_t;
36
37 #define FLASH_GET_PROTECT_CFG(cfg) ((cfg) & FLASH_STATUS_REG_PROTECT_MASK)
38 #define FLASH_GET_CMP_CFG(cfg) (((cfg) >> FLASH_STATUS_REG_PROTECT_OFFSET) & FLASH_STATUS_REG_PROTECT_MASK)
39
40 #define FLASH_RETURN_ON_DRIVER_NOT_INIT() do {\
41 if (!s_flash_is_init) {\
42 return BK_ERR_FLASH_NOT_INIT;\
43 }\
44 } while(0)
45
46 #define FLASH_RETURN_ON_WRITE_ADDR_OUT_OF_RANGE(addr, len) do {\
47 if ((addr >= s_flash.flash_cfg->flash_size) ||\
48 (len > s_flash.flash_cfg->flash_size) ||\
49 ((addr + len) > s_flash.flash_cfg->flash_size)) {\
50 FLASH_LOGW("write error[addr:0x%x len:0x%x]\r\n", addr, len);\
51 return BK_ERR_FLASH_ADDR_OUT_OF_RANGE;\
52 }\
53 } while(0)
54
55 static const flash_config_t flash_config[] = {
56 /* flash_id, status_reg_size, flash_size, line_mode, cmp_post, protect_post, protect_mask, protect_all, protect_none, protect_half, unprotect_last_block. quad_en_post, quad_en_val, coutinuous_read_mode_bits_val, mode_sel*/
57 {0x1C7016, 1, FLASH_SIZE_4M, FLASH_LINE_MODE_TWO, 0, 2, 0x1F, 0x1F, 0x00, 0x16, 0x01B, 0, 0, 0xA5, 0x01}, //en_25qh32b
58 {0x1C7015, 1, FLASH_SIZE_2M, FLASH_LINE_MODE_TWO, 0, 2, 0x1F, 0x1F, 0x00, 0x0d, 0x0d, 0, 0, 0xA5, 0x01}, //en_25qh16b
59 {0x0B4014, 2, FLASH_SIZE_1M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x0C, 0x101, 9, 1, 0xA0, 0x01}, //xtx_25f08b
60 {0x0B4015, 2, FLASH_SIZE_2M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x0D, 0x101, 9, 1, 0xA0, 0x01}, //xtx_25f16b
61 #if CONFIG_FLASH_QUAD_ENABLE
62 {0x1C4116, 2, FLASH_SIZE_4M, FLASH_LINE_MODE_FOUR, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x00E, 9, 1, 0xA0, 0x02}, //en_25qe32a
63 #else
64 {0x1C4116, 1, FLASH_SIZE_4M, FLASH_LINE_MODE_TWO, 0, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x00E, 0, 0, 0xA0, 0x01}, //en_25qe32a
65 #endif
66 #if CONFIG_FLASH_QUAD_ENABLE
67 {0x0B4016, 2, FLASH_SIZE_4M, FLASH_LINE_MODE_FOUR, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x101, 9, 1, 0xA0, 0x02}, //xtx_25f32b
68 #else
69 {0x0B4016, 2, FLASH_SIZE_4M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x101, 9, 1, 0xA0, 0x01}, //xtx_25f32b
70 #endif
71 {0x0B4017, 2, FLASH_SIZE_8M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x05, 0x00, 0x0E, 0x109, 9, 1, 0xA0, 0x01}, //xtx_25f64b
72 {0x0E4016, 2, FLASH_SIZE_4M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x101, 9, 1, 0xA0, 0x01}, //xtx_FT25H32
73 {0xC84015, 2, FLASH_SIZE_2M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x0D, 0x101, 9, 1, 0xA0, 0x01}, //gd_25q16c
74 #if CONFIG_FLASH_QUAD_ENABLE
75 {0xC84016, 2, FLASH_SIZE_4M, FLASH_LINE_MODE_FOUR, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x00E, 9, 1, 0xA0, 0x02}, //gd_25q32c
76 #else
77 {0xC84016, 1, FLASH_SIZE_4M, FLASH_LINE_MODE_TWO, 0, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x00E, 0, 0, 0xA0, 0x01}, //gd_25q32c
78 #endif
79 {0xC86515, 2, FLASH_SIZE_2M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x0D, 0x101, 9, 1, 0xA0, 0x01}, //gd_25w16e
80
81 {0xEF4016, 2, FLASH_SIZE_4M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x00, 0x101, 9, 1, 0xA0, 0x01}, //w_25q32(bfj)
82 {0x204016, 2, FLASH_SIZE_4M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x0E, 0x101, 9, 1, 0xA0, 0x01}, //xmc_25qh32b
83 {0xC22315, 1, FLASH_SIZE_2M, FLASH_LINE_MODE_TWO, 0, 2, 0x0F, 0x0F, 0x00, 0x0A, 0x00E, 6, 1, 0xA5, 0x01}, //mx_25v16b
84 {0xEB6015, 2, FLASH_SIZE_2M, FLASH_LINE_MODE_TWO, 14, 2, 0x1F, 0x1F, 0x00, 0x0D, 0x101, 9, 1, 0xA0, 0x01}, //zg_th25q16b
85 {0x000000, 2, FLASH_SIZE_4M, FLASH_LINE_MODE_TWO, 0, 2, 0x1F, 0x00, 0x00, 0x00, 0x000, 0, 0, 0x00, 0x01}, //default
86 };
87
88 static flash_driver_t s_flash = {0};
89 static bool s_flash_is_init = false;
90 static beken_mutex_t s_flash_mutex = NULL;
91 static PM_STATUS flash_ps_status;
92 static flash_ps_callback_t s_flash_ps_suspend_cb = NULL;
93 static flash_ps_callback_t s_flash_ps_resume_cb = NULL;
94 #if (CONFIG_SOC_BK7256XX)
95 static uint32_t s_hold_low_speed_status = 0;
96 #endif
97
flash_ps_suspend(UINT32 ps_level)98 static UINT32 flash_ps_suspend(UINT32 ps_level)
99 {
100 PM_STATUS *flash_ps_status_ptr = &flash_ps_status;
101
102 switch (ps_level) {
103 case NORMAL_PS:
104 case LOWVOL_PS:
105 case DEEP_PS:
106 case IDLE_PS:
107 if (s_flash_ps_suspend_cb) {
108 s_flash_ps_suspend_cb();
109 }
110 if (FLASH_LINE_MODE_FOUR == bk_flash_get_line_mode())
111 bk_flash_set_line_mode(FLASH_LINE_MODE_TWO);
112 flash_ps_status_ptr->bits.unconditional_ps_sleeped = 1;
113 flash_ps_status_ptr->bits.normal_ps_sleeped = 1;
114 flash_ps_status_ptr->bits.lowvol_ps_sleeped = 1;
115 flash_ps_status_ptr->bits.deep_ps_sleeped = 1;
116 break;
117 default:
118 break;
119 }
120 return 0;
121 }
122
flash_ps_resume(UINT32 ps_level)123 static UINT32 flash_ps_resume(UINT32 ps_level)
124 {
125 PM_STATUS *flash_ps_status_ptr = &flash_ps_status;
126
127 switch (ps_level) {
128 case NORMAL_PS:
129 case LOWVOL_PS:
130 case DEEP_PS:
131 case IDLE_PS:
132 if (FLASH_LINE_MODE_FOUR == bk_flash_get_line_mode())
133 bk_flash_set_line_mode(FLASH_LINE_MODE_FOUR);
134 if (s_flash_ps_resume_cb) {
135 s_flash_ps_resume_cb();
136 }
137 flash_ps_status_ptr->bits.unconditional_ps_sleeped = 0;
138 flash_ps_status_ptr->bits.normal_ps_sleeped = 0;
139 flash_ps_status_ptr->bits.lowvol_ps_sleeped = 0;
140 flash_ps_status_ptr->bits.deep_ps_sleeped = 0;
141 break;
142 default:
143 break;
144 }
145 return 0;
146 }
147
flash_ps_get_status(UINT32 flag)148 static PM_STATUS flash_ps_get_status(UINT32 flag)
149 {
150 return flash_ps_status;
151 }
152
153 static DEV_PM_OPS_S flash_ps_ops = {
154 .pm_init = NULL,
155 .pm_deinit = NULL,
156 .suspend = flash_ps_suspend,
157 .resume = flash_ps_resume,
158 .status = flash_ps_get_status,
159 .get_sleep_time = NULL,
160 };
161
flash_init_common(void)162 static void flash_init_common(void)
163 {
164 int ret = rtos_init_mutex(&s_flash_mutex);
165 BK_ASSERT(kNoErr == ret);
166 }
167
flash_deinit_common(void)168 static void flash_deinit_common(void)
169 {
170 int ret = rtos_deinit_mutex(&s_flash_mutex);
171 BK_ASSERT(kNoErr == ret);
172 }
173
flash_get_current_config(void)174 static void flash_get_current_config(void)
175 {
176 bool cfg_success = false;
177
178 for (uint32_t i = 0; i < (ARRAY_SIZE(flash_config) - 1); i++) {
179 if (s_flash.flash_id == flash_config[i].flash_id) {
180 s_flash.flash_cfg = &flash_config[i];
181 cfg_success = true;
182 break;
183 }
184 }
185
186 if (!cfg_success) {
187 s_flash.flash_cfg = &flash_config[ARRAY_SIZE(flash_config) - 1];
188 FLASH_LOGW("don't config this flash, choose default config\r\n");
189 }
190 }
191
flash_get_protect_cfg(flash_protect_type_t type)192 static uint32_t flash_get_protect_cfg(flash_protect_type_t type)
193 {
194 switch (type) {
195 case FLASH_PROTECT_NONE:
196 return FLASH_GET_PROTECT_CFG(s_flash.flash_cfg->protect_none);
197 case FLASH_PROTECT_ALL:
198 return FLASH_GET_PROTECT_CFG(s_flash.flash_cfg->protect_all);
199 case FLASH_PROTECT_HALF:
200 return FLASH_GET_PROTECT_CFG(s_flash.flash_cfg->protect_half);
201 case FLASH_UNPROTECT_LAST_BLOCK:
202 return FLASH_GET_PROTECT_CFG(s_flash.flash_cfg->unprotect_last_block);
203 default:
204 return FLASH_GET_PROTECT_CFG(s_flash.flash_cfg->protect_all);
205 }
206 }
207
flash_set_protect_cfg(uint32_t * status_reg_val,uint32_t new_protect_cfg)208 static void flash_set_protect_cfg(uint32_t *status_reg_val, uint32_t new_protect_cfg)
209 {
210 *status_reg_val &= ~(s_flash.flash_cfg->protect_mask << s_flash.flash_cfg->protect_post);
211 *status_reg_val |= ((new_protect_cfg & s_flash.flash_cfg->protect_mask) << s_flash.flash_cfg->protect_post);
212 }
213
flash_get_cmp_cfg(flash_protect_type_t type)214 static uint32_t flash_get_cmp_cfg(flash_protect_type_t type)
215 {
216 switch (type) {
217 case FLASH_PROTECT_NONE:
218 return FLASH_GET_CMP_CFG(s_flash.flash_cfg->protect_none);
219 case FLASH_PROTECT_ALL:
220 return FLASH_GET_CMP_CFG(s_flash.flash_cfg->protect_all);
221 case FLASH_PROTECT_HALF:
222 return FLASH_GET_CMP_CFG(s_flash.flash_cfg->protect_half);
223 case FLASH_UNPROTECT_LAST_BLOCK:
224 return FLASH_GET_CMP_CFG(s_flash.flash_cfg->unprotect_last_block);
225 default:
226 return FLASH_GET_CMP_CFG(s_flash.flash_cfg->protect_all);
227 }
228 }
229
flash_set_cmp_cfg(uint32_t * status_reg_val,uint32_t new_cmp_cfg)230 static void flash_set_cmp_cfg(uint32_t *status_reg_val, uint32_t new_cmp_cfg)
231 {
232 *status_reg_val &= ~(FLASH_CMP_MASK << s_flash.flash_cfg->cmp_post);
233 *status_reg_val |= ((new_cmp_cfg & FLASH_CMP_MASK) << s_flash.flash_cfg->cmp_post);
234 }
235
flash_is_need_update_status_reg(uint32_t protect_cfg,uint32_t cmp_cfg,uint32_t status_reg_val)236 static bool flash_is_need_update_status_reg(uint32_t protect_cfg, uint32_t cmp_cfg, uint32_t status_reg_val)
237 {
238 uint32_t cur_protect_val_in_status_reg = (status_reg_val >> s_flash.flash_cfg->protect_post) & s_flash.flash_cfg->protect_mask;
239 uint32_t cur_cmp_val_in_status_reg = (status_reg_val >> s_flash.flash_cfg->cmp_post) & FLASH_CMP_MASK;
240
241 if (cur_protect_val_in_status_reg != protect_cfg ||
242 cur_cmp_val_in_status_reg != cmp_cfg) {
243 return true;
244 } else {
245 return false;
246 }
247 }
248
flash_set_protect_type(flash_protect_type_t type)249 static void flash_set_protect_type(flash_protect_type_t type)
250 {
251 uint32_t protect_cfg = flash_get_protect_cfg(type);
252 uint32_t cmp_cfg = flash_get_cmp_cfg(type);
253 uint32_t status_reg = flash_hal_read_status_reg(&s_flash.hal, s_flash.flash_cfg->status_reg_size);
254
255 if (flash_is_need_update_status_reg(protect_cfg, cmp_cfg, status_reg)) {
256 flash_set_protect_cfg(&status_reg, protect_cfg);
257 flash_set_cmp_cfg(&status_reg, cmp_cfg);
258
259 FLASH_LOGI("write status reg:%x, status_reg_size:%d\r\n", status_reg, s_flash.flash_cfg->status_reg_size);
260 flash_hal_write_status_reg(&s_flash.hal, s_flash.flash_cfg->status_reg_size, status_reg);
261 }
262 }
263
flash_set_qe(void)264 static void flash_set_qe(void)
265 {
266 uint32_t status_reg;
267
268 while (flash_hal_is_busy(&s_flash.hal));
269 status_reg = flash_hal_read_status_reg(&s_flash.hal, s_flash.flash_cfg->status_reg_size);
270 if (status_reg & (s_flash.flash_cfg->quad_en_val << s_flash.flash_cfg->quad_en_post)) {
271 return;
272 }
273
274 status_reg |= s_flash.flash_cfg->quad_en_val << s_flash.flash_cfg->quad_en_post;
275 flash_hal_write_status_reg(&s_flash.hal, s_flash.flash_cfg->status_reg_size, status_reg);
276 }
277
flash_set_qwfr(void)278 static void flash_set_qwfr(void)
279 {
280 flash_hal_set_mode(&s_flash.hal, s_flash.flash_cfg->mode_sel);
281 }
282
flash_read_common(uint8_t * buffer,uint32_t address,uint32_t len)283 static void flash_read_common(uint8_t *buffer, uint32_t address, uint32_t len)
284 {
285 uint32_t addr = address & (~FLASH_ADDRESS_MASK);
286 uint32_t buf[FLASH_BUFFER_LEN] = {0};
287 uint8_t *pb = (uint8_t *)&buf[0];
288
289 if (len == 0) {
290 return;
291 }
292
293 uint32_t int_level = rtos_disable_int();
294 while (flash_hal_is_busy(&s_flash.hal));
295 while (len) {
296 flash_hal_set_op_cmd_read(&s_flash.hal, addr);
297 addr += FLASH_BYTES_CNT;
298 for (uint32_t i = 0; i < FLASH_BUFFER_LEN; i++) {
299 buf[i] = flash_hal_read_data(&s_flash.hal);
300 }
301
302 for (uint32_t i = address % FLASH_BYTES_CNT; i < FLASH_BYTES_CNT; i++) {
303 *buffer++ = pb[i];
304 address++;
305 len--;
306 if (len == 0) {
307 break;
308 }
309 }
310 }
311 rtos_enable_int(int_level);
312 }
313
flash_write_common(const uint8_t * buffer,uint32_t address,uint32_t len)314 static bk_err_t flash_write_common(const uint8_t *buffer, uint32_t address, uint32_t len)
315 {
316 uint32_t buf[FLASH_BUFFER_LEN];
317 uint8_t *pb = (uint8_t *)&buf[0];
318 uint32_t addr = address & (~FLASH_ADDRESS_MASK);
319
320 FLASH_RETURN_ON_WRITE_ADDR_OUT_OF_RANGE(addr, len);
321
322 if (address % FLASH_BYTES_CNT)
323 flash_read_common(pb, addr, FLASH_BYTES_CNT);
324 else
325 os_memset(pb, 0xFF, FLASH_BYTES_CNT);
326
327 while (flash_hal_is_busy(&s_flash.hal));
328 while (len) {
329 if (len < FLASH_BYTES_CNT) {
330 flash_read_common(pb, addr, FLASH_BYTES_CNT);
331 while (flash_hal_is_busy(&s_flash.hal));
332 }
333 for (uint32_t i = address % FLASH_BYTES_CNT; i < FLASH_BYTES_CNT; i++) {
334 pb[i] = *buffer++;
335 address++;
336 len--;
337 if (len == 0) {
338 break;
339 }
340 }
341
342 uint32_t int_level = rtos_disable_int();
343 for (uint32_t i = 0; i < FLASH_BUFFER_LEN; i++) {
344 flash_hal_write_data(&s_flash.hal, buf[i]);
345 }
346 flash_hal_set_op_cmd_write(&s_flash.hal, addr);
347 rtos_enable_int(int_level);
348 addr += FLASH_BYTES_CNT;
349 os_memset(pb, 0xFF, FLASH_BYTES_CNT);
350 }
351 return BK_OK;
352 }
353
flash_lock(void)354 void flash_lock(void)
355 {
356 rtos_lock_mutex(&s_flash_mutex);
357 }
358
flash_unlock(void)359 void flash_unlock(void)
360 {
361 rtos_unlock_mutex(&s_flash_mutex);
362 }
363
bk_flash_set_line_mode(flash_line_mode_t line_mode)364 bk_err_t bk_flash_set_line_mode(flash_line_mode_t line_mode)
365 {
366 flash_hal_clear_qwfr(&s_flash.hal);
367
368 if (FLASH_LINE_MODE_TWO == line_mode) {
369 flash_hal_set_dual_mode(&s_flash.hal);
370 } else if (FLASH_LINE_MODE_FOUR == line_mode) {
371 flash_hal_set_quad_m_value(&s_flash.hal, s_flash.flash_cfg->coutinuous_read_mode_bits_val);
372 if (1 == s_flash.flash_cfg->quad_en_val) {
373 flash_set_qe();
374 }
375 flash_set_qwfr();
376 }
377
378 return BK_OK;
379 }
380
bk_flash_driver_init(void)381 bk_err_t bk_flash_driver_init(void)
382 {
383 if (s_flash_is_init) {
384 return BK_OK;
385 }
386 #if CONFIG_FLASH_QUAD_ENABLE
387 #if CONFIG_FLASH_ORIGIN_API
388 if (FLASH_LINE_MODE_FOUR == flash_get_line_mode())
389 flash_set_line_mode(FLASH_LINE_MODE_TWO);
390 #endif
391 #endif
392 os_memset(&s_flash, 0, sizeof(s_flash));
393 flash_hal_init(&s_flash.hal);
394 s_flash.flash_id = flash_hal_get_id(&s_flash.hal);
395 FLASH_LOGI("id=0x%x\r\n", s_flash.flash_id);
396 flash_get_current_config();
397 flash_set_protect_type(FLASH_UNPROTECT_LAST_BLOCK);
398 #if (0 == CONFIG_JTAG)
399 flash_hal_disable_cpu_data_wr(&s_flash.hal);
400 #endif
401 bk_flash_set_line_mode(s_flash.flash_cfg->line_mode);
402 flash_hal_set_default_clk(&s_flash.hal);
403 #if (CONFIG_SOC_BK7256XX)
404 bk_flash_clk_switch(FLASH_SPEED_HIGH, 0);
405 #endif
406
407 flash_init_common();
408 s_flash_is_init = true;
409
410 return BK_OK;
411 }
412
bk_flash_driver_deinit(void)413 bk_err_t bk_flash_driver_deinit(void)
414 {
415 if (!s_flash_is_init) {
416 return BK_OK;
417 }
418 flash_deinit_common();
419 s_flash_is_init = false;
420
421 return BK_OK;
422 }
423
bk_flash_erase_sector(uint32_t address)424 bk_err_t bk_flash_erase_sector(uint32_t address)
425 {
426 uint32_t erase_addr = address & FLASH_ERASE_SECTOR_MASK;
427
428 flash_ps_suspend(NORMAL_PS);
429 if (erase_addr >= s_flash.flash_cfg->flash_size) {
430 FLASH_LOGW("erase error:invalid address 0x%x\r\n", erase_addr);
431 return BK_ERR_FLASH_ADDR_OUT_OF_RANGE;
432 }
433
434 uint32_t int_level = rtos_disable_int();
435 flash_hal_erase_sector(&s_flash.hal, erase_addr);
436 rtos_enable_int(int_level);
437 flash_ps_resume(NORMAL_PS);
438
439 return BK_OK;
440 }
441
bk_flash_read_bytes(uint32_t address,uint8_t * user_buf,uint32_t size)442 bk_err_t bk_flash_read_bytes(uint32_t address, uint8_t *user_buf, uint32_t size)
443 {
444 if (address >= s_flash.flash_cfg->flash_size) {
445 FLASH_LOGW("read error:invalid address 0x%x\r\n", address);
446 return BK_ERR_FLASH_ADDR_OUT_OF_RANGE;
447 }
448 flash_read_common(user_buf, address, size);
449
450 return BK_OK;
451 }
452
bk_flash_write_bytes(uint32_t address,const uint8_t * user_buf,uint32_t size)453 bk_err_t bk_flash_write_bytes(uint32_t address, const uint8_t *user_buf, uint32_t size)
454 {
455 flash_ps_suspend(NORMAL_PS);
456 if (address >= s_flash.flash_cfg->flash_size) {
457 FLASH_LOGW("write error:invalid address 0x%x\r\n", address);
458 return BK_ERR_FLASH_ADDR_OUT_OF_RANGE;
459 }
460 flash_write_common(user_buf, address, size);
461 flash_ps_resume(NORMAL_PS);
462
463 return BK_OK;
464 }
465
bk_flash_get_id(void)466 uint32_t bk_flash_get_id(void)
467 {
468 flash_ps_suspend(NORMAL_PS);
469 s_flash.flash_id = flash_hal_get_id(&s_flash.hal);
470 flash_ps_resume(NORMAL_PS);
471 return s_flash.flash_id;
472 }
473
bk_flash_get_line_mode(void)474 flash_line_mode_t bk_flash_get_line_mode(void)
475 {
476 return s_flash.flash_cfg->line_mode;
477 }
478
bk_flash_set_clk_dpll(void)479 bk_err_t bk_flash_set_clk_dpll(void)
480 {
481 flash_ps_suspend(NORMAL_PS);
482 sys_drv_flash_set_dpll();
483 flash_hal_set_clk_dpll(&s_flash.hal);
484 flash_ps_resume(NORMAL_PS);
485
486 return BK_OK;
487 }
488
bk_flash_set_clk_dco(void)489 bk_err_t bk_flash_set_clk_dco(void)
490 {
491 flash_ps_suspend(NORMAL_PS);
492 sys_drv_flash_set_dco();
493 bool ate_enabled = ate_is_enabled();
494 flash_hal_set_clk_dco(&s_flash.hal, ate_enabled);
495 flash_ps_resume(NORMAL_PS);
496
497 return BK_OK;
498 }
499
500 #if (CONFIG_SOC_BK7256XX)
bk_flash_set_clk(flash_clk_src_t flash_src_clk,uint8_t flash_dpll_div)501 bk_err_t bk_flash_set_clk(flash_clk_src_t flash_src_clk, uint8_t flash_dpll_div)
502 {
503 if ((FLASH_CLK_DPLL == flash_src_clk) && (flash_dpll_div == 0)) {
504 FLASH_LOGE("flash 120M clock not support.\r\n");
505 return BK_FAIL;
506 }
507 if (FLASH_CLK_APLL == flash_src_clk) {
508 FLASH_LOGE("flash apll clock not support.\r\n");
509 return BK_FAIL;
510 }
511
512 uint32_t int_level = rtos_disable_int();
513 if((sys_drv_flash_get_clk_sel() == flash_src_clk) && (sys_drv_flash_get_clk_div() == flash_dpll_div)) {
514 rtos_enable_int(int_level);
515 return BK_OK;
516 }
517 if (FLASH_CLK_DPLL == flash_src_clk) {
518 sys_drv_flash_set_clk_div(flash_dpll_div);
519 }
520 sys_drv_flash_cksel(flash_src_clk);
521 rtos_enable_int(int_level);
522
523 return BK_OK;
524 }
525
bk_flash_clk_switch(uint32_t flash_speed_type,uint32_t modules)526 bk_err_t bk_flash_clk_switch(uint32_t flash_speed_type, uint32_t modules)
527 {
528 uint32_t int_level = rtos_disable_int();
529 switch (flash_speed_type) {
530 case FLASH_SPEED_LOW:
531 s_hold_low_speed_status |= modules;
532 FLASH_LOGD("%s: set low, 0x%x 0x%x\r\n", __func__, s_hold_low_speed_status, modules);
533 if (s_hold_low_speed_status) {
534 bk_flash_set_clk(FLASH_CLK_XTAL, FLASH_DPLL_DIV_VALUE_TEN);
535 }
536 break;
537
538 case FLASH_SPEED_HIGH:
539 s_hold_low_speed_status &= ~(modules);
540 FLASH_LOGD("%s: clear low bit, 0x%x 0x%x\r\n", __func__, s_hold_low_speed_status, modules);
541 if (0 == s_hold_low_speed_status) {
542 bk_flash_set_clk(FLASH_CLK_DPLL, FLASH_DPLL_DIV_VALUE_TEN);
543 }
544 break;
545 }
546 rtos_enable_int(int_level);
547
548 return BK_OK;
549 }
550 #endif
551
bk_flash_write_enable(void)552 bk_err_t bk_flash_write_enable(void)
553 {
554 flash_ps_suspend(NORMAL_PS);
555 flash_hal_write_enable(&s_flash.hal);
556 flash_ps_resume(NORMAL_PS);
557 return BK_OK;
558 }
559
bk_flash_write_disable(void)560 bk_err_t bk_flash_write_disable(void)
561 {
562 flash_ps_suspend(NORMAL_PS);
563 flash_hal_write_disable(&s_flash.hal);
564 flash_ps_resume(NORMAL_PS);
565 return BK_OK;
566 }
567
bk_flash_read_status_reg(void)568 uint16_t bk_flash_read_status_reg(void)
569 {
570 flash_ps_suspend(NORMAL_PS);
571 uint16_t sr_data = flash_hal_read_status_reg(&s_flash.hal, s_flash.flash_cfg->status_reg_size);
572 flash_ps_resume(NORMAL_PS);
573 return sr_data;
574 }
575
bk_flash_write_status_reg(uint16_t status_reg_data)576 bk_err_t bk_flash_write_status_reg(uint16_t status_reg_data)
577 {
578 flash_ps_suspend(NORMAL_PS);
579 flash_hal_write_status_reg(&s_flash.hal, s_flash.flash_cfg->status_reg_size, status_reg_data);
580 flash_ps_resume(NORMAL_PS);
581 return BK_OK;
582 }
583
bk_flash_get_protect_type(void)584 flash_protect_type_t bk_flash_get_protect_type(void)
585 {
586 uint32_t type = 0;
587 uint16_t protect_value = 0;
588
589 flash_ps_suspend(NORMAL_PS);
590 protect_value = flash_hal_get_protect_value(&s_flash.hal, s_flash.flash_cfg->status_reg_size,
591 s_flash.flash_cfg->protect_post, s_flash.flash_cfg->protect_mask,
592 s_flash.flash_cfg->cmp_post);
593 if (protect_value == s_flash.flash_cfg->protect_all)
594 type = FLASH_PROTECT_ALL;
595 else if (protect_value == s_flash.flash_cfg->protect_none)
596 type = FLASH_PROTECT_NONE;
597 else if (protect_value == s_flash.flash_cfg->protect_half)
598 type = FLASH_PROTECT_HALF;
599 else if (protect_value == s_flash.flash_cfg->unprotect_last_block)
600 type = FLASH_UNPROTECT_LAST_BLOCK;
601 else
602 type = -1;
603
604 flash_ps_resume(NORMAL_PS);
605 return type;
606 }
607
bk_flash_set_protect_type(flash_protect_type_t type)608 bk_err_t bk_flash_set_protect_type(flash_protect_type_t type)
609 {
610 flash_ps_suspend(NORMAL_PS);
611 flash_set_protect_type(type);
612 flash_ps_resume(NORMAL_PS);
613 return BK_OK;
614 }
615
616 /* This API is not used in bk7256xx */
flash_ps_pm_init(void)617 void flash_ps_pm_init(void)
618 {
619 PM_STATUS *flash_ps_status_ptr = &flash_ps_status;
620
621 bk_flash_set_clk_dco();
622 bk_flash_get_id();
623
624 flash_ps_status_ptr->bits.unconditional_ps_support = 1;
625 flash_ps_status_ptr->bits.unconditional_ps_suspend_allow = 1;
626 flash_ps_status_ptr->bits.unconditional_ps_resume_allow = 1;
627 flash_ps_status_ptr->bits.unconditional_ps_sleeped = 0;
628 flash_ps_status_ptr->bits.normal_ps_support = 1;
629 flash_ps_status_ptr->bits.normal_ps_suspend_allow = 1;
630 flash_ps_status_ptr->bits.normal_ps_resume_allow = 1;
631 flash_ps_status_ptr->bits.normal_ps_sleeped = 0;
632 flash_ps_status_ptr->bits.lowvol_ps_support = 1;
633 flash_ps_status_ptr->bits.lowvol_ps_suspend_allow = 1;
634 flash_ps_status_ptr->bits.lowvol_ps_resume_allow = 1;
635 flash_ps_status_ptr->bits.lowvol_ps_sleeped = 0;
636 flash_ps_status_ptr->bits.deep_ps_support = 1;
637 flash_ps_status_ptr->bits.deep_ps_suspend_allow = 1;
638 flash_ps_status_ptr->bits.deep_ps_resume_allow = 1;
639 flash_ps_status_ptr->bits.deep_ps_sleeped = 0;
640
641 dev_pm_register(PM_ID_FLASH, "flash", &flash_ps_ops);
642 }
643
bk_flash_is_driver_inited()644 bool bk_flash_is_driver_inited()
645 {
646 return s_flash_is_init;
647 }
648
bk_flash_get_current_total_size(void)649 uint32_t bk_flash_get_current_total_size(void)
650 {
651 return s_flash.flash_cfg->flash_size;
652 }
653
bk_flash_register_ps_suspend_callback(flash_ps_callback_t ps_suspend_cb)654 bk_err_t bk_flash_register_ps_suspend_callback(flash_ps_callback_t ps_suspend_cb)
655 {
656 s_flash_ps_suspend_cb = ps_suspend_cb;
657 return BK_OK;
658 }
659
bk_flash_register_ps_resume_callback(flash_ps_callback_t ps_resume_cb)660 bk_err_t bk_flash_register_ps_resume_callback(flash_ps_callback_t ps_resume_cb)
661 {
662 s_flash_ps_resume_cb = ps_resume_cb;
663 return BK_OK;
664 }
665
666