1 /** 2 **************************************************************************************** 3 * 4 * @file gr55xx_hal_gpio_ex.h 5 * @author BLE Driver Team 6 * @brief Header file containing extended macro of GPIO HAL library. 7 * 8 **************************************************************************************** 9 * @attention 10 #####Copyright (c) 2019 GOODIX 11 All rights reserved. 12 13 Redistribution and use in source and binary forms, with or without 14 modification, are permitted provided that the following conditions are met: 15 * Redistributions of source code must retain the above copyright 16 notice, this list of conditions and the following disclaimer. 17 * Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 * Neither the name of GOODIX nor the names of its contributors may be used 21 to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 POSSIBILITY OF SUCH DAMAGE. 35 **************************************************************************************** 36 */ 37 38 /** @addtogroup PERIPHERAL Peripheral Driver 39 * @{ 40 */ 41 42 /** @addtogroup HAL_DRIVER HAL Driver 43 * @{ 44 */ 45 46 /** @defgroup HAL_GPIOEx GPIOEx 47 * @brief GPIOEx HAL module driver. 48 * @{ 49 */ 50 51 /* Define to prevent recursive inclusion -------------------------------------*/ 52 #ifndef __GR55xx_HAL_GPIO_EX_H__ 53 #define __GR55xx_HAL_GPIO_EX_H__ 54 55 /* Includes ------------------------------------------------------------------*/ 56 #include "gr55xx_hal_def.h" 57 #include "gr55xx_ll_gpio.h" 58 59 #ifdef __cplusplus 60 extern "C" { 61 #endif 62 63 /* Exported types ------------------------------------------------------------*/ 64 65 /** 66 * @defgroup HAL_GPIOEX_MACRO Defines 67 * @{ 68 */ 69 70 /* Exported constants --------------------------------------------------------*/ 71 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants 72 * @{ 73 */ 74 75 /** @defgroup GPIOEx_Mux_Mode GPIOEx Mux Mode definition 76 * @{ 77 */ 78 #define GPIO_MUX_0 LL_GPIO_MUX_0 /**< GPIO Mux mode 0 */ 79 #define GPIO_MUX_1 LL_GPIO_MUX_1 /**< GPIO Mux mode 1 */ 80 #define GPIO_MUX_2 LL_GPIO_MUX_2 /**< GPIO Mux mode 2 */ 81 #define GPIO_MUX_3 LL_GPIO_MUX_3 /**< GPIO Mux mode 3 */ 82 #define GPIO_MUX_4 LL_GPIO_MUX_4 /**< GPIO Mux mode 4 */ 83 #define GPIO_MUX_5 LL_GPIO_MUX_5 /**< GPIO Mux mode 5 */ 84 #define GPIO_MUX_6 LL_GPIO_MUX_6 /**< GPIO Mux mode 6 */ 85 #define GPIO_MUX_7 LL_GPIO_MUX_7 /**< GPIO Mux mode 7 */ 86 #define GPIO_MUX_8 LL_GPIO_MUX_8 /**< GPIO Mux mode 8 */ 87 /** @} */ 88 89 /** @defgroup GPIOEx_Mux_Function_Selection GPIOEx Mux function selection 90 * @{ 91 */ 92 93 #if defined (GR551xx) 94 /*---------------------------------- GR551xx ------------------------------*/ 95 96 /** @defgroup GPIOEx_Common_Selection GPIO PIN common MUX selection(Available for all GPIO pins) 97 * @{ 98 */ 99 #define GPIO_PIN_MUX_TESTBUS GPIO_MUX_8 /**< GPIO PIN x Mux Select TESTBUS */ 100 101 #define GPIO_PIN_MUX_GPIO GPIO_MUX_7 /**< GPIO PIN x Mux Select GPIO */ 102 103 /** @} */ 104 105 /** @defgroup GPIOEx_GPIO0_PIN0_Mux_Selection GPIO0_PIN0 MUX selection 106 * @{ 107 */ 108 #define GPIO0_PIN0_MUX_SWD_CLK GPIO_MUX_0 /**< GPIO0_PIN0 Mux Select SWD_CLK */ 109 #define GPIO0_PIN0_MUX_I2C0_SCL GPIO_MUX_1 /**< GPIO0_PIN0 Mux Select I2C0_SCL */ 110 #define GPIO0_PIN0_MUX_I2C1_SCL GPIO_MUX_2 /**< GPIO0_PIN0 Mux Select I2C1_SCL */ 111 #define GPIO0_PIN0_MUX_UART1_RTS GPIO_MUX_3 /**< GPIO0_PIN0 Mux Select UART1_RTS */ 112 #define GPIO0_PIN0_MUX_UART0_TX GPIO_MUX_4 /**< GPIO0_PIN0 Mux Select UART0_TX */ 113 #define GPIO0_PIN0_MUX_UART1_TX GPIO_MUX_5 /**< GPIO0_PIN0 Mux Select UART1_TX */ 114 #define GPIO0_PIN0_MUX_UART0_RTS GPIO_MUX_6 /**< GPIO0_PIN0 Mux Select UART0_RTS */ 115 /** @} */ 116 117 /** @defgroup GPIOEx_GPIO0_PIN1_Mux_Selection GPIO0_PIN1 MUX selection 118 * @{ 119 */ 120 #define GPIO0_PIN1_MUX_SWD_IO GPIO_MUX_0 /**< GPIO0_PIN1 Mux Select SWD_IO */ 121 #define GPIO0_PIN1_MUX_I2C0_SDA GPIO_MUX_1 /**< GPIO0_PIN1 Mux Select I2C0_SDA */ 122 #define GPIO0_PIN1_MUX_I2C1_SDA GPIO_MUX_2 /**< GPIO0_PIN1 Mux Select I2C1_SDA */ 123 #define GPIO0_PIN1_MUX_UART1_CTS GPIO_MUX_3 /**< GPIO0_PIN1 Mux Select UART1_CTS */ 124 #define GPIO0_PIN1_MUX_UART0_RX GPIO_MUX_4 /**< GPIO0_PIN1 Mux Select UART0_RX */ 125 #define GPIO0_PIN1_MUX_UART1_RX GPIO_MUX_5 /**< GPIO0_PIN1 Mux Select UART1_RX */ 126 #define GPIO0_PIN1_MUX_UART0_CTS GPIO_MUX_6 /**< GPIO0_PIN1 Mux Select UART0_CTS */ 127 /** @} */ 128 129 /** @defgroup GPIOEx_GPIO0_PIN2_Mux_Selection GPIO0_PIN2 MUX selection 130 * @{ 131 */ 132 #define GPIO0_PIN2_MUX_UART0_CTS GPIO_MUX_0 /**< GPIO0_PIN2 Mux Select UART0_CTS */ 133 #define GPIO0_PIN2_MUX_SIM_PRESENCE GPIO_MUX_1 /**< GPIO0_PIN2 Mux Select SIM_PRESENCE */ 134 #define GPIO0_PIN2_MUX_SWV GPIO_MUX_2 /**< GPIO0_PIN2 Mux Select SWV */ 135 #define GPIO0_PIN2_MUX_SPIS_CS_N GPIO_MUX_3 /**< GPIO0_PIN2 Mux Select SPIS_CS_N */ 136 #define GPIO0_PIN2_MUX_I2C0_SDA GPIO_MUX_4 /**< GPIO0_PIN2 Mux Select I2C0_SDA */ 137 #define GPIO0_PIN2_MUX_PWM0_A GPIO_MUX_5 /**< GPIO0_PIN2 Mux Select PWM0_A */ 138 #define GPIO0_PIN2_MUX_FERP_TRIG GPIO_MUX_6 /**< GPIO0_PIN2 Mux Select FERP_TRIG */ 139 /** @} */ 140 141 /** @defgroup GPIOEx_GPIO0_PIN3_Mux_Selection GPIO0_PIN3 MUX selection 142 * @{ 143 */ 144 #define GPIO0_PIN3_MUX_UART0_TX GPIO_MUX_0 /**< GPIO0_PIN3 Mux Select UART0_TX */ 145 #define GPIO0_PIN3_MUX_SIM_RST_N GPIO_MUX_1 /**< GPIO0_PIN3 Mux Select SIM_RST_N */ 146 #define GPIO0_PIN3_MUX_SPIM_CLK GPIO_MUX_2 /**< GPIO0_PIN3 Mux Select SPIM_CLK */ 147 #define GPIO0_PIN3_MUX_SPIS_CLK GPIO_MUX_3 /**< GPIO0_PIN3 Mux Select SPIS_CLK */ 148 #define GPIO0_PIN3_MUX_SPIM_CS1 GPIO_MUX_4 /**< GPIO0_PIN3 Mux Select SPIM_CS1 */ 149 #define GPIO0_PIN3_MUX_PWM0_B GPIO_MUX_5 /**< GPIO0_PIN3 Mux Select PWM0_B */ 150 #define GPIO0_PIN3_MUX_COEX_BLE_TX GPIO_MUX_6 /**< GPIO0_PIN3 Mux Select COEX_BLE_TX */ 151 /** @} */ 152 153 /** @defgroup GPIOEx_GPIO0_PIN4_Mux_Selection GPIO0_PIN4 MUX selection 154 * @{ 155 */ 156 #define GPIO0_PIN4_MUX_UART0_RX GPIO_MUX_0 /**< GPIO0_PIN4 Mux Select UART0_RX */ 157 #define GPIO0_PIN4_MUX_SIM_IO GPIO_MUX_1 /**< GPIO0_PIN4 Mux Select SIM_IO */ 158 #define GPIO0_PIN4_MUX_SPIM_MOSI GPIO_MUX_2 /**< GPIO0_PIN4 Mux Select SPIM_MOSI */ 159 #define GPIO0_PIN4_MUX_SPIS_MISO GPIO_MUX_3 /**< GPIO0_PIN4 Mux Select SPIS_MISO */ 160 #define GPIO0_PIN4_MUX_SPIM_CS0 GPIO_MUX_4 /**< GPIO0_PIN4 Mux Select SPIM_CS0 */ 161 #define GPIO0_PIN4_MUX_PWM0_C GPIO_MUX_5 /**< GPIO0_PIN3 Mux Select PWM0_C */ 162 #define GPIO0_PIN4_MUX_COEX_BLE_RX GPIO_MUX_6 /**< GPIO0_PIN4 Mux Select COEX_BLE_RX */ 163 /** @} */ 164 165 /** @defgroup GPIOEx_GPIO0_PIN5_Mux_Selection GPIO0_PIN5 MUX selection 166 * @{ 167 */ 168 #define GPIO0_PIN5_MUX_UART0_RTS GPIO_MUX_0 /**< GPIO0_PIN5 Mux Select UART0_RTS */ 169 #define GPIO0_PIN5_MUX_SIM_CLK GPIO_MUX_1 /**< GPIO0_PIN5 Mux Select SIM_CLK */ 170 #define GPIO0_PIN5_MUX_SPIM_MISO GPIO_MUX_2 /**< GPIO0_PIN5 Mux Select SPIM_MISO */ 171 #define GPIO0_PIN5_MUX_SPIS_MOSI GPIO_MUX_3 /**< GPIO0_PIN5 Mux Select SPIS_MOSI */ 172 // #define GPIO0_PIN5_MUX_SPIM_MISO GPIO_MUX_4 /**< GPIO0_PIN5 Mux Select SPIM_MISO */ 173 #define GPIO0_PIN5_MUX_I2C0_SCL GPIO_MUX_5 /**< GPIO0_PIN5 Mux Select I2C0_SCL */ 174 #define GPIO0_PIN5_MUX_COEX_WLAN_TX GPIO_MUX_6 /**< GPIO0_PIN5 Mux Select COEX_WLAN_TX */ 175 /** @} */ 176 177 /** @defgroup GPIOEx_GPIO0_PIN6_Mux_Selection GPIO0_PIN6 MUX selection 178 * @{ 179 */ 180 #define GPIO0_PIN6_MUX_I2SM_WS GPIO_MUX_0 /**< GPIO0_PIN6 Mux Select I2S_WS */ 181 #define GPIO0_PIN6_MUX_I2SS_WS GPIO_MUX_1 /**< GPIO0_PIN6 Mux Select I2S_S_WS */ 182 #define GPIO0_PIN6_MUX_SPIM_CS0 GPIO_MUX_2 /**< GPIO0_PIN6 Mux Select SPIM_CS0 */ 183 #define GPIO0_PIN6_MUX_UART1_RX GPIO_MUX_3 /**< GPIO0_PIN6 Mux Select UART1_RX */ 184 #define GPIO0_PIN6_MUX_SPIM_MOSI GPIO_MUX_4 /**< GPIO0_PIN6 Mux Select SPIM_MOSI */ 185 #define GPIO0_PIN6_MUX_I2C0_SDA GPIO_MUX_5 /**< GPIO0_PIN6 Mux Select I2C0_SDA */ 186 #define GPIO0_PIN6_MUX_COEX_WLAN_RX GPIO_MUX_6 /**< GPIO0_PIN6 Mux Select COEX_WLAN_RX */ 187 /** @} */ 188 189 /** @defgroup GPIOEx_GPIO0_PIN7_Mux_Selection GPIO0_PIN7 MUX selection 190 * @{ 191 */ 192 #define GPIO0_PIN7_MUX_I2SM_TX_SDO GPIO_MUX_0 /**< GPIO0_PIN7 Mux Select I2SM_TX_SDO */ 193 #define GPIO0_PIN7_MUX_I2SS_TX_SDO GPIO_MUX_1 /**< GPIO0_PIN7 Mux Select I2SS_TX_SDO */ 194 #define GPIO0_PIN7_MUX_SPIM_CS1 GPIO_MUX_2 /**< GPIO0_PIN7 Mux Select SPIM_CS1 */ 195 #define GPIO0_PIN7_MUX_UART1_TX GPIO_MUX_3 /**< GPIO0_PIN7 Mux Select UART1_TX */ 196 #define GPIO0_PIN7_MUX_SPIM_CLK GPIO_MUX_4 /**< GPIO0_PIN7 Mux Select SPIM_CLK */ 197 #define GPIO0_PIN7_MUX_PWM1_A GPIO_MUX_5 /**< GPIO0_PIN7 Mux Select PWM1_A */ 198 #define GPIO0_PIN7_MUX_COEX_BLE_PROC GPIO_MUX_6 /**< GPIO0_PIN7 Mux Select COEX_BLE_PROC */ 199 /** @} */ 200 201 /** @defgroup GPIOEx_GPIO0_PIN8_Mux_Selection GPIO0_PIN8 MUX selection 202 * @{ 203 */ 204 #define GPIO0_PIN8_MUX_XQSPIM_IO_0 GPIO_MUX_0 /**< GPIO0_PIN8 Mux Select XQSPIM_IO_0 */ 205 #define GPIO0_PIN8_MUX_I2C1_SDA GPIO_MUX_1 /**< GPIO0_PIN8 Mux Select I2C1_SDA */ 206 #define GPIO0_PIN8_MUX_QSPIM1_IO_0 GPIO_MUX_2 /**< GPIO0_PIN8 Mux Select QSPIM1_IO_0 */ 207 #define GPIO0_PIN8_MUX_UART1_RX GPIO_MUX_3 /**< GPIO0_PIN8 Mux Select UART1_RX */ 208 #define GPIO0_PIN8_MUX_PWM1_B GPIO_MUX_5 /**< GPIO0_PIN8 Mux Select PWM1_B */ 209 /** @} */ 210 211 /** @defgroup GPIOEx_GPIO0_PIN9_Mux_Selection GPIO0_PIN9 MUX selection 212 * @{ 213 */ 214 #define GPIO0_PIN9_MUX_XQSPIM_CLK GPIO_MUX_0 /**< GPIO0_PIN9 Mux Select XQSPIM_CLK */ 215 #define GPIO0_PIN9_MUX_I2C1_SCL GPIO_MUX_1 /**< GPIO0_PIN9 Mux Select I2C1_SCL */ 216 #define GPIO0_PIN9_MUX_QSPIM1_CLK GPIO_MUX_2 /**< GPIO0_PIN9 Mux Select QSPIM1_CLK */ 217 #define GPIO0_PIN9_MUX_UART1_TX GPIO_MUX_3 /**< GPIO0_PIN9 Mux Select UART1_TX */ 218 #define GPIO0_PIN9_MUX_PWM1_C GPIO_MUX_5 /**< GPIO0_PIN9 Mux Select PWM1_C */ 219 /** @} */ 220 221 /** @defgroup GPIOEx_GPIO0_PIN10_Mux_Selection GPIO0_PIN10 MUX selection 222 * @{ 223 */ 224 #define GPIO0_PIN10_MUX_I2SM_RX_SDI GPIO_MUX_0 /**< GPIO0_PIN10 Mux Select I2SM_RX_SDI */ 225 #define GPIO0_PIN10_MUX_I2SS_RX_SDI GPIO_MUX_1 /**< GPIO0_PIN10 Mux Select I2SS_RX_SDI */ 226 #define GPIO0_PIN10_MUX_UART0_TX GPIO_MUX_2 /**< GPIO0_PIN10 Mux Select UART0_TX */ 227 #define GPIO0_PIN10_MUX_I2C0_SCL GPIO_MUX_4 /**< GPIO0_PIN10 Mux Select I2C0_SCL */ 228 #define GPIO0_PIN10_MUX_PWM1_B GPIO_MUX_5 /**< GPIO0_PIN10 Mux Select PWM1_B */ 229 #define GPIO0_PIN10_MUX_COEX_BLE_TX GPIO_MUX_6 /**< GPIO0_PIN10 Mux Select COEX_BLE_TX */ 230 /** @} */ 231 232 /** @defgroup GPIOEx_GPIO0_PIN11_Mux_Selection GPIO0_PIN11 MUX selection 233 * @{ 234 */ 235 #define GPIO0_PIN11_MUX_I2SM_SCLK GPIO_MUX_0 /**< GPIO0_PIN10 Mux Select I2SM_SCLK */ 236 #define GPIO0_PIN11_MUX_I2SS_SCLK GPIO_MUX_1 /**< GPIO0_PIN10 Mux Select I2SS_SCLK */ 237 #define GPIO0_PIN11_MUX_UART0_RX GPIO_MUX_2 /**< GPIO0_PIN10 Mux Select UART0_RX */ 238 #define GPIO0_PIN11_MUX_I2C0_SDA GPIO_MUX_4 /**< GPIO0_PIN10 Mux Select I2C0_SDA */ 239 #define GPIO0_PIN11_MUX_PWM1_C GPIO_MUX_5 /**< GPIO0_PIN10 Mux Select PWM1_C */ 240 /** @} */ 241 242 /** @defgroup GPIOEx_GPIO0_PIN12_Mux_Selection GPIO0_PIN12 MUX selection 243 * @{ 244 */ 245 #define GPIO0_PIN12_MUX_XQSPIM_IO_3 GPIO_MUX_0 /**< GPIO0_PIN12 Mux Select XQSPIM_IO_3 */ 246 #define GPIO0_PIN12_MUX_SPIM_CLK GPIO_MUX_1 /**< GPIO0_PIN12 Mux Select SPIM_CLK */ 247 #define GPIO0_PIN12_MUX_QSPIM1_IO3 GPIO_MUX_2 /**< GPIO0_PIN12 Mux Select QSPIM1_IO3 */ 248 #define GPIO0_PIN12_MUX_SIM_PRESENCE GPIO_MUX_3 /**< GPIO0_PIN12 Mux Select SIM_PRESENCE */ 249 #define GPIO0_PIN12_MUX_I2SM_WS GPIO_MUX_4 /**< GPIO0_PIN12 Mux Select I2SM_WS */ 250 #define GPIO0_PIN12_MUX_I2SS_WS GPIO_MUX_5 /**< GPIO0_PIN12 Mux Select I2SS_WS */ 251 #define GPIO0_PIN12_MUX_SPIS_CS GPIO_MUX_6 /**< GPIO0_PIN12 Mux Select I2SS_WS */ 252 /** @} */ 253 254 /** @defgroup GPIOEx_GPIO0_PIN13_Mux_Selection GPIO0_PIN13 MUX selection 255 * @{ 256 */ 257 #define GPIO0_PIN13_MUX_XQSPIM_IO_2 GPIO_MUX_0 /**< GPIO0_PIN13 Mux Select XQSPIM_IO_2 */ 258 #define GPIO0_PIN13_MUX_SPIM_MOSI GPIO_MUX_1 /**< GPIO0_PIN13 Mux Select SPIM_MOSI */ 259 #define GPIO0_PIN13_MUX_QSPIM1_IO_2 GPIO_MUX_2 /**< GPIO0_PIN13 Mux Select QSPIM1_IO_2 */ 260 #define GPIO0_PIN13_MUX_SIM_RST_N GPIO_MUX_3 /**< GPIO0_PIN13 Mux Select SIM_RST_N */ 261 #define GPIO0_PIN13_MUX_I2SM_TX_SDO GPIO_MUX_4 /**< GPIO0_PIN13 Mux Select I2SM_TX_SDO */ 262 #define GPIO0_PIN13_MUX_I2SS_TX_SDO GPIO_MUX_5 /**< GPIO0_PIN13 Mux Select I2SS_TX_SDO */ 263 #define GPIO0_PIN13_MUX_SPIS_CLK GPIO_MUX_6 /**< GPIO0_PIN13 Mux Select SPIS_CLK */ 264 /** @} */ 265 266 /** @defgroup GPIOEx_GPIO0_PIN14_Mux_Selection GPIO0_PIN14 MUX selection 267 * @{ 268 */ 269 #define GPIO0_PIN14_MUX_XQSPIM_IO_1 GPIO_MUX_0 /**< GPIO0_PIN14 Mux Select XQSPIM_IO_1 */ 270 #define GPIO0_PIN14_MUX_SPIM_MISO GPIO_MUX_1 /**< GPIO0_PIN14 Mux Select SPIM_MISO */ 271 #define GPIO0_PIN14_MUX_QSPIM1_IO1 GPIO_MUX_2 /**< GPIO0_PIN14 Mux Select QSPIM1_IO1 */ 272 #define GPIO0_PIN14_MUX_SIM_IO GPIO_MUX_3 /**< GPIO0_PIN14 Mux Select SIM_IO */ 273 #define GPIO0_PIN14_MUX_I2SM_RX_SDI GPIO_MUX_4 /**< GPIO0_PIN14 Mux Select I2SM_RX_SDI */ 274 #define GPIO0_PIN14_MUX_I2SS_RX_SDI GPIO_MUX_5 /**< GPIO0_PIN14 Mux Select I2SS_RX_SDI */ 275 #define GPIO0_PIN14_MUX_SPIS_MISO GPIO_MUX_6 /**< GPIO0_PIN14 Mux Select SPIS_MISO */ 276 /** @} */ 277 278 /** @defgroup GPIOEx_GPIO0_PIN15_Mux_Selection GPIO0_PIN15 MUX selection 279 * @{ 280 */ 281 #define GPIO0_PIN15_MUX_XQSPIM_CS_N GPIO_MUX_0 /**< GPIO0_PIN15 Mux Select QSPIM_CS_N */ 282 #define GPIO0_PIN15_MUX_SPIM_CS0 GPIO_MUX_1 /**< GPIO0_PIN15 Mux Select SPIM_CS0 */ 283 #define GPIO0_PIN15_MUX_QSPIM1_CS_N GPIO_MUX_2 /**< GPIO0_PIN15 Mux Select QSPIM1_CS_N */ 284 #define GPIO0_PIN15_MUX_SIM_CLK GPIO_MUX_3 /**< GPIO0_PIN15 Mux Select SIM_CLK */ 285 #define GPIO0_PIN15_MUX_I2SM_SCLK GPIO_MUX_4 /**< GPIO0_PIN15 Mux Select I2SM_SCLK */ 286 #define GPIO0_PIN15_MUX_I2SS_SCLK GPIO_MUX_5 /**< GPIO0_PIN15 Mux Select I2SS_SCLK */ 287 #define GPIO0_PIN15_MUX_SPIS_MOSI GPIO_MUX_6 /**< GPIO0_PIN15 Mux Select SPIS_MOSI */ 288 /** @} */ 289 290 /** @defgroup GPIOEx_GPIO1_PIN0_Mux_Selection GPIO1_PIN0 MUX selection 291 * @{ 292 */ 293 #define GPIO1_PIN0_MUX_SPIM_MISO GPIO_MUX_0 /**< GPIO1_PIN0 Mux Select SPIM_MISO */ 294 #define GPIO1_PIN0_MUX_SPIS_MOSI GPIO_MUX_1 /**< GPIO1_PIN0 Mux Select SPIS_MOSI */ 295 #define GPIO1_PIN0_MUX_SIM_IO GPIO_MUX_2 /**< GPIO1_PIN0 Mux Select SIM_IO */ 296 #define GPIO1_PIN0_MUX_I2SM_RX_SDI GPIO_MUX_3 /**< GPIO1_PIN0 Mux Select I2SM_RX_SDI */ 297 #define GPIO1_PIN0_MUX_I2SS_RX_SDI GPIO_MUX_4 /**< GPIO1_PIN0 Mux Select I2SS_RX_SDI */ 298 #define GPIO1_PIN0_MUX_QSPIM0_IO_1 GPIO_MUX_5 /**< GPIO1_PIN0 Mux Select QSPIM0_IO_1 */ 299 #define GPIO1_PIN0_MUX_ISO_SYNC GPIO_MUX_6 /**< GPIO1_PIN0 Mux Select ISO_SYNC */ 300 /** @} */ 301 302 /** @defgroup GPIOEx_GPIO1_PIN1_Mux_Selection GPIO1_PIN1 MUX selection 303 * @{ 304 */ 305 #define GPIO1_PIN1_MUX_SPIM_CS0 GPIO_MUX_0 /**< GPIO1_PIN1 Mux Select SPIM_CS0 */ 306 #define GPIO1_PIN1_MUX_SPIS_CS GPIO_MUX_1 /**< GPIO1_PIN1 Mux Select SPIS_CS */ 307 #define GPIO1_PIN1_MUX_SIM_CLK GPIO_MUX_2 /**< GPIO1_PIN1 Mux Select SIM_CLK */ 308 #define GPIO1_PIN1_MUX_I2SM_SCLK GPIO_MUX_3 /**< GPIO1_PIN1 Mux Select I2SM_SCLK */ 309 #define GPIO1_PIN1_MUX_I2SS_SCLK GPIO_MUX_4 /**< GPIO1_PIN1 Mux Select I2SS_SCLK */ 310 #define GPIO1_PIN1_MUX_QSPIM0_IO_2 GPIO_MUX_5 /**< GPIO1_PIN1 Mux Select QSPIM0_IO_2 */ 311 #define GPIO1_PIN1_MUX_COEX_BLE_RX GPIO_MUX_6 /**< GPIO1_PIN1 Mux Select COEX_BLE_RX */ 312 /** @} */ 313 314 /** @defgroup GPIOEx_GPIO1_PIN2_Mux_Selection GPIO1_PIN2 MUX selection 315 * @{ 316 */ 317 #define GPIO1_PIN2_MUX_QSPIM0_CS_N GPIO_MUX_0 /**< GPIO1_PIN2 Mux Select QSPIM0_CS_N */ 318 #define GPIO1_PIN2_MUX_XQSPIM_CS_N GPIO_MUX_1 /**< GPIO1_PIN2 Mux Select XQSPIM_CS_N */ 319 /** @} */ 320 321 /** @defgroup GPIOEx_GPIO1_PIN3_Mux_Selection GPIO1_PIN3 MUX selection 322 * @{ 323 */ 324 #define GPIO1_PIN3_MUX_QSPIM0_IO_3 GPIO_MUX_0 /**< GPIO1_PIN3 Mux Select QSPIM0_IO_3 */ 325 #define GPIO1_PIN3_MUX_XQSPIM_IO_3 GPIO_MUX_1 /**< GPIO1_PIN3 Mux Select XQSPIM_IO_3 */ 326 /** @} */ 327 328 /** @defgroup GPIOEx_GPIO1_PIN4_Mux_Selection GPIO1_PIN4 MUX selection 329 * @{ 330 */ 331 #define GPIO1_PIN4_MUX_QSPIM0_CLK GPIO_MUX_0 /**< GPIO1_PIN4 Mux Select QSPIM0_CLK */ 332 #define GPIO1_PIN4_MUX_XQSPIM_CLK GPIO_MUX_1 /**< GPIO1_PIN4 Mux Select XQSPIM_CLK */ 333 /** @} */ 334 335 /** @defgroup GPIOEx_GPIO1_PIN5_Mux_Selection GPIO1_PIN5 MUX selection 336 * @{ 337 */ 338 #define GPIO1_PIN5_MUX_QSPIM0_IO_2 GPIO_MUX_0 /**< GPIO1_PIN5 Mux Select QSPIM0_IO_2 */ 339 #define GPIO1_PIN5_MUX_XQSPIM_IO_2 GPIO_MUX_1 /**< GPIO1_PIN5 Mux Select XQSPIM_IO_2 */ 340 /** @} */ 341 342 /** @defgroup GPIOEx_GPIO1_PIN6_Mux_Selection GPIO1_PIN6 MUX selection 343 * @{ 344 */ 345 #define GPIO1_PIN6_MUX_QSPIM0_IO_1 GPIO_MUX_0 /**< GPIO1_PIN6 Mux Select QSPIM0_IO_1 */ 346 #define GPIO1_PIN6_MUX_XQSPIM_IO_1 GPIO_MUX_1 /**< GPIO1_PIN6 Mux Select XQSPIM_IO_1 */ 347 /** @} */ 348 349 /** @defgroup GPIOEx_GPIO1_PIN7_Mux_Selection GPIO1_PIN7 MUX selection 350 * @{ 351 */ 352 #define GPIO1_PIN7_MUX_QSPIM0_IO_0 GPIO_MUX_0 /**< GPIO1_PIN7 Mux Select QSPIM0_IO_0 */ 353 #define GPIO1_PIN7_MUX_XQSPIM_IO_0 GPIO_MUX_1 /**< GPIO1_PIN7 Mux Select XQSPIM_IO_0 */ 354 /** @} */ 355 356 /** @defgroup GPIOEx_GPIO1_PIN8_Mux_Selection GPIO1_PIN8 MUX selection 357 * @{ 358 */ 359 #define GPIO1_PIN8_MUX_SPIM_CLK GPIO_MUX_0 /**< GPIO1_PIN8 Mux Select SPIM_CLK */ 360 #define GPIO1_PIN8_MUX_SPIS_CLK GPIO_MUX_1 /**< GPIO1_PIN8 Mux Select SPIS_CLK */ 361 #define GPIO1_PIN8_MUX_SIM_PRESENCE GPIO_MUX_2 /**< GPIO1_PIN8 Mux Select SIM_PRESENCE */ 362 #define GPIO1_PIN8_MUX_I2SM_WS GPIO_MUX_3 /**< GPIO1_PIN8 Mux Select I2SM_WS */ 363 #define GPIO1_PIN8_MUX_I2SS_WS GPIO_MUX_4 /**< GPIO1_PIN8 Mux Select I2SS_WS */ 364 #define GPIO1_PIN8_MUX_QSPIM0_CLK GPIO_MUX_5 /**< GPIO1_PIN8 Mux Select QSPIM0_CLK */ 365 #define GPIO1_PIN8_MUX_COEX_WLAN_TX GPIO_MUX_6 /**< GPIO1_PIN8 Mux Select COEX_WLAN_TX */ 366 /** @} */ 367 368 /** @defgroup GPIOEx_GPIO1_PIN9_Mux_Selection GPIO1_PIN9 MUX selection 369 * @{ 370 */ 371 #define GPIO1_PIN9_MUX_SPIM_MOSI GPIO_MUX_0 /**< GPIO1_PIN9 Mux Select SPIM_MOSI */ 372 #define GPIO1_PIN9_MUX_SPIS_MISO GPIO_MUX_1 /**< GPIO1_PIN9 Mux Select SPIS_MISO */ 373 #define GPIO1_PIN9_MUX_SIM_RST_N GPIO_MUX_2 /**< GPIO1_PIN9 Mux Select SIM_RST_N */ 374 #define GPIO1_PIN9_MUX_I2SM_TX_SD0 GPIO_MUX_3 /**< GPIO1_PIN9 Mux Select I2SM_TX_SD0 */ 375 #define GPIO1_PIN9_MUX_I2SS_TX_SD0 GPIO_MUX_4 /**< GPIO1_PIN9 Mux Select I2SS_TX_SD0 */ 376 #define GPIO1_PIN9_MUX_QSPIM0_IO_0 GPIO_MUX_5 /**< GPIO1_PIN9 Mux Select QSPIM0_IO_0 */ 377 #define GPIO1_PIN9_MUX_COEX_BLE_PROC GPIO_MUX_6 /**< GPIO1_PIN9 Mux Select COEX_BLE_PROC */ 378 /** @} */ 379 380 /** @defgroup GPIOEx_GPIO1_PIN10_Mux_Selection GPIO1_PIN10 MUX selection 381 * @{ 382 */ 383 #define GPIO1_PIN10_MUX_I2C1_SDA GPIO_MUX_0 /**< GPIO1_PIN10 Mux Select I2C1_SDA */ 384 #define GPIO1_PIN10_MUX_UART1_RX GPIO_MUX_1 /**< GPIO1_PIN10 Mux Select UART1_RX */ 385 #define GPIO1_PIN10_MUX_I2C0_SDA GPIO_MUX_2 /**< GPIO1_PIN10 Mux Select I2C0_SDA */ 386 #define GPIO1_PIN10_MUX_PWM0_C GPIO_MUX_3 /**< GPIO1_PIN10 Mux Select PWM0_C */ 387 #define GPIO1_PIN10_MUX_PWM1_C GPIO_MUX_4 /**< GPIO1_PIN10 Mux Select PWM5 */ 388 #define GPIO1_PIN10_MUX_UART0_RX GPIO_MUX_5 /**< GPIO1_PIN10 Mux Select UART0_RX */ 389 /** @} */ 390 391 /** @defgroup GPIOEx_GPIO1_PIN11_Mux_Selection GPIO1_PIN11 MUX selection 392 * @{ 393 */ 394 #define GPIO1_PIN11_MUX_UART1_RTS GPIO_MUX_1 /**< GPIO1_PIN11 Mux Select UART1_RTS */ 395 #define GPIO1_PIN11_MUX_UART0_RTS GPIO_MUX_5 /**< GPIO1_PIN11 Mux Select UART0_RTS */ 396 /** @} */ 397 398 /** @defgroup GPIOEx_GPIO1_PIN12_Mux_Selection GPIO1_PIN12 MUX selection 399 * @{ 400 */ 401 #define GPIO1_PIN12_MUX_UART1_CTS GPIO_MUX_1 /**< GPIO1_PIN12 Mux Select UART1_CTS */ 402 #define GPIO1_PIN12_MUX_UART0_CTS GPIO_MUX_5 /**< GPIO1_PIN12 Mux Select UART0_CTS */ 403 /** @} */ 404 405 /** @defgroup GPIOEx_GPIO1_PIN13_Mux_Selection GPIO1_PIN13 MUX selection 406 * @{ 407 */ 408 409 /** @} */ 410 411 /** @defgroup GPIOEx_GPIO1_PIN14_Mux_Selection GPIO1_PIN14 MUX selection 412 * @{ 413 */ 414 #define GPIO1_PIN14_MUX_I2C1_SCL GPIO_MUX_0 /**< GPIO1_PIN14 Mux Select I2C1_SCL */ 415 #define GPIO1_PIN14_MUX_UART1_TX GPIO_MUX_1 /**< GPIO1_PIN14 Mux Select UART1_TX */ 416 #define GPIO1_PIN14_MUX_I2C0_SCL GPIO_MUX_2 /**< GPIO1_PIN14 Mux Select I2C0_SCL */ 417 #define GPIO1_PIN14_MUX_PWM0_B GPIO_MUX_3 /**< GPIO1_PIN14 Mux Select PWM0_B */ 418 #define GPIO1_PIN14_MUX_PWM1_B GPIO_MUX_4 /**< GPIO1_PIN14 Mux Select PWM1_B */ 419 #define GPIO1_PIN14_MUX_UART0_TX GPIO_MUX_5 /**< GPIO1_PIN14 Mux Select UART0_TX */ 420 #define GPIO1_PIN14_MUX_COEX_BLE_TX GPIO_MUX_6 /**< GPIO1_PIN14 Mux Select COEX_BLE_TX */ 421 /** @} */ 422 423 /** @defgroup GPIOEx_GPIO1_PIN15_Mux_Selection GPIO1_PIN15 MUX selection 424 * @{ 425 */ 426 #define GPIO1_PIN15_MUX_SPIM_CS1 GPIO_MUX_0 /**< GPIO1_PIN15 Mux Select SPIM_CS1 */ 427 #define GPIO1_PIN15_MUX_PWM0_A GPIO_MUX_3 /**< GPIO1_PIN15 Mux Select PWM0_A */ 428 #define GPIO1_PIN15_MUX_PWM1_A GPIO_MUX_4 /**< GPIO1_PIN15 Mux Select PWM1_A */ 429 #define GPIO1_PIN15_MUX_QSPIM0_IO_3 GPIO_MUX_5 /**< GPIO1_PIN15 Mux Select QSPIM0_IO_3 */ 430 #define GPIO1_PIN15_MUX_COEX_WLAN_TX GPIO_MUX_6 /**< GPIO1_PIN15 Mux Select COEX_WLAN_TX */ 431 /** @} */ 432 433 /** 434 * @brief Check if GPIO Mux mode is valid. 435 * @param __MUX__ GPIO mux mode. 436 * @retval SET (__ACTION__ is valid) or RESET (__ACTION__ is invalid) 437 */ 438 #define IS_GPIO_MUX(__MUX__) (((__MUX__) <= GPIO_MUX_8)) 439 440 /*------------------------------------------------------------------------------------------*/ 441 #endif /* GR551xx */ 442 443 /** @} */ 444 445 /** @} */ 446 447 /* Exported macro ------------------------------------------------------------*/ 448 /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros 449 * @{ 450 */ 451 452 /** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index 453 * @{ 454 */ 455 #if defined(GR551xx) 456 457 /** 458 * @brief Get GPIO Port Index. 459 * @param __GPIOx__ GPIO instance. 460 * @retval Port Index. 461 */ 462 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIO0))? 0U : 1U) 463 464 #endif /* GR551xx */ 465 /** @} */ 466 467 /** @defgroup GPIOEx_Get_Port_IRQNum GPIOEx_Get Port IRQ number 468 * @{ 469 */ 470 #if defined(GR551xx) 471 472 /** 473 * @brief Get GPIO Port IRQ number. 474 * @param __GPIOx__ GPIO instance. 475 * @retval Port IRQ number. 476 */ 477 #define GPIO_GET_IRQNUM(__GPIOx__) (((__GPIOx__) == (GPIO0))? EXT0_IRQn : EXT1_IRQn) 478 479 #endif /* GR551xx */ 480 481 /** @} */ 482 483 /** @} */ 484 485 /** @} */ 486 487 #ifdef __cplusplus 488 } 489 #endif 490 491 #endif /* __GR55xx_HAL_GPIO_EX_H__ */ 492 493 /** @} */ 494 495 /** @} */ 496 497 /** @} */ 498