1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef __DAC_TYPES_H__ 16 #define __DAC_TYPES_H__ 17 18 #pragma once 19 20 #include "soc/soc_caps.h" 21 #include "hal/adc_types.h" 22 #include "sdkconfig.h" 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 typedef enum { 29 DAC_CHANNEL_1 = 0, /*!< DAC channel 1 is GPIO25(ESP32) / GPIO17(ESP32S2) */ 30 DAC_CHANNEL_2 = 1, /*!< DAC channel 2 is GPIO26(ESP32) / GPIO18(ESP32S2) */ 31 DAC_CHANNEL_MAX, 32 } dac_channel_t; 33 34 /** 35 * @brief The multiple of the amplitude of the cosine wave generator. The max amplitude is VDD3P3_RTC. 36 */ 37 typedef enum { 38 DAC_CW_SCALE_1 = 0x0, /*!< 1/1. Default. */ 39 DAC_CW_SCALE_2 = 0x1, /*!< 1/2. */ 40 DAC_CW_SCALE_4 = 0x2, /*!< 1/4. */ 41 DAC_CW_SCALE_8 = 0x3, /*!< 1/8. */ 42 } dac_cw_scale_t; 43 44 /** 45 * @brief Set the phase of the cosine wave generator output. 46 */ 47 typedef enum { 48 DAC_CW_PHASE_0 = 0x2, /*!< Phase shift +0° */ 49 DAC_CW_PHASE_180 = 0x3, /*!< Phase shift +180° */ 50 } dac_cw_phase_t; 51 52 /** 53 * @brief Config the cosine wave generator function in DAC module. 54 */ 55 typedef struct { 56 dac_channel_t en_ch; /*!< Enable the cosine wave generator of DAC channel. */ 57 dac_cw_scale_t scale; /*!< Set the amplitude of the cosine wave generator output. */ 58 dac_cw_phase_t phase; /*!< Set the phase of the cosine wave generator output. */ 59 uint32_t freq; /*!< Set frequency of cosine wave generator output. Range: 130(130Hz) ~ 55000(100KHz). */ 60 int8_t offset; /*!< Set the voltage value of the DC component of the cosine wave generator output. 61 Note: Unreasonable settings can cause waveform to be oversaturated. Range: -128 ~ 127. */ 62 } dac_cw_config_t; 63 64 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 65 66 /** 67 * @brief DAC digital controller (DMA mode) work mode. 68 */ 69 typedef enum { 70 DAC_CONV_NORMAL, /*!< The data in the DMA buffer is simultaneously output to the enable channel of the DAC. */ 71 DAC_CONV_ALTER, /*!< The data in the DMA buffer is alternately output to the enable channel of the DAC. */ 72 DAC_CONV_MAX 73 } dac_digi_convert_mode_t; 74 75 /** 76 * @brief DAC digital controller (DMA mode) configuration parameters. 77 */ 78 typedef struct { 79 dac_digi_convert_mode_t mode; /*!<DAC digital controller (DMA mode) work mode. See ``dac_digi_convert_mode_t``. */ 80 uint32_t interval; /*!<The number of interval clock cycles for the DAC digital controller to output voltage. 81 The unit is the divided clock. Range: 1 ~ 4095. 82 Expression: `dac_output_freq` = `controller_clk` / interval. Refer to ``adc_digi_clk_t``. 83 Note: The sampling rate of each channel is also related to the conversion mode (See ``dac_digi_convert_mode_t``) and pattern table settings. */ 84 adc_digi_clk_t dig_clk; /*!<DAC digital controller clock divider settings. Refer to ``adc_digi_clk_t``. 85 Note: The clocks of the DAC digital controller use the ADC digital controller clock divider. */ 86 } dac_digi_config_t; 87 88 #endif //CONFIG_IDF_TARGET_ESP32S2 89 90 91 #ifdef __cplusplus 92 } 93 #endif /* __cplusplus */ 94 #endif /* __DAC_TYPES_H__ */ 95