1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #pragma once
16
17 #include <stdint.h>
18 #include "soc/soc_caps.h"
19 #include "soc/soc.h"
20 #include "xtensa/xtensa_api.h"
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /**
27 * @brief enable interrupts specified by the mask
28 *
29 * @param mask bitmask of interrupts that needs to be enabled
30 */
intr_cntrl_ll_enable_interrupts(uint32_t mask)31 static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask)
32 {
33 xt_ints_on(mask);
34 }
35
36 /**
37 * @brief disable interrupts specified by the mask
38 *
39 * @param mask bitmask of interrupts that needs to be disabled
40 */
intr_cntrl_ll_disable_interrupts(uint32_t mask)41 static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
42 {
43 xt_ints_off(mask);
44 }
45
46 /**
47 * @brief checks if given interrupt number has a valid handler
48 *
49 * @param intr interrupt number ranged from 0 to 31
50 * @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1
51 * @return true for valid handler, false otherwise
52 */
intr_cntrl_ll_has_handler(uint8_t intr,uint8_t cpu)53 static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
54 {
55 return xt_int_has_handler(intr, cpu);
56 }
57
58 /**
59 * @brief sets interrupt handler and optional argument of a given interrupt number
60 *
61 * @param intr interrupt number ranged from 0 to 31
62 * @param handler handler invoked when an interrupt occurs
63 * @param arg optional argument to pass to the handler
64 */
intr_cntrl_ll_set_int_handler(uint8_t intr,interrupt_handler_t handler,void * arg)65 static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
66 {
67 xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
68 }
69
70 /**
71 * @brief Gets argument passed to handler of a given interrupt number
72 *
73 * @param intr interrupt number ranged from 0 to 31
74 *
75 * @return argument used by handler of passed interrupt number
76 */
intr_cntrl_ll_get_int_handler_arg(uint8_t intr)77 static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
78 {
79 return xt_get_interrupt_handler_arg(intr);
80 }
81
82 /**
83 * @brief Disables interrupts that are not located in iram
84 *
85 * @param newmask mask of interrupts needs to be disabled
86 * @return oldmask where to store old interrupts state
87 */
intr_cntrl_ll_disable_int_mask(uint32_t newmask)88 static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask)
89 {
90 return xt_int_disable_mask(newmask);
91 }
92
93 /**
94 * @brief Enables interrupts that are not located in iram
95 *
96 * @param newmask mask of interrupts needs to be disabled
97 */
intr_cntrl_ll_enable_int_mask(uint32_t newmask)98 static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
99 {
100 xt_int_enable_mask(newmask);
101 }
102
103 /**
104 * @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
105 *
106 * @param intr interrupt number ranged from 0 to 31
107 */
intr_cntrl_ll_edge_int_acknowledge(int intr)108 static inline void intr_cntrl_ll_edge_int_acknowledge(int intr)
109 {
110 xthal_set_intclear(1 << intr);
111 }
112
113 #ifdef __cplusplus
114 }
115 #endif
116