1 /****************************************************************************** 2 * 3 * Copyright(c) 2015 - 2021 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _HAL_HALMAC_H_ 16 #define _HAL_HALMAC_H_ 17 18 #include <drv_types.h> /* adapter_to_dvobj(), struct intf_hdl and etc. */ 19 #include <hal_data.h> /* struct hal_spec_t */ 20 #ifdef CONFIG_HALMAC_RS 21 #include "halmac-rs/halmac_api.h" /* struct halmac_adapter* and etc. */ 22 #else /* !CONFIG_HALMAC_RS */ 23 #include "halmac/halmac_api.h" /* struct halmac_adapter* and etc. */ 24 #endif /* !CONFIG_HALMAC_RS */ 25 26 /* HALMAC Definition for Driver */ 27 #define RTW_HALMAC_H2C_MAX_SIZE 8 28 #define RTW_HALMAC_BA_SSN_RPT_SIZE 4 29 30 #define dvobj_set_halmac(d, mac) ((d)->halmac = (mac)) 31 #define dvobj_to_halmac(d) ((struct halmac_adapter *)((d)->halmac)) 32 #define adapter_to_halmac(p) dvobj_to_halmac(adapter_to_dvobj(p)) 33 34 /* for H2C cmd */ 35 #define MAX_H2C_BOX_NUMS 4 36 #define MESSAGE_BOX_SIZE 4 37 #define EX_MESSAGE_BOX_SIZE 4 38 39 typedef enum _RTW_HALMAC_MODE { 40 RTW_HALMAC_MODE_NORMAL, 41 RTW_HALMAC_MODE_WIFI_TEST, 42 } RTW_HALMAC_MODE; 43 44 union rtw_phy_para_data { 45 struct _mac { 46 u32 value; /* value to be set in bit mask(msk) */ 47 u32 msk; /* bit mask */ 48 u16 offset; /* address */ 49 u8 msk_en; /* 0/1 for msk invalid/valid */ 50 u8 size; /* Unit is bytes, and value should be 1/2/4 */ 51 } mac; 52 struct _bb { 53 u32 value; 54 u32 msk; 55 u16 offset; 56 u8 msk_en; 57 u8 size; 58 } bb; 59 struct _rf { 60 u32 value; 61 u32 msk; 62 u8 offset; 63 u8 msk_en; 64 /* 65 * 0: path A 66 * 1: path B 67 * 2: path C 68 * 3: path D 69 */ 70 u8 path; 71 } rf; 72 struct _delay { 73 /* 74 * 0: microsecond (us) 75 * 1: millisecond (ms) 76 */ 77 u8 unit; 78 u16 value; 79 } delay; 80 }; 81 82 struct rtw_phy_parameter { 83 /* 84 * 0: MAC register 85 * 1: BB register 86 * 2: RF register 87 * 3: Delay 88 * 0xFF: Latest(End) command 89 */ 90 u8 cmd; 91 union rtw_phy_para_data data; 92 }; 93 94 struct rtw_halmac_bcn_ctrl { 95 u8 rx_bssid_fit:1; /* 0:HW handle beacon, 1:ignore */ 96 u8 txbcn_rpt:1; /* Enable TXBCN report in ad hoc and AP mode */ 97 u8 tsf_update:1; /* Update TSF when beacon or probe response */ 98 u8 enable_bcn:1; /* Enable beacon related functions */ 99 u8 rxbcn_rpt:1; /* Enable RXBCNOK report */ 100 u8 p2p_ctwin:1; /* Enable P2P CTN WINDOWS function */ 101 u8 p2p_bcn_area:1; /* Enable P2P BCN area on function */ 102 }; 103 104 extern struct halmac_platform_api rtw_halmac_platform_api; 105 106 /* HALMAC API for Driver(HAL) */ 107 u8 rtw_halmac_read8(struct intf_hdl *, u32 addr); 108 u16 rtw_halmac_read16(struct intf_hdl *, u32 addr); 109 u32 rtw_halmac_read32(struct intf_hdl *, u32 addr); 110 void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); 111 #ifdef CONFIG_SDIO_INDIRECT_ACCESS 112 u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr); 113 u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr); 114 u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr); 115 #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ 116 int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value); 117 int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value); 118 int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value); 119 120 /* Software Information */ 121 void rtw_halmac_get_version(char *str, u32 len); 122 123 /* Software setting before Initialization */ 124 int rtw_halmac_preinit_sdio_io_indirect(struct dvobj_priv *d, bool enable); 125 126 /* Software Initialization */ 127 int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api); 128 int rtw_halmac_deinit_adapter(struct dvobj_priv *); 129 130 /* Get operations */ 131 int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue); 132 int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size); 133 int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size); 134 int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy); 135 int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size); 136 int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size); 137 int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size); 138 int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz); 139 int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size); 140 int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size); 141 int rtw_halmac_get_tx_dma_ch_map(struct dvobj_priv *d, u8 *dma_ch_map, u8 map_size); 142 int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size); 143 int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size); 144 int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num); 145 int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 146 int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type); 147 int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); 148 /*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/ 149 150 /* Set operations */ 151 int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info); 152 int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size); 153 int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 154 int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 155 int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); 156 int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type); 157 int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport); 158 int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space); 159 int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); 160 int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid); 161 int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw); 162 int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop); 163 int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable); 164 165 /* Functions */ 166 int rtw_halmac_poweron(struct dvobj_priv *); 167 int rtw_halmac_poweroff(struct dvobj_priv *); 168 int rtw_halmac_init_hal(struct dvobj_priv *); 169 int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize); 170 int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath); 171 int rtw_halmac_deinit_hal(struct dvobj_priv *); 172 int rtw_halmac_self_verify(struct dvobj_priv *); 173 int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout); 174 int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize); 175 int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath); 176 int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem); 177 int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem); 178 int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable); 179 int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c); 180 int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size); 181 182 /* eFuse */ 183 int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); 184 int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size); 185 int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); 186 int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 187 int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 188 int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size); 189 int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); 190 int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); 191 int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 192 int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 193 194 int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); 195 int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); 196 197 int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer); 198 int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable); 199 200 /* Specific function APIs*/ 201 int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size); 202 int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *); 203 int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para); 204 int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment); 205 int rtw_halmac_dpk(struct dvobj_priv *d, u8 *buf, u32 bufsz); 206 int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para); 207 int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode); 208 void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on); 209 int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable); 210 int rtw_halmac_rfe_ctrl_cfg(struct dvobj_priv *d, u8 gpio); 211 #ifdef CONFIG_PNO_SUPPORT 212 int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable); 213 #endif 214 215 #ifdef CONFIG_SDIO_HCI 216 int rtw_halmac_query_tx_page_num(struct dvobj_priv *); 217 int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page); 218 u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size); 219 int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size); 220 u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq); 221 int rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format); 222 #endif /* CONFIG_SDIO_HCI */ 223 224 #ifdef CONFIG_USB_HCI 225 u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size); 226 int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num); 227 u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode); 228 #endif /* CONFIG_USB_HCI */ 229 230 #ifdef CONFIG_SUPPORT_TRX_SHARED 231 void dump_trx_share_mode(void *sel, _adapter *adapter); 232 #endif 233 234 #ifdef CONFIG_BEAMFORMING 235 #ifdef RTW_BEAMFORMING_VERSION_2 236 int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, 237 u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr); 238 int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d); 239 240 int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role, 241 enum halmac_data_rate rate); 242 int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role); 243 244 int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate, 245 u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54); 246 247 int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role, 248 u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en, 249 u32 *given_gid_tab, u32 *given_user_pos); 250 #define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \ 251 rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos) 252 253 #endif /* RTW_BEAMFORMING_VERSION_2 */ 254 #endif /* CONFIG_BEAMFORMING */ 255 256 #endif /* _HAL_HALMAC_H_ */ 257