1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_MP_C_
16
17 #include <drv_types.h>
18
19 #ifdef CONFIG_MP_INCLUDED
20
21 #ifdef RTW_HALMAC
22 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
23 #else /* !RTW_HALMAC */
24 #ifdef CONFIG_RTL8188E
25 #include <rtl8188e_hal.h>
26 #endif
27 #ifdef CONFIG_RTL8723B
28 #include <rtl8723b_hal.h>
29 #endif
30 #ifdef CONFIG_RTL8192E
31 #include <rtl8192e_hal.h>
32 #endif
33 #ifdef CONFIG_RTL8814A
34 #include <rtl8814a_hal.h>
35 #endif
36 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
37 #include <rtl8812a_hal.h>
38 #endif
39 #ifdef CONFIG_RTL8703B
40 #include <rtl8703b_hal.h>
41 #endif
42 #ifdef CONFIG_RTL8723D
43 #include <rtl8723d_hal.h>
44 #endif
45 #ifdef CONFIG_RTL8710B
46 #include <rtl8710b_hal.h>
47 #endif
48 #ifdef CONFIG_RTL8188F
49 #include <rtl8188f_hal.h>
50 #endif
51 #ifdef CONFIG_RTL8188GTV
52 #include <rtl8188gtv_hal.h>
53 #endif
54 #ifdef CONFIG_RTL8192F
55 #include <rtl8192f_hal.h>
56 #endif
57 #endif /* !RTW_HALMAC */
58
59
MgntQuery_NssTxRate(u16 Rate)60 u8 MgntQuery_NssTxRate(u16 Rate)
61 {
62 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
63
64 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
65 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
66 NssNum = RF_2TX;
67 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
68 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
69 NssNum = RF_3TX;
70 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
71 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
72 NssNum = RF_4TX;
73 else
74 NssNum = RF_1TX;
75
76 return NssNum;
77 }
78
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)79 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
80 {
81 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
82 u8 ChannelToSw = pMptCtx->MptChannelToSw;
83 u32 ulRateIdx = pMptCtx->mpt_rate_index;
84 u32 ulbandwidth = pMptCtx->MptBandWidth;
85
86 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
87 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
88 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
89 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
90 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
91
92 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
93 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
94 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
95 } else {
96 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
97 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
98 }
99 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
100 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
101 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
102 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
103 } else {
104 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
105 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
106 }
107 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
108 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
109 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
110 }
111 }
112
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)113 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
114 {
115 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
116 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
117
118
119 if (!netif_running(padapter->pnetdev)) {
120 return _FAIL;
121 }
122
123 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
124 return _FAIL;
125 }
126 if (enable)
127 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
128 else
129 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
130
131 return _SUCCESS;
132 }
133
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)134 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
137 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
138
139
140 *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
141 }
142
143
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)144 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
145 {
146 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
147 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
148 u8 i;
149 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
150 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
151 u8 u1Channel = pHalData->current_channel;
152 u32 ulRateIdx = pMptCtx->mpt_rate_index;
153 u8 DataRate = 0xFF;
154
155 /* Do not modify CCK TX filter parameters for 8822B*/
156 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
157 IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
158 return;
159
160 DataRate = mpt_to_mgnt_rate(ulRateIdx);
161
162 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
163 pHalData->bCCKinCH14 = TRUE;
164 else
165 pHalData->bCCKinCH14 = FALSE;
166
167 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
168 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
169 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
170 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
171 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
172
173 } else {
174 /* Normal setting for 8703B, just recover to the default setting. */
175 /* This hardcore values reference from the parameter which BB team gave. */
176 for (i = 0 ; i < 2 ; ++i)
177 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
178
179 }
180 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
181 /* 2.4G CCK TX DFIR */
182 /* 2016.01.20 Suggest from RS BB mingzhi*/
183 if (u1Channel == 14) {
184 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
185 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
186 phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
187 } else {
188 for (i = 0 ; i < 3 ; ++i) {
189 phy_set_bb_reg(Adapter,
190 pHalData->RegForRecover[i].offset,
191 bMaskDWord,
192 pHalData->RegForRecover[i].value);
193 }
194 }
195 } else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
196 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
197 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
198 CCKSwingIndex = 20; /* default index */
199
200 if (!pHalData->bCCKinCH14) {
201 /* Readback the current bb cck swing value and compare with the table to */
202 /* get the current swing index */
203 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
204 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
205 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
206 CCKSwingIndex = i;
207 break;
208 }
209 }
210 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
211 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
212 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
213 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
214 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
215 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
216 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
217 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
218 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
219 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
220 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
221 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
222 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
223 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
224 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
225 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
226 RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
227 } else {
228 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
229 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
230 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
231 CCKSwingIndex = i;
232 break;
233 }
234 }
235 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
236 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
237 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
238 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
239 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
240 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
241 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
242 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
243 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
244 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
245 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
246 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
247 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
248 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
249 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
250 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
251 RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
252 }
253 } else {
254
255 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
256 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
257
258 if (!pHalData->bCCKinCH14) {
259 /* Readback the current bb cck swing value and compare with the table to */
260 /* get the current swing index */
261 for (i = 0; i < CCK_TABLE_SIZE; i++) {
262 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
263 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
264 CCKSwingIndex = i;
265 break;
266 }
267 }
268
269 /*Write 0xa22 0xa23*/
270 TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
271 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
272
273
274 /*Write 0xa24 ~ 0xa27*/
275 TempVal2 = 0;
276 TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
277 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
278 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
279 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
280
281 /*Write 0xa28 0xa29*/
282 TempVal3 = 0;
283 TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
284 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
285 } else {
286 for (i = 0; i < CCK_TABLE_SIZE; i++) {
287 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
288 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
289 CCKSwingIndex = i;
290 break;
291 }
292 }
293
294 /*Write 0xa22 0xa23*/
295 TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
296 (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
297
298 /*Write 0xa24 ~ 0xa27*/
299 TempVal2 = 0;
300 TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
301 (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
302 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
303 (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
304
305 /*Write 0xa28 0xa29*/
306 TempVal3 = 0;
307 TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
308 (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
309 }
310
311 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
312 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
313 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
314 }
315
316 }
317
hal_mpt_SetChannel(PADAPTER pAdapter)318 void hal_mpt_SetChannel(PADAPTER pAdapter)
319 {
320 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
321 struct mp_priv *pmp = &pAdapter->mppriv;
322 u8 channel = pmp->channel;
323 u8 bandwidth = pmp->bandwidth;
324
325 hal_mpt_SwitchRfSetting(pAdapter);
326
327 pHalData->bSwChnl = _TRUE;
328 pHalData->bSetChnlBW = _TRUE;
329
330 if (bandwidth == 2) {
331 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
332 } else if (bandwidth == 1) {
333 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
334 } else
335 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
336
337 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
338 rtw_btcoex_wifionly_scan_notify(pAdapter);
339
340 }
341
342 /*
343 * Notice
344 * Switch bandwitdth may change center frequency(channel)
345 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)346 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
347 {
348 struct mp_priv *pmp = &pAdapter->mppriv;
349 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
350
351 u8 channel = pmp->channel;
352 u8 bandwidth = pmp->bandwidth;
353
354 pHalData->bSwChnl = _TRUE;
355 pHalData->bSetChnlBW = _TRUE;
356
357 if (bandwidth == 2) {
358 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
359 } else if (bandwidth == 1) {
360 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
361 } else
362 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
363
364 hal_mpt_SwitchRfSetting(pAdapter);
365 rtw_btcoex_wifionly_scan_notify(pAdapter);
366
367 }
368
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)369 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
370 {
371 switch (Rate) {
372 case MPT_CCK: {
373 u32 TxAGC = 0, pwr = 0;
374
375 pwr = pTxPower[RF_PATH_A];
376 if (pwr < 0x3f) {
377 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
378 phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
379 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
380 }
381 pwr = pTxPower[RF_PATH_B];
382 if (pwr < 0x3f) {
383 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
384 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
385 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
386 }
387 }
388 break;
389
390 case MPT_OFDM_AND_HT: {
391 u32 TxAGC = 0;
392 u8 pwr = 0;
393
394 pwr = pTxPower[0];
395 if (pwr < 0x3f) {
396 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
397 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
398 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
399 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
400 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
401 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
402 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
403 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
404 }
405 TxAGC = 0;
406 pwr = pTxPower[1];
407 if (pwr < 0x3f) {
408 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
409 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
410 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
411 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
412 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
413 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
414 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
415 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
416 }
417 }
418 break;
419
420 default:
421 break;
422 }
423 RTW_INFO("<===mpt_SetTxPower_Old()\n");
424 }
425
426 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)427 mpt_SetTxPower(
428 PADAPTER pAdapter,
429 MPT_TXPWR_DEF Rate,
430 u8 *pTxPower
431 )
432 {
433 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
434
435 u8 path = 0 , i = 0, MaxRate = MGN_6M;
436 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
437 u8 tx_nss = 2;
438
439 if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter)) {
440 EndPath = RF_PATH_D;
441 tx_nss = 4;
442 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
443 || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8723F(pAdapter)) {
444 EndPath = RF_PATH_A;
445 tx_nss = 1;
446 }
447
448 switch (Rate) {
449 case MPT_CCK: {
450 u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
451
452 for (path = StartPath; path <= EndPath; path++)
453 for (i = 0; i < sizeof(rate); ++i)
454 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
455 }
456 break;
457 case MPT_OFDM: {
458 u8 rate[] = {
459 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
460 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
461 };
462
463 for (path = StartPath; path <= EndPath; path++)
464 for (i = 0; i < sizeof(rate); ++i)
465 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
466 }
467 break;
468 case MPT_HT: {
469 u8 rate[] = {
470 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
471 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
472 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
473 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
474 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
475 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
476 MGN_MCS30, MGN_MCS31,
477 };
478 if (tx_nss == 4)
479 MaxRate = MGN_MCS31;
480 else if (tx_nss == 3)
481 MaxRate = MGN_MCS23;
482 else if (tx_nss == 2)
483 MaxRate = MGN_MCS15;
484 else
485 MaxRate = MGN_MCS7;
486
487 for (path = StartPath; path <= EndPath; path++) {
488 for (i = 0; i < sizeof(rate); ++i) {
489 if (rate[i] > MaxRate)
490 break;
491 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
492 }
493 }
494 }
495 break;
496 case MPT_VHT: {
497 u8 rate[] = {
498 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
499 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
500 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
501 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
502 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
503 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
504 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
505 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
506 };
507 if (tx_nss == 4)
508 MaxRate = MGN_VHT4SS_MCS9;
509 else if (tx_nss == 3)
510 MaxRate = MGN_VHT3SS_MCS9;
511 else if (tx_nss == 2)
512 MaxRate = MGN_VHT2SS_MCS9;
513 else
514 MaxRate = MGN_VHT1SS_MCS9;
515
516 for (path = StartPath; path <= EndPath; path++) {
517 for (i = 0; i < sizeof(rate); ++i) {
518 if (rate[i] > MaxRate)
519 break;
520 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
521 }
522 }
523 }
524 break;
525 default:
526 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
527 break;
528 }
529 }
530
hal_mpt_SetTxPower(PADAPTER pAdapter)531 void hal_mpt_SetTxPower(PADAPTER pAdapter)
532 {
533 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
534 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
535 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
536
537 if (pHalData->rf_chip < RF_CHIP_MAX) {
538 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
539 IS_HARDWARE_TYPE_8723B(pAdapter) ||
540 IS_HARDWARE_TYPE_8192E(pAdapter) ||
541 IS_HARDWARE_TYPE_8703B(pAdapter) ||
542 IS_HARDWARE_TYPE_8188F(pAdapter) ||
543 IS_HARDWARE_TYPE_8188GTV(pAdapter)
544 ) {
545
546 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
547
548 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
549 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
550
551 } else {
552
553 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
554 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
555 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
556 if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
557 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
558 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
559 }
560 }
561
562 rtw_hal_set_txpwr_done(pAdapter);
563 } else
564 RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
565
566 odm_clear_txpowertracking_state(pDM_Odm);
567 }
568
hal_mpt_SetDataRate(PADAPTER pAdapter)569 void hal_mpt_SetDataRate(PADAPTER pAdapter)
570 {
571 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
572 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
573 u32 DataRate;
574
575 DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
576
577 hal_mpt_SwitchRfSetting(pAdapter);
578
579 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
580 #ifdef CONFIG_RTL8723B
581 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
582 if (IS_CCK_RATE(DataRate)) {
583 if (pMptCtx->mpt_rf_path == RF_PATH_A)
584 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
585 else
586 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
587 } else {
588 if (pMptCtx->mpt_rf_path == RF_PATH_A)
589 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
590 else
591 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
592 }
593 }
594
595 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
596 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
597 if (pMptCtx->mpt_rf_path == RF_PATH_A)
598 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
599 else
600 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
601 }
602 #endif
603 }
604
hal_mpt_tssi_turn_target_power(PADAPTER padapter,s16 power_offset,u8 path)605 u32 hal_mpt_tssi_turn_target_power(PADAPTER padapter, s16 power_offset, u8 path)
606 {
607 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
608 struct dm_struct *pdm = &pHalData->odmpriv;
609 u32 pout = 0;
610
611 #ifdef CONFIG_RTL8723F
612 pout = halrf_tssi_turn_target_power(pdm, power_offset, path);
613 #endif
614 RTW_INFO("%s()===> pout %d\n", __func__, pout);
615
616 return pout;
617 }
618
619 #define RF_PATH_AB 22
620
621 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)622 void mpt_ToggleIG_8814A(PADAPTER pAdapter)
623 {
624 u8 Path;
625 u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
626
627 for (Path = 0; Path <= RF_PATH_D; Path++) {
628 switch (Path) {
629 case RF_PATH_B:
630 IGReg = rB_IGI_Jaguar;
631 break;
632 case RF_PATH_C:
633 IGReg = rC_IGI_Jaguar2;
634 break;
635 case RF_PATH_D:
636 IGReg = rD_IGI_Jaguar2;
637 break;
638 default:
639 IGReg = rA_IGI_Jaguar;
640 break;
641 }
642
643 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
644 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
645 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
646 }
647 }
648
mpt_SetRFPath_8814A(PADAPTER pAdapter)649 void mpt_SetRFPath_8814A(PADAPTER pAdapter)
650 {
651
652 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
653 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
654 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
655 R_ANTENNA_SELECT_CCK *p_cck_txrx;
656 u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
657 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
658 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
659
660 u32 ulAntennaTx = pHalData->antenna_tx_path;
661 u32 ulAntennaRx = pHalData->AntennaRxPath;
662 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
663
664 if (NssforRate == RF_3TX) {
665 RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
666
667 switch (ulAntennaTx) {
668 case ANTENNA_BCD:
669 pMptCtx->mpt_rf_path = RF_PATH_BCD;
670 /*pHalData->ValidTxPath = 0x0e;*/
671 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
672 break;
673
674 case ANTENNA_ABC:
675 default:
676 pMptCtx->mpt_rf_path = RF_PATH_ABC;
677 /*pHalData->ValidTxPath = 0x0d;*/
678 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
679 break;
680 }
681
682 } else { /*/if(NssforRate == RF_1TX)*/
683 RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
684 switch (ulAntennaTx) {
685 case ANTENNA_BCD:
686 pMptCtx->mpt_rf_path = RF_PATH_BCD;
687 /*pHalData->ValidTxPath = 0x0e;*/
688 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
689 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
690 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
691 break;
692
693 case ANTENNA_BC:
694 pMptCtx->mpt_rf_path = RF_PATH_BC;
695 /*pHalData->ValidTxPath = 0x06;*/
696 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
697 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
698 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
699 break;
700 case ANTENNA_B:
701 pMptCtx->mpt_rf_path = RF_PATH_B;
702 /*pHalData->ValidTxPath = 0x02;*/
703 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
704 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
705 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
706 break;
707
708 case ANTENNA_C:
709 pMptCtx->mpt_rf_path = RF_PATH_C;
710 /*pHalData->ValidTxPath = 0x04;*/
711 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
712 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
713 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
714 break;
715
716 case ANTENNA_D:
717 pMptCtx->mpt_rf_path = RF_PATH_D;
718 /*pHalData->ValidTxPath = 0x08;*/
719 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
720 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
721 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
722 break;
723
724 case ANTENNA_A:
725 default:
726 pMptCtx->mpt_rf_path = RF_PATH_A;
727 /*pHalData->ValidTxPath = 0x01;*/
728 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
729 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
730 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
731 break;
732 }
733 }
734
735 switch (ulAntennaRx) {
736 case ANTENNA_A:
737 /*pHalData->ValidRxPath = 0x01;*/
738 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
739 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
740 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
741 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
742 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
743 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
744 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
745 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
746 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
747 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
748 /*/ CCA related PD_delay_th*/
749 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
750 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
751 break;
752
753 case ANTENNA_B:
754 /*pHalData->ValidRxPath = 0x02;*/
755 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
756 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
757 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
758 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
759 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
760 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
761 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
762 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
763 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
764 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
765 /*/ CCA related PD_delay_th*/
766 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
767 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
768 break;
769
770 case ANTENNA_C:
771 /*pHalData->ValidRxPath = 0x04;*/
772 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
773 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
774 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
775 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
776 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
777 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
778 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
779 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
780 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
781 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
782 /*/ CCA related PD_delay_th*/
783 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
784 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
785 break;
786
787 case ANTENNA_D:
788 /*pHalData->ValidRxPath = 0x08;*/
789 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
790 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
791 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
792 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
793 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
794 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
795 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
796 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
797 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
798 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
799 /*/ CCA related PD_delay_th*/
800 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
801 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
802 break;
803
804 case ANTENNA_BC:
805 /*pHalData->ValidRxPath = 0x06;*/
806 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
807 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
808 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
809 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
810 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
811 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
812 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
813 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
814 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
815 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
816 /*/ CCA related PD_delay_th*/
817 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
818 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
819 break;
820
821 case ANTENNA_CD:
822 /*pHalData->ValidRxPath = 0x0C;*/
823 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
824 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
825 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
826 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
827 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
828 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
829 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
830 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
831 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
832 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
833 /*/ CCA related PD_delay_th*/
834 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
835 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
836 break;
837
838 case ANTENNA_BCD:
839 /*pHalData->ValidRxPath = 0x0e;*/
840 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
841 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
842 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
843 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
844 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
845 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
846 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
847 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
848 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
849 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
850 /*/ CCA related PD_delay_th*/
851 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
852 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
853 break;
854
855 case ANTENNA_ABCD:
856 /*pHalData->ValidRxPath = 0x0f;*/
857 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
858 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
859 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
860 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
861 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
862 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
863 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
864 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
865 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
866 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
867 /*/ CCA related PD_delay_th*/
868 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
869 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
870 break;
871
872 default:
873 break;
874 }
875
876 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
877
878 mpt_ToggleIG_8814A(pAdapter);
879 }
880
881 #endif /* CONFIG_RTL8814A */
882 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) \
883 || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8723F)
884 void
mpt_SetSingleTone_8814A(PADAPTER pAdapter,BOOLEAN bSingleTone,BOOLEAN bEnPMacTx)885 mpt_SetSingleTone_8814A(
886 PADAPTER pAdapter,
887 BOOLEAN bSingleTone,
888 BOOLEAN bEnPMacTx)
889 {
890
891 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
892 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_A, path;
893 static u32 regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
894
895 if (bSingleTone) {
896 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
897 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
898 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
899 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
900
901 switch (pMptCtx->mpt_rf_path) {
902 case RF_PATH_A:
903 case RF_PATH_B:
904 case RF_PATH_C:
905 case RF_PATH_D:
906 StartPath = pMptCtx->mpt_rf_path;
907 EndPath = pMptCtx->mpt_rf_path;
908 break;
909 case RF_PATH_AB:
910 EndPath = RF_PATH_B;
911 break;
912 case RF_PATH_BC:
913 StartPath = RF_PATH_B;
914 EndPath = RF_PATH_C;
915 break;
916 case RF_PATH_ABC:
917 EndPath = RF_PATH_C;
918 break;
919 case RF_PATH_BCD:
920 StartPath = RF_PATH_B;
921 EndPath = RF_PATH_D;
922 break;
923 case RF_PATH_ABCD:
924 EndPath = RF_PATH_D;
925 break;
926 }
927
928 if (bEnPMacTx == FALSE) {
929 hal_mpt_SetContinuousTx(pAdapter, _TRUE);
930 issue_nulldata(pAdapter, NULL, 1, 3, 500);
931 }
932
933 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
934
935 for (path = StartPath; path <= EndPath; path++) {
936 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
937 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
938
939 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
940 }
941
942 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
943 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
944 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
945 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
946 } else {
947 switch (pMptCtx->mpt_rf_path) {
948 case RF_PATH_A:
949 case RF_PATH_B:
950 case RF_PATH_C:
951 case RF_PATH_D:
952 StartPath = pMptCtx->mpt_rf_path;
953 EndPath = pMptCtx->mpt_rf_path;
954 break;
955 case RF_PATH_AB:
956 EndPath = RF_PATH_B;
957 break;
958 case RF_PATH_BC:
959 StartPath = RF_PATH_B;
960 EndPath = RF_PATH_C;
961 break;
962 case RF_PATH_ABC:
963 EndPath = RF_PATH_C;
964 break;
965 case RF_PATH_BCD:
966 StartPath = RF_PATH_B;
967 EndPath = RF_PATH_D;
968 break;
969 case RF_PATH_ABCD:
970 EndPath = RF_PATH_D;
971 break;
972 }
973 for (path = StartPath; path <= EndPath; path++)
974 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
975
976 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
977
978 if (bEnPMacTx == FALSE) {
979 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
980 #ifdef PHYDM_MP_SUPPORT
981 phydm_stop_ofdm_cont_tx(pAdapter);
982 pMptCtx->bCckContTx = FALSE;
983 pMptCtx->bOfdmContTx = FALSE;
984 #endif
985 } else
986 hal_mpt_SetContinuousTx(pAdapter, _FALSE);
987 }
988
989 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
990 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
991 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
992 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
993 }
994 }
995
996 #endif
997
998 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)999 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
1000 {
1001 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1002 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
1003 struct mp_priv *pmp = &pAdapter->mppriv;
1004 u8 channel = pmp->channel;
1005 u8 bandwidth = pmp->bandwidth;
1006 u8 eLNA_2g = pHalData->ExternalLNA_2G;
1007 u32 ulAntennaTx, ulAntennaRx;
1008 u32 reg0xC50 = 0;
1009
1010 ulAntennaTx = pHalData->antenna_tx_path;
1011 ulAntennaRx = pHalData->AntennaRxPath;
1012
1013 switch (ulAntennaTx) {
1014 case ANTENNA_A:
1015 pMptCtx->mpt_rf_path = RF_PATH_A;
1016 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
1017 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1018 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1019 break;
1020 case ANTENNA_B:
1021 pMptCtx->mpt_rf_path = RF_PATH_B;
1022 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
1023 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1024 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
1025 break;
1026 case ANTENNA_AB:
1027 pMptCtx->mpt_rf_path = RF_PATH_AB;
1028 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
1029 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1030 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1031 break;
1032 default:
1033 pMptCtx->mpt_rf_path = RF_PATH_AB;
1034 RTW_INFO("Unknown Tx antenna.\n");
1035 break;
1036 }
1037
1038 switch (ulAntennaRx) {
1039 case ANTENNA_A:
1040 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
1041 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
1042 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1043 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1044
1045 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1046 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1047 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1048 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1049
1050 /* set PWED_TH for BB Yn user guide R29 */
1051 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1052 if (channel <= 14) { /* 2.4G */
1053 if (bandwidth == CHANNEL_WIDTH_20
1054 && eLNA_2g == 0) {
1055 /* 0x830[3:1]=3'b010 */
1056 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1057 } else
1058 /* 0x830[3:1]=3'b100 */
1059 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1060 } else
1061 /* 0x830[3:1]=3'b100 for 5G */
1062 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1063 }
1064 break;
1065 case ANTENNA_B:
1066 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1067 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1068 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1069 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1070
1071 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1072 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1073 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1074 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1075
1076 /* set PWED_TH for BB Yn user guide R29 */
1077 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1078 if (channel <= 14) {
1079 if (bandwidth == CHANNEL_WIDTH_20
1080 && eLNA_2g == 0) {
1081 /* 0x830[3:1]=3'b010 */
1082 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1083 } else
1084 /* 0x830[3:1]=3'b100 */
1085 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1086 } else
1087 /* 0x830[3:1]=3'b100 for 5G */
1088 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1089 }
1090 break;
1091 case ANTENNA_AB:
1092 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1093 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1094 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1095 /* set PWED_TH for BB Yn user guide R29 */
1096 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1097 break;
1098 default:
1099 RTW_INFO("Unknown Rx antenna.\n");
1100 break;
1101 }
1102
1103 if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1104 if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1105 /* WiFi */
1106 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1107 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1108 } else {
1109 /* BT */
1110 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1111 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1112 }
1113 }
1114 }
1115 #endif
1116
1117 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1118 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1119 {
1120 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1121 u32 ulAntennaTx, ulAntennaRx;
1122 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1123 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1124 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1125 u8 i;
1126
1127 ulAntennaTx = pHalData->antenna_tx_path;
1128 ulAntennaRx = pHalData->AntennaRxPath;
1129
1130 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1131 RTW_INFO("This RF chip ID is not supported\n");
1132 return;
1133 }
1134
1135 switch (pAdapter->mppriv.antenna_tx) {
1136 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1137 pMptCtx->mpt_rf_path = RF_PATH_A;
1138 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1139 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1140
1141 for (i = 0; i < 3; ++i) {
1142 u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1143 u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1144
1145 if (offset != 0) {
1146 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1147 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1148 }
1149 }
1150 for (i = 0; i < 2; ++i) {
1151 u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1152 u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1153
1154 if (offset != 0) {
1155 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1156 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1157 }
1158 }
1159 }
1160 break;
1161 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1162 u32 offset;
1163 u32 data;
1164
1165 pMptCtx->mpt_rf_path = RF_PATH_B;
1166 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1167 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1168
1169 for (i = 0; i < 3; ++i) {
1170 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1171 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1172 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1173 if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1174 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1175 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1176 }
1177 }
1178 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1179 for (i = 0; i < 2; ++i) {
1180 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1181 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1182 if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1183 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1184 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1185 }
1186 }
1187 }
1188 break;
1189 default:
1190 pMptCtx->mpt_rf_path = RF_PATH_AB;
1191 break;
1192 }
1193 }
1194 #endif
1195
1196 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1197 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1198 {
1199 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1200 u32 ulAntennaTx, ulAntennaRx;
1201 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1202 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1203 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1204 u8 i;
1205
1206 ulAntennaTx = pHalData->antenna_tx_path;
1207 ulAntennaRx = pHalData->AntennaRxPath;
1208
1209 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1210 RTW_INFO("This RF chip ID is not supported\n");
1211 return;
1212 }
1213
1214 switch (pAdapter->mppriv.antenna_tx) {
1215 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1216 pMptCtx->mpt_rf_path = RF_PATH_A;
1217 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1218 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1219
1220 for (i = 0; i < 3; ++i) {
1221 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1222 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1223
1224 if (offset != 0) {
1225 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1226 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1227 }
1228
1229 }
1230 for (i = 0; i < 2; ++i) {
1231 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1232 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1233
1234 if (offset != 0) {
1235 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1236 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1237 }
1238 }
1239 }
1240 break;
1241 case ANTENNA_B: { /* Actually path S0 (BT)*/
1242 pMptCtx->mpt_rf_path = RF_PATH_B;
1243 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1244 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1245
1246 for (i = 0; i < 3; ++i) {
1247 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1248 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1249
1250 if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1251 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1252 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1253 }
1254 }
1255 for (i = 0; i < 2; ++i) {
1256 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1257 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1258
1259 if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1260 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1261 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1262 }
1263 }
1264 }
1265 break;
1266 default:
1267 pMptCtx->mpt_rf_path = RF_PATH_AB;
1268 break;
1269 }
1270
1271 }
1272 #endif
1273
1274 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1275 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1276 {
1277 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1278 u8 p = 0, i = 0;
1279 u32 ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1280 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1281 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1282 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1283
1284 ulAntennaTx = pHalData->antenna_tx_path;
1285 ulAntennaRx = pHalData->AntennaRxPath;
1286
1287 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1288 RTW_INFO("This RF chip ID is not supported\n");
1289 return;
1290 }
1291
1292 switch (pAdapter->mppriv.antenna_tx) {
1293 /* Actually path S1 (Wi-Fi) */
1294 case ANTENNA_A: {
1295 pMptCtx->mpt_rf_path = RF_PATH_A;
1296 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1297 }
1298 break;
1299 /* Actually path S0 (BT) */
1300 case ANTENNA_B: {
1301 pMptCtx->mpt_rf_path = RF_PATH_B;
1302 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1303
1304 }
1305 break;
1306 default:
1307 pMptCtx->mpt_rf_path = RF_PATH_AB;
1308 break;
1309 }
1310 }
1311 #endif
1312
mpt_SetRFPath_819X(PADAPTER pAdapter)1313 void mpt_SetRFPath_819X(PADAPTER pAdapter)
1314 {
1315 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1316 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1317 u32 ulAntennaTx, ulAntennaRx;
1318 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1319 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1320 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1321 u8 chgTx = 0, chgRx = 0;
1322 u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1323
1324 ulAntennaTx = pHalData->antenna_tx_path;
1325 ulAntennaRx = pHalData->AntennaRxPath;
1326
1327 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1328 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1329
1330 p_ofdm_tx->r_ant_ht1 = 0x1;
1331 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1332 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1333
1334 switch (ulAntennaTx) {
1335 case ANTENNA_A:
1336 p_ofdm_tx->r_tx_antenna = 0x1;
1337 r_ofdm_tx_en_val = 0x1;
1338 p_ofdm_tx->r_ant_l = 0x1;
1339 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1340 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1341 p_cck_txrx->r_ccktx_enable = 0x8;
1342 chgTx = 1;
1343 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1344 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1345 {
1346 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1347 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1348 r_ofdm_tx_en_val = 0x3;
1349 /*/ Power save*/
1350 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1351 /*/ We need to close RFB by SW control*/
1352 if (pHalData->rf_type == RF_2T2R) {
1353 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1354 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1355 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1356 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1357 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1358 }
1359 }
1360 pMptCtx->mpt_rf_path = RF_PATH_A;
1361 break;
1362 case ANTENNA_B:
1363 p_ofdm_tx->r_tx_antenna = 0x2;
1364 r_ofdm_tx_en_val = 0x2;
1365 p_ofdm_tx->r_ant_l = 0x2;
1366 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1367 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1368 p_cck_txrx->r_ccktx_enable = 0x4;
1369 chgTx = 1;
1370 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1371 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1372 {
1373 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1374 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1375
1376 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1377 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1378 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1379 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1380 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1381 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1382 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1383 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1384 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1385 }
1386 }
1387 pMptCtx->mpt_rf_path = RF_PATH_B;
1388 break;
1389 case ANTENNA_AB:/*/ For 8192S*/
1390 p_ofdm_tx->r_tx_antenna = 0x3;
1391 r_ofdm_tx_en_val = 0x3;
1392 p_ofdm_tx->r_ant_l = 0x3;
1393 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1394 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1395 p_cck_txrx->r_ccktx_enable = 0xC;
1396 chgTx = 1;
1397 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1398 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1399 {
1400 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1401 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1402 /* Disable Power save*/
1403 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1404 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1405 if (pHalData->rf_type == RF_2T2R) {
1406 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1407
1408 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1409 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1410 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1411 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1412 }
1413 }
1414 pMptCtx->mpt_rf_path = RF_PATH_AB;
1415 break;
1416 default:
1417 break;
1418 }
1419 #if 0
1420 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1421 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1422 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1423 #endif
1424 switch (ulAntennaRx) {
1425 case ANTENNA_A:
1426 r_rx_antenna_ofdm = 0x1; /* A*/
1427 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1428 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1429 chgRx = 1;
1430 break;
1431 case ANTENNA_B:
1432 r_rx_antenna_ofdm = 0x2; /*/ B*/
1433 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1434 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1435 chgRx = 1;
1436 break;
1437 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1438 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1439 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1440 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1441 chgRx = 1;
1442 break;
1443 default:
1444 break;
1445 }
1446
1447
1448 if (chgTx && chgRx) {
1449 switch (pHalData->rf_chip) {
1450 case RF_8225:
1451 case RF_8256:
1452 case RF_6052:
1453 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1454 phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1455 phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1456 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1457 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1458 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1459 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1460 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1461 }
1462 phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1463 break;
1464
1465 default:
1466 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1467 break;
1468 }
1469 }
1470 } /* MPT_ProSetRFPath */
1471
1472 #ifdef CONFIG_RTL8192F
1473
mpt_set_rfpath_8192f(PADAPTER pAdapter)1474 void mpt_set_rfpath_8192f(PADAPTER pAdapter)
1475 {
1476 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1477 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1478
1479 u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
1480 u8 NssforRate, odmNssforRate;
1481 u32 ulAntennaTx, ulAntennaRx;
1482 enum bb_path RxAntToPhyDm;
1483 enum bb_path TxAntToPhyDm;
1484
1485 ulAntennaTx = pHalData->antenna_tx_path;
1486 ulAntennaRx = pHalData->AntennaRxPath;
1487 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
1488
1489 if (pHalData->rf_chip >= RF_TYPE_MAX)
1490 RTW_INFO("This RF chip ID is not supported\n");
1491
1492 switch (ulAntennaTx) {
1493 case ANTENNA_A:
1494 pMptCtx->mpt_rf_path = RF_PATH_A;
1495 TxAntToPhyDm = BB_PATH_A;
1496 break;
1497 case ANTENNA_B:
1498 pMptCtx->mpt_rf_path = RF_PATH_B;
1499 TxAntToPhyDm = BB_PATH_B;
1500 break;
1501 case ANTENNA_AB:
1502 pMptCtx->mpt_rf_path = RF_PATH_AB;
1503 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1504 break;
1505 default:
1506 pMptCtx->mpt_rf_path = RF_PATH_AB;
1507 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1508 break;
1509 }
1510
1511 switch (ulAntennaRx) {
1512 case ANTENNA_A:
1513 RxAntToPhyDm = BB_PATH_A;
1514 break;
1515 case ANTENNA_B:
1516 RxAntToPhyDm = BB_PATH_B;
1517 break;
1518 case ANTENNA_AB:
1519 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1520 break;
1521 default:
1522 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1523 break;
1524 }
1525
1526 phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
1527
1528 }
1529
1530 #endif
1531
hal_mpt_SetAntenna(PADAPTER pAdapter)1532 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1533 {
1534 PHAL_DATA_TYPE hal;
1535 ANTENNA_PATH anttx;
1536 enum bb_path bb_tx = 0;
1537
1538
1539 hal = GET_HAL_DATA(pAdapter);
1540 anttx = hal->antenna_tx_path;
1541
1542 switch (anttx) {
1543 case ANTENNA_A:
1544 bb_tx = BB_PATH_A;
1545 break;
1546 case ANTENNA_B:
1547 bb_tx = BB_PATH_B;
1548 break;
1549 case ANTENNA_C:
1550 bb_tx = BB_PATH_C;
1551 break;
1552 case ANTENNA_D:
1553 bb_tx = BB_PATH_D;
1554 break;
1555 case ANTENNA_AB:
1556 bb_tx = BB_PATH_AB;
1557 break;
1558 case ANTENNA_AC:
1559 bb_tx = BB_PATH_AC;
1560 break;
1561 case ANTENNA_AD:
1562 bb_tx = BB_PATH_AD;
1563 break;
1564 case ANTENNA_BC:
1565 bb_tx = BB_PATH_BC;
1566 break;
1567 case ANTENNA_BD:
1568 bb_tx = BB_PATH_BD;
1569 break;
1570 case ANTENNA_CD:
1571 bb_tx = BB_PATH_CD;
1572 break;
1573 case ANTENNA_ABC:
1574 bb_tx = BB_PATH_ABC;
1575 break;
1576 case ANTENNA_BCD:
1577 bb_tx = BB_PATH_BCD;
1578 break;
1579 case ANTENNA_ABD:
1580 bb_tx = BB_PATH_ABD;
1581 break;
1582 case ANTENNA_ACD:
1583 bb_tx = BB_PATH_ACD;
1584 break;
1585 case ANTENNA_ABCD:
1586 bb_tx = BB_PATH_ABCD;
1587 break;
1588 default:
1589 bb_tx = BB_PATH_A;
1590 break;
1591 }
1592 tx_path_nss_set_full_tx(hal->txpath_nss, hal->txpath_num_nss, bb_tx);
1593 RTW_INFO("%s ,ant idx %d, tx path_num_nss = %d\n", __func__, anttx, hal->txpath_num_nss[0]);
1594
1595 #ifdef CONFIG_RTL8822C
1596 if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
1597 rtl8822c_mp_config_rfpath(pAdapter);
1598 return;
1599 }
1600 #endif
1601 #ifdef CONFIG_RTL8814A
1602 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1603 mpt_SetRFPath_8814A(pAdapter);
1604 return;
1605 }
1606 #endif
1607 #ifdef CONFIG_RTL8822B
1608 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1609 rtl8822b_mp_config_rfpath(pAdapter);
1610 return;
1611 }
1612 #endif
1613 #ifdef CONFIG_RTL8821C
1614 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1615 rtl8821c_mp_config_rfpath(pAdapter);
1616 return;
1617 }
1618 #endif
1619 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1620 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1621 mpt_SetRFPath_8812A(pAdapter);
1622 return;
1623 }
1624 #endif
1625 #ifdef CONFIG_RTL8723B
1626 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1627 mpt_SetRFPath_8723B(pAdapter);
1628 return;
1629 }
1630 #endif
1631
1632 #ifdef CONFIG_RTL8703B
1633 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1634 mpt_SetRFPath_8703B(pAdapter);
1635 return;
1636 }
1637 #endif
1638
1639 #ifdef CONFIG_RTL8723D
1640 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1641 mpt_SetRFPath_8723D(pAdapter);
1642 return;
1643 }
1644 #endif
1645
1646 #ifdef CONFIG_RTL8192F
1647 if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
1648 mpt_set_rfpath_8192f(pAdapter);
1649 return;
1650 }
1651 #endif
1652
1653 #ifdef CONFIG_RTL8814B
1654 if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
1655 rtl8814b_mp_config_rfpath(pAdapter);
1656 return;
1657 }
1658 #endif
1659
1660 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1661 mpt_SetRFPath_8821B(pAdapter);
1662 Prepare for 8822B
1663 else if (IS_HARDWARE_TYPE_8822B(Context))
1664 mpt_SetRFPath_8822B(Context);
1665 */
1666 mpt_SetRFPath_819X(pAdapter);
1667 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1668 }
1669
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1670 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1671 {
1672 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1673
1674 if (!netif_running(pAdapter->pnetdev)) {
1675 return _FAIL;
1676 }
1677
1678
1679 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1680 return _FAIL;
1681 }
1682
1683 target_ther &= 0xff;
1684
1685 pHalData->eeprom_thermal_meter = target_ther;
1686
1687 return _SUCCESS;
1688 }
1689
1690
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1691 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1692 {
1693 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
1694 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1695 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
1696 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1697 } else
1698 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1699
1700 }
1701
1702
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter,u8 rf_path)1703 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
1704
1705 {
1706 struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
1707
1708 u32 ThermalValue = 0;
1709 s32 thermal_value_temp = 0;
1710 s8 thermal_offset = 0;
1711 u32 thermal_reg_mask = 0;
1712
1713 if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id) || IS_8723F_SERIES(GET_HAL_DATA(pAdapter)->version_id))
1714 thermal_reg_mask = 0x007e; /*0x42: RF Reg[6:1], 35332(themal K & bias k & power trim) & 35325(tssi )*/
1715 else
1716 thermal_reg_mask = 0xfc00; /*0x42: RF Reg[15:10]*/
1717
1718 ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
1719
1720 thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1721
1722 thermal_value_temp = ThermalValue + thermal_offset;
1723
1724 if (thermal_value_temp > 63)
1725 ThermalValue = 63;
1726 else if (thermal_value_temp < 0)
1727 ThermalValue = 0;
1728 else
1729 ThermalValue = thermal_value_temp;
1730
1731 return (u8)ThermalValue;
1732 }
1733
1734
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1735 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
1736 {
1737 #if 0
1738 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1739 rtw_msleep_os(1000);
1740 fw_cmd_data(pAdapter, value, 1);
1741 *value &= 0xFF;
1742 #else
1743 hal_mpt_TriggerRFThermalMeter(pAdapter);
1744 rtw_msleep_os(1000);
1745 *value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
1746 #endif
1747
1748 }
1749
1750
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1751 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1752 {
1753 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1754
1755 pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1756
1757 if (bStart) {/*/ Start Single Carrier.*/
1758 /*/ Start Single Carrier.*/
1759 /*/ 1. if OFDM block on?*/
1760 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1761 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1762
1763 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1764 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1765
1766 /*/ 3. turn on scramble setting*/
1767 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1768
1769 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1770 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)\
1771 || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8723F)
1772 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
1773 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1774 else
1775 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1776 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1777
1778 } else {
1779 /*/ Stop Single Carrier.*/
1780 /*/ Stop Single Carrier.*/
1781 /*/ Turn off all test modes.*/
1782 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)\
1783 || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8723F)
1784 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)|| IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
1785 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1786 else
1787 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1788 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1789
1790 rtw_msleep_os(10);
1791 /*/BB Reset*/
1792 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1793 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1794 }
1795 }
1796
1797
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1798 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1799 {
1800 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1801 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1802 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1803 u32 ulAntennaTx = pHalData->antenna_tx_path;
1804 static u32 regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1805 u8 rfPath;
1806
1807 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
1808 #ifdef PHYDM_MP_SUPPORT
1809 #ifdef CONFIG_RTL8814B
1810 if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
1811 {
1812 /* @Tx mode: RF0x00[19:16]=4'b0010 */
1813 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
1814 /* @Lowest RF gain index: RF_0x0[4:0] = 0*/
1815 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
1816 /* @RF LO enabled */
1817 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
1818 /* @SYN1 */
1819 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
1820 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
1821 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
1822 }
1823 #endif
1824 phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
1825 #endif
1826 return;
1827 }
1828
1829 switch (ulAntennaTx) {
1830 case ANTENNA_B:
1831 rfPath = RF_PATH_B;
1832 break;
1833 case ANTENNA_C:
1834 rfPath = RF_PATH_C;
1835 break;
1836 case ANTENNA_D:
1837 rfPath = RF_PATH_D;
1838 break;
1839 case ANTENNA_A:
1840 default:
1841 rfPath = RF_PATH_A;
1842 break;
1843 }
1844
1845 pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1846 if (bStart) {
1847 /*/ Start Single Tone.*/
1848 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1849 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1850 regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1851 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1852 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1853 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1854 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1855 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1856 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1857 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1858 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1859 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1860 #ifdef CONFIG_RTL8192F
1861 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
1862 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
1863 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
1864 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
1865 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
1866 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
1867 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1868 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
1869 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
1870 #endif
1871 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1872 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1873 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1874 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1875 } else {
1876 /*/ S0/S1 both use PATH A to configure*/
1877 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1878 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1879 }
1880 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1881 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1882 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1883 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1884 }
1885 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1886 /*Set BB REG 88C: Prevent SingleTone Fail*/
1887 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1888 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1889 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1890
1891 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1892 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1893 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1894 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1895 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1896 } else {/* S0/S1 both use PATH A to configure */
1897 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1898 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1899 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1900 }
1901 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1902 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1903 u8 p = RF_PATH_A;
1904
1905 regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1906 regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1907 regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1908 regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1909 regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1910
1911 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1912
1913 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1914 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1915 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1916 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1917 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1918 }
1919 } else {
1920 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1921 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1922 #ifdef CONFIG_RTL8821C
1923 if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
1924 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
1925 else
1926 #endif
1927 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1928 }
1929 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1930 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/
1931 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/
1932 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/
1933 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/
1934 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
1935 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
1936 } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1937 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
1938
1939 if (pHalData->external_pa_5g)
1940 {
1941 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1942 }
1943 else if (pHalData->ExternalPA_2G)
1944 {
1945 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1946 }
1947 } else {
1948 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1949 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1950
1951 if (pHalData->external_pa_5g) {
1952 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1953 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1954 } else if (pHalData->ExternalPA_2G) {
1955 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1956 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1957 }
1958 }
1959 #endif
1960 }
1961 #if defined(CONFIG_RTL8814A)
1962 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1963 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1964 #endif
1965 else /*/ Turn On SingleTone and turn off the other test modes.*/
1966 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1967
1968 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1969 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1970
1971 } else {/*/ Stop Single Ton e.*/
1972
1973 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1974 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1975 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1976 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1977 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1978 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1979 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1980 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1981 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1982 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
1983 #ifdef CONFIG_RTL8192F
1984 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
1985 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
1986 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
1987 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
1988 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
1989 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
1990 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1991 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
1992 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
1993 #endif
1994 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1995 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1996 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1997 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1998 } else {
1999 /*/ S0/S1 both use PATH A to configure*/
2000 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
2001 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
2002 }
2003 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
2004 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
2005 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
2006 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
2007 }
2008 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2009 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
2010 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
2011 /*Set BB REG 88C: Prevent SingleTone Fail*/
2012 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
2013 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
2014 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
2015 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
2016 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
2017 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
2018 } else { /* S0/S1 both use PATH A to configure */
2019 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
2020 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
2021 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
2022 }
2023 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
2024 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2025 u8 p = RF_PATH_A;
2026
2027 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
2028
2029 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
2030 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
2031 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2032 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2033 }
2034 } else {
2035 p = pMptCtx->mpt_rf_path;
2036 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2037
2038 if (IS_HARDWARE_TYPE_8821C(pAdapter))
2039 phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
2040
2041 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2042 }
2043
2044 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
2045 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
2046 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
2047 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
2048
2049 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
2050 RTW_INFO("Restore RFE control Pin cbc\n");
2051 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
2052 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
2053 }
2054 #endif
2055 }
2056 #if defined(CONFIG_RTL8814A)
2057 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
2058 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
2059
2060 else/*/ Turn off all test modes.*/
2061 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2062 #endif
2063 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2064 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2065
2066 }
2067 }
2068
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)2069 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
2070 {
2071 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2072 struct dm_struct *pdm_odm = &pHalData->odmpriv;
2073 u8 Rate;
2074
2075 pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
2076
2077 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2078 #ifdef PHYDM_MP_SUPPORT
2079 phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
2080 #endif
2081 return;
2082 }
2083
2084 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2085 if (bStart) {/* Start Carrier Suppression.*/
2086 if (Rate <= MPT_RATE_11M) {
2087 /*/ 1. if CCK block on?*/
2088 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2089 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
2090
2091 /*/Turn Off All Test Mode*/
2092 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
2093 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
2094 else
2095 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2096
2097 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
2098 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
2099
2100 /*/Set CCK Tx Test Rate*/
2101 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
2102 }
2103
2104 /*Set for dynamic set Power index*/
2105 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2106 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2107
2108 } else {/* Stop Carrier Suppression.*/
2109
2110 if (Rate <= MPT_RATE_11M) {
2111 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2112 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2113
2114 /*BB Reset*/
2115 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2116 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2117 }
2118 /*Stop for dynamic set Power index*/
2119 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2120 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2121 }
2122 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
2123 }
2124
hal_mpt_query_phytxok(PADAPTER pAdapter)2125 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
2126 {
2127 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2128 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2129 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2130 u16 count = 0;
2131
2132 #ifdef PHYDM_MP_SUPPORT
2133 struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
2134 struct phydm_mp *mp = &dm->dm_mp_table;
2135
2136 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2137 phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
2138 count = mp->tx_phy_ok_cnt;
2139
2140 } else
2141 #endif
2142 {
2143
2144 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2145 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
2146 else
2147 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
2148 }
2149
2150 if (count > 50000) {
2151 rtw_reset_phy_trx_ok_counters(pAdapter);
2152 pAdapter->mppriv.tx.sended += count;
2153 count = 0;
2154 }
2155
2156 return pAdapter->mppriv.tx.sended + count;
2157
2158 }
2159
mpt_StopCckContTx(PADAPTER pAdapter)2160 static void mpt_StopCckContTx(
2161 PADAPTER pAdapter
2162 )
2163 {
2164 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2165 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2166 u8 u1bReg;
2167
2168 pMptCtx->bCckContTx = FALSE;
2169 pMptCtx->bOfdmContTx = FALSE;
2170
2171 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2172 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2173
2174 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2175 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
2176 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2177
2178 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2179 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
2180 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
2181 }
2182
2183 /*BB Reset*/
2184 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2185 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2186
2187 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)
2188 && !IS_HARDWARE_TYPE_8723D(pAdapter) && !IS_HARDWARE_TYPE_8192F(pAdapter)
2189 && !IS_HARDWARE_TYPE_8188F(pAdapter)) {
2190 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2191 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2192 }
2193
2194 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2195 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2196 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2197 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2198 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
2199 }
2200
2201 } /* mpt_StopCckContTx */
2202
2203
mpt_StopOfdmContTx(PADAPTER pAdapter)2204 static void mpt_StopOfdmContTx(
2205 PADAPTER pAdapter
2206 )
2207 {
2208 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2209 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2210 u8 u1bReg;
2211 u32 data;
2212
2213 pMptCtx->bCckContTx = FALSE;
2214 pMptCtx->bOfdmContTx = FALSE;
2215
2216 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
2217 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2218 else
2219 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2220
2221 rtw_mdelay_os(10);
2222
2223 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)){
2224 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
2225 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2226 }
2227
2228 /*BB Reset*/
2229 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2230 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2231
2232 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)
2233 && !IS_HARDWARE_TYPE_8723D(pAdapter) && !IS_HARDWARE_TYPE_8192F(pAdapter)
2234 && !IS_HARDWARE_TYPE_8188F(pAdapter)) {
2235 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2236 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2237 }
2238 } /* mpt_StopOfdmContTx */
2239
2240
mpt_StartCckContTx(PADAPTER pAdapter)2241 static void mpt_StartCckContTx(
2242 PADAPTER pAdapter
2243 )
2244 {
2245 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2246 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2247 u32 cckrate;
2248
2249 /* 1. if CCK block on */
2250 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2251 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2252
2253 /*Turn Off All Test Mode*/
2254 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
2255 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2256 else
2257 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2258
2259 cckrate = pAdapter->mppriv.rateidx;
2260
2261 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2262
2263 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
2264 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2265
2266 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2267 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2268 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2269 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2270 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
2271 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
2272 }
2273
2274 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)
2275 && !IS_HARDWARE_TYPE_8723D(pAdapter) && !IS_HARDWARE_TYPE_8192F(pAdapter)
2276 && !IS_HARDWARE_TYPE_8188F(pAdapter)) {
2277 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2278 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2279 }
2280
2281 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2282 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2283 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2284 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2285 if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
2286 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
2287 else
2288 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
2289 }
2290
2291 pMptCtx->bCckContTx = TRUE;
2292 pMptCtx->bOfdmContTx = FALSE;
2293
2294 } /* mpt_StartCckContTx */
2295
2296
mpt_StartOfdmContTx(PADAPTER pAdapter)2297 static void mpt_StartOfdmContTx(
2298 PADAPTER pAdapter
2299 )
2300 {
2301 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2302 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2303
2304 /* 1. if OFDM block on?*/
2305 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2306 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2307
2308 /* 2. set CCK test mode off, set to CCK normal mode*/
2309 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2310
2311 /* 3. turn on scramble setting*/
2312 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
2313
2314 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)) {
2315 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
2316 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
2317 }
2318
2319 /* 4. Turn On Continue Tx and turn off the other test modes.*/
2320 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter))
2321 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2322 else
2323 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2324
2325 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR3_11N(pAdapter)
2326 && !IS_HARDWARE_TYPE_8723D(pAdapter) && !IS_HARDWARE_TYPE_8192F(pAdapter)
2327 && !IS_HARDWARE_TYPE_8188F(pAdapter)) {
2328 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2329 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2330 }
2331
2332 pMptCtx->bCckContTx = FALSE;
2333 pMptCtx->bOfdmContTx = TRUE;
2334 } /* mpt_StartOfdmContTx */
2335
2336 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) \
2337 || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
2338 || defined(CONFIG_RTL8723F)
2339 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
mpt_convert_phydm_txinfo_for_jaguar3(RT_PMAC_TX_INFO * pMacTxInfo,struct phydm_pmac_info * phydmtxinfo)2340 static void mpt_convert_phydm_txinfo_for_jaguar3(
2341 RT_PMAC_TX_INFO *pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
2342 {
2343 phydmtxinfo->en_pmac_tx = pMacTxInfo->bEnPMacTx;
2344 phydmtxinfo->mode = pMacTxInfo->Mode;
2345 phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo->TX_RATE));
2346 phydmtxinfo->tx_sc = pMacTxInfo->TX_SC;
2347 phydmtxinfo->is_short_preamble = pMacTxInfo->bSPreamble;
2348 phydmtxinfo->ndp_sound = pMacTxInfo->NDP_sound;
2349 phydmtxinfo->bw = pMacTxInfo->BandWidth;
2350 phydmtxinfo->m_stbc = pMacTxInfo->m_STBC;
2351 phydmtxinfo->packet_period = pMacTxInfo->PacketPeriod;
2352 phydmtxinfo->packet_count = pMacTxInfo->PacketCount;
2353 phydmtxinfo->packet_pattern = pMacTxInfo->PacketPattern;
2354 phydmtxinfo->sfd = pMacTxInfo->SFD;
2355 phydmtxinfo->signal_field = pMacTxInfo->SignalField;
2356 phydmtxinfo->service_field = pMacTxInfo->ServiceField;
2357 phydmtxinfo->length = pMacTxInfo->LENGTH;
2358 #if defined(CONFIG_RTL8723F)
2359 if (IS_MPT_CCK_RATE(pMacTxInfo->TX_RATE))
2360 phydmtxinfo->service_field_bit2= 0x1;
2361 phydmtxinfo->packet_length = pMacTxInfo->PacketLength;
2362 #endif
2363 _rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo->CRC16, 2);
2364 _rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo->LSIG,3);
2365 _rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo->HT_SIG,6);
2366 _rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo->VHT_SIG_A,6);
2367 _rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo->VHT_SIG_B,4);
2368 phydmtxinfo->vht_sig_b_crc = pMacTxInfo->VHT_SIG_B_CRC;
2369 _rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo->VHT_Delimiter,4);
2370 }
2371 #endif
2372
2373 /* for HW TX mode */
mpt_ProSetPMacTx(PADAPTER Adapter)2374 u8 mpt_ProSetPMacTx(PADAPTER Adapter)
2375 {
2376 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2377 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
2378 struct mp_priv *pmppriv = &Adapter->mppriv;
2379 struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
2380 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2381 struct dm_struct *p_dm_odm;
2382 u32 u4bTmp;
2383 u8 status = _TRUE;
2384
2385 p_dm_odm = &pHalData->odmpriv;
2386
2387 #if 0
2388 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2389 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2390 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2391 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2392 dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2393 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2394
2395 PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
2396 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
2397 #endif
2398 if (pmppriv->pktInterval != 0)
2399 PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
2400
2401 if (pmppriv->tx.count != 0)
2402 PMacTxInfo.PacketCount = pmppriv->tx.count;
2403
2404 RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2405 RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2406 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2407
2408 if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(PMacTxInfo.TX_RATE))
2409 return _FALSE;
2410 if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(PMacTxInfo.TX_RATE))
2411 return _FALSE;
2412 if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(PMacTxInfo.TX_RATE))
2413 return _FALSE;
2414 if (!is_supported_vht(Adapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(PMacTxInfo.TX_RATE))
2415 return _FALSE;
2416 if (!is_supported_ht(Adapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(PMacTxInfo.TX_RATE))
2417 return _FALSE;
2418
2419 if (PMacTxInfo.BandWidth == 1 && hal_chk_bw_cap(Adapter, BW_CAP_40M))
2420 PMacTxInfo.BandWidth = CHANNEL_WIDTH_40;
2421 else if (PMacTxInfo.BandWidth == 2 && hal_chk_bw_cap(Adapter, BW_CAP_80M))
2422 PMacTxInfo.BandWidth = CHANNEL_WIDTH_80;
2423 else
2424 PMacTxInfo.BandWidth = CHANNEL_WIDTH_20;
2425
2426 if (IS_HARDWARE_TYPE_JAGUAR3(Adapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(Adapter)) {
2427 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2428 struct phydm_pmac_info phydm_mactxinfo;
2429
2430 if (PMacTxInfo.bEnPMacTx == TRUE) {
2431 pMptCtx->HWTxmode = PMacTxInfo.Mode;
2432 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2433 if (PMacTxInfo.Mode != PACKETS_TX)
2434 hal_mpt_SetTxPower(Adapter);
2435 } else {
2436 PMacTxInfo.Mode = pMptCtx->HWTxmode;
2437 PMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;
2438 pMptCtx->HWTxmode = TEST_NONE;
2439 }
2440 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2441 phydm_mp_set_single_tone(p_dm_odm, PMacTxInfo.bEnPMacTx ,pMptCtx->mpt_rf_path);
2442 RTW_INFO("To set Tx mode OFDM_Single_Tone_TX\n");
2443 return status;
2444 }
2445
2446 if (PMacTxInfo.Mode == CCK_Carrier_Suppression_TX) {
2447 phydm_mp_set_carrier_supp(p_dm_odm, PMacTxInfo.bEnPMacTx ,PMacTxInfo.TX_RATE);
2448
2449 RTW_INFO("To set Tx mode CCK_Carrier_Suppression_TX\n");
2450 return status;
2451 }
2452
2453 mpt_convert_phydm_txinfo_for_jaguar3(&PMacTxInfo, &phydm_mactxinfo);
2454 phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
2455 #endif
2456 return status;
2457 }
2458
2459 if (PMacTxInfo.bEnPMacTx == FALSE) {
2460 if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
2461 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2462 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2463 mpt_StopCckContTx(Adapter);
2464 else
2465 mpt_StopOfdmContTx(Adapter);
2466 } else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
2467 u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2468 phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2469 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2470 } else
2471 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2472
2473 if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
2474 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2475 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2476 mpt_StopCckContTx(Adapter);
2477 else
2478 mpt_StopOfdmContTx(Adapter);
2479
2480 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2481 }
2482 pMptCtx->HWTxmode = TEST_NONE;
2483 return status;
2484 }
2485
2486 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2487
2488 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2489 pMptCtx->HWTxmode = CONTINUOUS_TX;
2490 PMacTxInfo.PacketCount = 1;
2491
2492 hal_mpt_SetTxPower(Adapter);
2493
2494 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2495 mpt_StartCckContTx(Adapter);
2496 else
2497 mpt_StartOfdmContTx(Adapter);
2498 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2499 /* Continuous TX -> HW TX -> RF Setting */
2500 pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
2501 PMacTxInfo.PacketCount = 1;
2502
2503 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2504 mpt_StartCckContTx(Adapter);
2505 else
2506 mpt_StartOfdmContTx(Adapter);
2507 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2508 pMptCtx->HWTxmode = PACKETS_TX;
2509 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2510 PMacTxInfo.PacketCount = 0xffff;
2511 }
2512
2513 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2514 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2515 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2516 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2517 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2518 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2519 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2520 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2521 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2522
2523 if (PMacTxInfo.bSPreamble)
2524 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2525 else
2526 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2527 } else {
2528 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2529
2530 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2531 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2532
2533 if (PMacTxInfo.PacketPattern == 0x12)
2534 u4bTmp = 0x3000000;
2535 else
2536 u4bTmp = 0;
2537 }
2538
2539 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2540 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2541 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2542 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2543 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2544 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2545 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2546 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2547 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2548 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2549
2550 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2551 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2552 }
2553
2554 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2555 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2556 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2557
2558 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2559 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2560
2561 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2562 /*& Duration & Frame control*/
2563 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2564
2565 /* Address1 [0:3]*/
2566 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2567 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2568
2569 /* Address3 [3:0]*/
2570 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2571
2572 /* Address2[0:1] & Address1 [5:4]*/
2573 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2574 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2575
2576 /* Address2 [5:2]*/
2577 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2578 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2579
2580 /* Sequence Control & Address3 [5:4]*/
2581 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2582 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2583 } else {
2584 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2585 /* & Duration & Frame control */
2586 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2587
2588 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2589 /* Address1 [0:3]*/
2590 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2591 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2592
2593 /* Address3 [3:0]*/
2594 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2595
2596 /* Address2[0:1] & Address1 [5:4]*/
2597 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2598 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2599
2600 /* Address2 [5:2] */
2601 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2602 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2603
2604 /* Sequence Control & Address3 [5:4]*/
2605 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2606 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2607 }
2608
2609 phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2610
2611 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2612 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2613 phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2614
2615 if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
2616 u32 offset = 0xb44;
2617
2618 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2619 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2620 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2621 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2622 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2623 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2624
2625 } else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
2626 u32 offset = 0xb4c;
2627
2628 if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2629 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2630 else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2631 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2632 else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2633 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2634 }
2635
2636 phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2637 /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2638 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2639 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2640 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2641 } else
2642 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2643
2644 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2645 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2646
2647 return status;
2648 }
2649
2650 #endif
2651
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2652 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2653 {
2654 u8 Rate;
2655
2656 RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
2657 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2658 pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2659
2660 if (Rate <= MPT_RATE_11M) {
2661 if (bStart)
2662 mpt_StartCckContTx(pAdapter);
2663 else
2664 mpt_StopCckContTx(pAdapter);
2665
2666 } else if (Rate >= MPT_RATE_6M) {
2667 if (bStart)
2668 mpt_StartOfdmContTx(pAdapter);
2669 else
2670 mpt_StopOfdmContTx(pAdapter);
2671 }
2672 }
2673
mpt_trigger_tssi_tracking(PADAPTER pAdapter,u8 rf_path)2674 void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path)
2675 {
2676 #ifdef CONFIG_RTL8814B
2677 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2678 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
2679
2680 halrf_do_tssi_8814b(pDM_Odm, rf_path);
2681 #endif
2682 }
2683
2684 #endif /* CONFIG_MP_INCLUDE*/
2685