1 /******************************************************************************
2 *
3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15
16 #ifndef _HALMAC_TYPE_H_
17 #define _HALMAC_TYPE_H_
18
19 #include "halmac_2_platform.h"
20 #include "halmac_hw_cfg.h"
21 #include "halmac_fw_info.h"
22 #include "halmac_intf_phy_cmd.h"
23 #include "halmac_state_machine.h"
24
25 #define IN
26 #define OUT
27 #define INOUT
28
29 #define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */
30
31 #ifndef HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE
32 #define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 80
33 #endif
34
35 #ifndef HALMAC_MSG_LEVEL_TRACE
36 #define HALMAC_MSG_LEVEL_TRACE 3
37 #endif
38
39 #ifndef HALMAC_MSG_LEVEL_WARNING
40 #define HALMAC_MSG_LEVEL_WARNING 2
41 #endif
42
43 #ifndef HALMAC_MSG_LEVEL_ERR
44 #define HALMAC_MSG_LEVEL_ERR 1
45 #endif
46
47 #ifndef HALMAC_MSG_LEVEL_NO_LOG
48 #define HALMAC_MSG_LEVEL_NO_LOG 0
49 #endif
50
51 #ifndef HALMAC_SDIO_SUPPORT
52 #define HALMAC_SDIO_SUPPORT 1
53 #endif
54
55 #ifndef HALMAC_USB_SUPPORT
56 #define HALMAC_USB_SUPPORT 1
57 #endif
58
59 #ifndef HALMAC_PCIE_SUPPORT
60 #define HALMAC_PCIE_SUPPORT 1
61 #endif
62
63 #ifndef HALMAC_MSG_LEVEL
64 #define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
65 #endif
66
67 #ifndef HALMAC_DBG_MONITOR_IO
68 #define HALMAC_DBG_MONITOR_IO 0
69 #endif
70
71 /* platform api */
72 #define PLTFM_SDIO_CMD52_R(offset) \
73 adapter->pltfm_api->SDIO_CMD52_READ(adapter->drv_adapter, offset)
74 #define PLTFM_SDIO_CMD53_R8(offset) \
75 adapter->pltfm_api->SDIO_CMD53_READ_8(adapter->drv_adapter, offset)
76 #define PLTFM_SDIO_CMD53_R16(offset) \
77 adapter->pltfm_api->SDIO_CMD53_READ_16(adapter->drv_adapter, offset)
78 #define PLTFM_SDIO_CMD53_R32(offset) \
79 adapter->pltfm_api->SDIO_CMD53_READ_32(adapter->drv_adapter, offset)
80 #define PLTFM_SDIO_CMD53_RN(offset, size, data) \
81 adapter->pltfm_api->SDIO_CMD53_READ_N(adapter->drv_adapter, offset, \
82 size, data)
83 #define PLTFM_SDIO_CMD52_W(offset, val) \
84 adapter->pltfm_api->SDIO_CMD52_WRITE(adapter->drv_adapter, offset, val)
85 #define PLTFM_SDIO_CMD53_W8(offset, val) \
86 adapter->pltfm_api->SDIO_CMD53_WRITE_8(adapter->drv_adapter, offset, \
87 val)
88 #define PLTFM_SDIO_CMD53_W16(offset, val) \
89 adapter->pltfm_api->SDIO_CMD53_WRITE_16(adapter->drv_adapter, offset, \
90 val)
91 #define PLTFM_SDIO_CMD53_W32(offset, val) \
92 adapter->pltfm_api->SDIO_CMD53_WRITE_32(adapter->drv_adapter, offset, \
93 val)
94 #define PLTFM_SDIO_CMD52_CIA_R(offset) \
95 adapter->pltfm_api->SDIO_CMD52_CIA_READ(adapter->drv_adapter, offset)
96
97 #define PLTFM_REG_R8(offset) \
98 adapter->pltfm_api->REG_READ_8(adapter->drv_adapter, offset)
99 #define PLTFM_REG_R16(offset) \
100 adapter->pltfm_api->REG_READ_16(adapter->drv_adapter, offset)
101 #define PLTFM_REG_R32(offset) \
102 adapter->pltfm_api->REG_READ_32(adapter->drv_adapter, offset)
103 #define PLTFM_REG_W8(offset, val) \
104 adapter->pltfm_api->REG_WRITE_8(adapter->drv_adapter, offset, val)
105 #define PLTFM_REG_W16(offset, val) \
106 adapter->pltfm_api->REG_WRITE_16(adapter->drv_adapter, offset, val)
107 #define PLTFM_REG_W32(offset, val) \
108 adapter->pltfm_api->REG_WRITE_32(adapter->drv_adapter, offset, val)
109
110 #define PLTFM_SEND_RSVD_PAGE(buf, size) \
111 adapter->pltfm_api->SEND_RSVD_PAGE(adapter->drv_adapter, buf, size)
112 #define PLTFM_SEND_H2C_PKT(buf, size) \
113 adapter->pltfm_api->SEND_H2C_PKT(adapter->drv_adapter, buf, size)
114
115 #define PLTFM_FREE(buf, size) \
116 adapter->pltfm_api->RTL_FREE(adapter->drv_adapter, buf, size)
117 #define PLTFM_MALLOC(size) \
118 adapter->pltfm_api->RTL_MALLOC(adapter->drv_adapter, size)
119 #define PLTFM_MEMCPY(dest, src, size) \
120 adapter->pltfm_api->RTL_MEMCPY(adapter->drv_adapter, dest, src, size)
121 #define PLTFM_MEMSET(addr, value, size) \
122 adapter->pltfm_api->RTL_MEMSET(adapter->drv_adapter, addr, value, size)
123 #define PLTFM_DELAY_US(us) \
124 adapter->pltfm_api->RTL_DELAY_US(adapter->drv_adapter, us)
125
126 #define PLTFM_MUTEX_INIT(mutex) \
127 adapter->pltfm_api->MUTEX_INIT(adapter->drv_adapter, mutex)
128 #define PLTFM_MUTEX_DEINIT(mutex) \
129 adapter->pltfm_api->MUTEX_DEINIT(adapter->drv_adapter, mutex)
130 #define PLTFM_MUTEX_LOCK(mutex) \
131 adapter->pltfm_api->MUTEX_LOCK(adapter->drv_adapter, mutex)
132 #define PLTFM_MUTEX_UNLOCK(mutex) \
133 adapter->pltfm_api->MUTEX_UNLOCK(adapter->drv_adapter, mutex)
134
135 #define PLTFM_EVENT_SIG(feature_id, proc_status, buf, size) \
136 adapter->pltfm_api->EVENT_INDICATION(adapter->drv_adapter, feature_id, \
137 proc_status, buf, size)
138
139 #if HALMAC_PLATFORM_WINDOWS
140 #define PLTFM_MSG_PRINT adapter->pltfm_api->MSG_PRINT
141 #endif
142
143 #define PLTFM_MSG_ALWAYS(...) \
144 adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \
145 HALMAC_DBG_ALWAYS, __VA_ARGS__)
146
147 #if HALMAC_DBG_MSG_ENABLE
148
149 /* Enable debug msg depends on HALMAC_MSG_LEVEL */
150 #if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_ERR)
151 #define PLTFM_MSG_ERR(...) \
152 adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \
153 HALMAC_DBG_ERR, __VA_ARGS__)
154 #else
155 #define PLTFM_MSG_ERR(...) do {} while (0)
156 #endif
157
158 #if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_WARNING)
159 #define PLTFM_MSG_WARN(...) \
160 adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \
161 HALMAC_DBG_WARN, __VA_ARGS__)
162 #else
163 #define PLTFM_MSG_WARN(...) do {} while (0)
164 #endif
165
166 #if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_TRACE)
167 #define PLTFM_MSG_TRACE(...) \
168 adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \
169 HALMAC_DBG_TRACE, __VA_ARGS__)
170 #else
171 #define PLTFM_MSG_TRACE(...) do {} while (0)
172 #endif
173
174 #else
175
176 /* Disable debug msg */
177 #define PLTFM_MSG_ERR(...) do {} while (0)
178 #define PLTFM_MSG_WARN(...) do {} while (0)
179 #define PLTFM_MSG_TRACE(...) do {} while (0)
180
181 #endif
182
183 #if HALMAC_DBG_MONITOR_IO
184 #define PLTFM_MONITOR_READ(offset, byte, val, __func, __line) \
185 adapter->pltfm_api->READ_MONITOR(adapter->drv_adapter, offset, byte, \
186 val, __func, __line)
187 #define PLTFM_MONITOR_WRITE(offset, byte, val, __func, __line) \
188 adapter->pltfm_api->WRITE_MONITOR(adapter->drv_adapter, offset, byte, \
189 val, __func, __line)
190
191 #define HALMAC_REG_R8(offset) \
192 api->halmac_mon_reg_read_8(adapter, offset, __func__, __LINE__)
193 #define HALMAC_REG_R16(offset) \
194 api->halmac_mon_reg_read_16(adapter, offset, __func__, __LINE__)
195 #define HALMAC_REG_R32(offset) \
196 api->halmac_mon_reg_read_32(adapter, offset, __func__, __LINE__)
197 #define HALMAC_REG_W8(offset, val) \
198 api->halmac_mon_reg_write_8(adapter, offset, val, \
199 __func__, __LINE__)
200 #define HALMAC_REG_W16(offset, val) \
201 api->halmac_mon_reg_write_16(adapter, offset, val, \
202 __func__, __LINE__)
203 #define HALMAC_REG_W32(offset, val) \
204 api->halmac_mon_reg_write_32(adapter, offset, val, \
205 __func__, __LINE__)
206 #define HALMAC_REG_SDIO_RN(offset, size, data) \
207 api->halmac_mon_reg_sdio_cmd53_read_n(adapter, offset, size, data, \
208 __func__, __LINE__)
209
210 #else
211 #define HALMAC_REG_R8(offset) api->halmac_reg_read_8(adapter, offset)
212 #define HALMAC_REG_R16(offset) api->halmac_reg_read_16(adapter, offset)
213 #define HALMAC_REG_R32(offset) api->halmac_reg_read_32(adapter, offset)
214 #define HALMAC_REG_W8(offset, val) api->halmac_reg_write_8(adapter, offset, val)
215 #define HALMAC_REG_W16(offset, val) \
216 api->halmac_reg_write_16(adapter, offset, val)
217 #define HALMAC_REG_W32(offset, val) \
218 api->halmac_reg_write_32(adapter, offset, val)
219 #define HALMAC_REG_SDIO_RN(offset, size, data) \
220 api->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, data)
221 #endif
222
223 #define HALMAC_REG_W8_CLR(offset, mask) \
224 do { \
225 u32 __offset = (u32)offset; \
226 HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) & ~(mask)); \
227 } while (0)
228 #define HALMAC_REG_W16_CLR(offset, mask) \
229 do { \
230 u32 __offset = (u32)offset; \
231 HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) & ~(mask)); \
232 } while (0)
233 #define HALMAC_REG_W32_CLR(offset, mask) \
234 do { \
235 u32 __offset = (u32)offset; \
236 HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) & ~(mask)); \
237 } while (0)
238
239 #define HALMAC_REG_W8_SET(offset, mask) \
240 do { \
241 u32 __offset = (u32)offset; \
242 HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) | mask); \
243 } while (0)
244 #define HALMAC_REG_W16_SET(offset, mask) \
245 do { \
246 u32 __offset = (u32)offset; \
247 HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) | mask); \
248 } while (0)
249 #define HALMAC_REG_W32_SET(offset, mask) \
250 do { \
251 u32 __offset = (u32)offset; \
252 HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) | mask); \
253 } while (0)
254
255 /* Swap Little-endian <-> Big-endia*/
256 #define SWAP32(x) \
257 ((u32)((((u32)(x) & (u32)0x000000ff) << 24) | \
258 (((u32)(x) & (u32)0x0000ff00) << 8) | \
259 (((u32)(x) & (u32)0x00ff0000) >> 8) | \
260 (((u32)(x) & (u32)0xff000000) >> 24)))
261
262 #define SWAP16(x) \
263 ((u16)((((u16)(x) & (u16)0x00ff) << 8) | \
264 (((u16)(x) & (u16)0xff00) >> 8)))
265
266 /*1->Little endian 0->Big endian*/
267 #if HALMAC_SYSTEM_ENDIAN
268 #ifndef rtk_le16_to_cpu
269 #define rtk_cpu_to_le32(x) ((u32)(x))
270 #define rtk_le32_to_cpu(x) ((u32)(x))
271 #define rtk_cpu_to_le16(x) ((u16)(x))
272 #define rtk_le16_to_cpu(x) ((u16)(x))
273 #define rtk_cpu_to_be32(x) SWAP32((x))
274 #define rtk_be32_to_cpu(x) SWAP32((x))
275 #define rtk_cpu_to_be16(x) SWAP16((x))
276 #define rtk_be16_to_cpu(x) SWAP16((x))
277 #endif
278 #else
279 #ifndef rtk_le16_to_cpu
280 #define rtk_cpu_to_le32(x) SWAP32((x))
281 #define rtk_le32_to_cpu(x) SWAP32((x))
282 #define rtk_cpu_to_le16(x) SWAP16((x))
283 #define rtk_le16_to_cpu(x) SWAP16((x))
284 #define rtk_cpu_to_be32(x) ((u32)(x))
285 #define rtk_be32_to_cpu(x) ((u32)(x))
286 #define rtk_cpu_to_be16(x) ((u16)(x))
287 #define rtk_be16_to_cpu(x) ((u16)(x))
288 #endif
289 #endif
290
291 #define HALMAC_ALIGN(x, a) HALMAC_ALIGN_MASK(x, (a) - 1)
292 #define HALMAC_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
293
294 /* #if !HALMAC_PLATFORM_WINDOWS */
295 #if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0))
296
297 /* Byte Swapping routine */
298 #ifndef EF1BYTE
299 #define EF1BYTE (u8)
300 #endif
301
302 #ifndef EF2BYTE
303 #define EF2BYTE rtk_le16_to_cpu
304 #endif
305
306 #ifndef EF4BYTE
307 #define EF4BYTE rtk_le32_to_cpu
308 #endif
309
310 /* Example:
311 * BIT_LEN_MASK_32(0) => 0x00000000
312 * BIT_LEN_MASK_32(1) => 0x00000001
313 * BIT_LEN_MASK_32(2) => 0x00000003
314 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
315 */
316 #ifndef BIT_LEN_MASK_32
317 #define BIT_LEN_MASK_32(__bitlen) (0xFFFFFFFF >> (32 - (__bitlen)))
318 #endif
319
320 /* Example:
321 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
322 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
323 */
324 #ifndef BIT_OFFSET_LEN_MASK_32
325 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
326 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
327 #endif
328
329 /* Return 4-byte value in host byte ordering from
330 * 4-byte pointer in litten-endian system
331 */
332 #ifndef LE_P4BYTE_TO_HOST_4BYTE
333 #define LE_P4BYTE_TO_HOST_4BYTE(__start) (EF4BYTE(*((u32 *)(__start))))
334 #endif
335
336 /* Translate subfield (continuous bits in little-endian) of
337 * 4-byte value in litten byte to 4-byte value in host byte ordering
338 */
339 #ifndef LE_BITS_TO_4BYTE
340 #define LE_BITS_TO_4BYTE(__start, __bitoffset, __bitlen) \
341 ((LE_P4BYTE_TO_HOST_4BYTE(__start) >> (__bitoffset)) & \
342 BIT_LEN_MASK_32(__bitlen))
343 #endif
344
345 /* Mask subfield (continuous bits in little-endian) of 4-byte
346 * value in litten byte oredering and return the result in 4-byte
347 * value in host byte ordering
348 */
349 #ifndef LE_BITS_CLEARED_TO_4BYTE
350 #define LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) \
351 (LE_P4BYTE_TO_HOST_4BYTE(__start) & \
352 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)))
353 #endif
354
355 /* Set subfield of little-endian 4-byte value to specified value */
356 #ifndef SET_BITS_TO_LE_4BYTE
357 #define SET_BITS_TO_LE_4BYTE(__start, __bitoffset, __bitlen, __value) \
358 do { \
359 *((u32 *)(__start)) = \
360 EF4BYTE( \
361 LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) | \
362 ((((u32)__value) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset))\
363 ); \
364 } while (0)
365 #endif
366
367 #ifndef HALMAC_BIT_OFFSET_VAL_MASK_32
368 #define HALMAC_BIT_OFFSET_VAL_MASK_32(__bitval, __bitoffset) \
369 (__bitval << (__bitoffset))
370 #endif
371
372 #ifndef SET_MEM_OP
373 #define SET_MEM_OP(dw, value32, mask, shift) \
374 (((dw) & ~((mask) << (shift))) | (((value32) & (mask)) << (shift)))
375 #endif
376
377 #ifndef HALMAC_SET_DESC_FIELD_CLR
378 #define HALMAC_SET_DESC_FIELD_CLR(dw, value32, mask, shift) \
379 (dw = (rtk_cpu_to_le32( \
380 SET_MEM_OP(rtk_cpu_to_le32(dw), value32, mask, shift))))
381 #endif
382
383 #ifndef HALMAC_SET_DESC_FIELD_NO_CLR
384 #define HALMAC_SET_DESC_FIELD_NO_CLR(dw, value32, mask, shift) \
385 (dw |= (rtk_cpu_to_le32(((value32) & (mask)) << (shift))))
386 #endif
387
388 #ifndef HALMAC_GET_DESC_FIELD
389 #define HALMAC_GET_DESC_FIELD(dw, mask, shift) \
390 ((rtk_le32_to_cpu(dw) >> (shift)) & (mask))
391 #endif
392
393 #define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR
394 #define HALMAC_SET_BD_FIELD_NO_CLR HALMAC_SET_DESC_FIELD_NO_CLR
395 #define HALMAC_GET_BD_FIELD HALMAC_GET_DESC_FIELD
396
397 #ifndef GET_H2C_FIELD
398 #define GET_H2C_FIELD LE_BITS_TO_4BYTE
399 #endif
400
401 #ifndef SET_H2C_FIELD_CLR
402 #define SET_H2C_FIELD_CLR SET_BITS_TO_LE_4BYTE
403 #endif
404
405 #ifndef SET_H2C_FIELD_NO_CLR
406 #define SET_H2C_FIELD_NO_CLR SET_BITS_TO_LE_4BYTE
407 #endif
408
409 #ifndef GET_C2H_FIELD
410 #define GET_C2H_FIELD LE_BITS_TO_4BYTE
411 #endif
412
413 #ifndef SET_C2H_FIELD_CLR
414 #define SET_C2H_FIELD_CLR SET_BITS_TO_LE_4BYTE
415 #endif
416
417 #ifndef SET_C2H_FIELD_NO_CLR
418 #define SET_C2H_FIELD_NO_CLR SET_BITS_TO_LE_4BYTE
419 #endif
420
421 #endif /* #if !HALMAC_PLATFORM_WINDOWS */
422
423 #ifndef BIT
424 #define BIT(x) (1 << (x))
425 #endif
426
427 #ifndef ARRAY_SIZE
428 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
429 #endif
430
431 /* HALMAC API return status*/
432 enum halmac_ret_status {
433 HALMAC_RET_SUCCESS = 0x00,
434 HALMAC_RET_NOT_SUPPORT = 0x01,
435 HALMAC_RET_SUCCESS_ENQUEUE = 0x01, /*Don't use this return code!!*/
436 HALMAC_RET_PLATFORM_API_NULL = 0x02,
437 HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
438 HALMAC_RET_MALLOC_FAIL = 0x04,
439 HALMAC_RET_ADAPTER_INVALID = 0x05,
440 HALMAC_RET_ITF_INCORRECT = 0x06,
441 HALMAC_RET_DLFW_FAIL = 0x07,
442 HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
443 HALMAC_RET_TXAGG_OVERFLOW = 0x09,
444 HALMAC_RET_INIT_LLT_FAIL = 0x0A,
445 HALMAC_RET_POWER_STATE_INVALID = 0x0B,
446 HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
447 HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,
448 HALMAC_RET_EFUSE_R_FAIL = 0x0E,
449 HALMAC_RET_EFUSE_W_FAIL = 0x0F,
450 HALMAC_RET_H2C_SW_RES_FAIL = 0x10,
451 HALMAC_RET_SEND_H2C_FAIL = 0x11,
452 HALMAC_RET_PARA_NOT_SUPPORT = 0x12,
453 HALMAC_RET_PLATFORM_API_INCORRECT = 0x13,
454 HALMAC_RET_ENDIAN_ERR = 0x14,
455 HALMAC_RET_FW_SIZE_ERR = 0x15,
456 HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,
457 HALMAC_RET_FAIL = 0x17,
458 HALMAC_RET_CHANGE_PS_FAIL = 0x18,
459 HALMAC_RET_CFG_PARA_FAIL = 0x19,
460 HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,
461 HALMAC_RET_SCAN_FAIL = 0x1B,
462 HALMAC_RET_STOP_SCAN_FAIL = 0x1C,
463 HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,
464 HALMAC_RET_POWER_ON_FAIL = 0x1E,
465 HALMAC_RET_POWER_OFF_FAIL = 0x1F,
466 HALMAC_RET_RX_AGG_MODE_FAIL = 0x20,
467 HALMAC_RET_DATA_BUF_NULL = 0x21,
468 HALMAC_RET_DATA_SIZE_INCORRECT = 0x22,
469 HALMAC_RET_QSEL_INCORRECT = 0x23,
470 HALMAC_RET_DMA_MAP_INCORRECT = 0x24,
471 HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,
472 HALMAC_RET_DDMA_FAIL = 0x26,
473 HALMAC_RET_FW_CHECKSUM_FAIL = 0x27,
474 HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,
475 HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,
476 HALMAC_RET_WRITE_DATA_FAIL = 0x2A,
477 HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,
478 HALMAC_RET_NULL_POINTER = 0x2C,
479 HALMAC_RET_PROBE_NOT_FOUND = 0x2D,
480 HALMAC_RET_FW_NO_MEMORY = 0x2E,
481 HALMAC_RET_H2C_STATUS_ERR = 0x2F,
482 HALMAC_RET_GET_H2C_SPACE_ERR = 0x30,
483 HALMAC_RET_H2C_SPACE_FULL = 0x31,
484 HALMAC_RET_DATAPACK_NO_FOUND = 0x32,
485 HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,
486 HALMAC_RET_TX_DMA_ERR = 0x34,
487 HALMAC_RET_RX_DMA_ERR = 0x35,
488 HALMAC_RET_CHIP_NOT_SUPPORT = 0x36,
489 HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,
490 HALMAC_RET_CH_SW_SEQ_WRONG = 0x38,
491 HALMAC_RET_CH_SW_NO_BUF = 0x39,
492 HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,
493 HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,
494 HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,
495 HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,
496 HALMAC_RET_STATE_INCORRECT = 0x3E,
497 HALMAC_RET_H2C_BUSY = 0x3F,
498 HALMAC_RET_INVALID_FEATURE_ID = 0x40,
499 HALMAC_RET_BUFFER_TOO_SMALL = 0x41,
500 HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,
501 HALMAC_RET_BUSY_STATE = 0x43,
502 HALMAC_RET_ERROR_STATE = 0x44,
503 HALMAC_RET_API_INVALID = 0x45,
504 HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,
505 HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,
506 HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
507 HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
508 HALMAC_RET_WRONG_ARGUMENT = 0x4A,
509 HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
510 HALMAC_RET_PARA_SENDING = 0x4D,
511 HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
512 HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,
513 HALMAC_RET_SWITCH_CASE_ERROR = 0x50,
514 HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,
515 HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,
516 HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
517 HALMAC_RET_NO_DLFW = 0x54,
518 HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
519 HALMAC_RET_BIP_NO_SUPPORT = 0x56,
520 HALMAC_RET_ENTRY_INDEX_ERROR = 0x57,
521 HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58,
522 HALMAC_RET_DRV_DL_ERR = 0x59,
523 HALMAC_RET_OQT_NOT_ENOUGH = 0x5A,
524 HALMAC_RET_PWR_UNCHANGE = 0x5B,
525 HALMAC_RET_WRONG_INTF = 0x5C,
526 HALMAC_RET_POLLING_HIOE_REQ_FAIL = 0x5E,
527 HALMAC_RET_HIOE_CHKSUM_FAIL = 0x5F,
528 HALMAC_RET_HIOE_ERR = 0x60,
529 HALMAC_RET_FW_NO_SUPPORT = 0x60,
530 HALMAC_RET_TXFIFO_NO_EMPTY = 0x61,
531 HALMAC_RET_SDIO_CLOCK_ERR = 0x62,
532 HALMAC_RET_GET_PINMUX_ERR = 0x63,
533 HALMAC_RET_PINMUX_USED = 0x64,
534 HALMAC_RET_WRONG_GPIO = 0x65,
535 HALMAC_RET_LTECOEX_READY_FAIL = 0x66,
536 HALMAC_RET_IDMEM_CHKSUM_FAIL = 0x67,
537 HALMAC_RET_ILLEGAL_KEY_FAIL = 0x68,
538 HALMAC_RET_FW_READY_CHK_FAIL = 0x69,
539 HALMAC_RET_RSVD_PG_OVERFLOW_FAIL = 0x70,
540 HALMAC_RET_THRESHOLD_FAIL = 0x71,
541 HALMAC_RET_SDIO_MIX_MODE = 0x72,
542 HALMAC_RET_TXDESC_SET_FAIL = 0x73,
543 HALMAC_RET_WLHDR_FAIL = 0x74,
544 HALMAC_RET_WLAN_MODE_FAIL = 0x75,
545 HALMAC_RET_SDIO_SEQ_FAIL = 0x72,
546 HALMAC_RET_INIT_XTAL_AAC_FAIL = 0x76,
547 HALMAC_RET_PINMUX_NOT_SUPPORT = 0x77,
548 HALMAC_RET_FWFF_NO_EMPTY = 0x78,
549 HALMAC_RET_ADR_NOT_ALIGN = 0x79,
550 };
551
552 enum halmac_chip_id {
553 HALMAC_CHIP_ID_8822B = 0,
554 HALMAC_CHIP_ID_8821C = 1,
555 HALMAC_CHIP_ID_8814B = 2,
556 HALMAC_CHIP_ID_8197F = 3,
557 HALMAC_CHIP_ID_8822C = 4,
558 HALMAC_CHIP_ID_8812F = 5,
559 HALMAC_CHIP_ID_UNDEFINE = 0x7F,
560 };
561
562 enum halmac_chip_ver {
563 HALMAC_CHIP_VER_A_CUT = 0x00,
564 HALMAC_CHIP_VER_B_CUT = 0x01,
565 HALMAC_CHIP_VER_C_CUT = 0x02,
566 HALMAC_CHIP_VER_D_CUT = 0x03,
567 HALMAC_CHIP_VER_E_CUT = 0x04,
568 HALMAC_CHIP_VER_F_CUT = 0x05,
569 HALMAC_CHIP_VER_G_CUT = 0x06,
570 HALMAC_CHIP_VER_H_CUT = 0x07,
571 HALMAC_CHIP_VER_I_CUT = 0x08,
572 HALMAC_CHIP_VER_J_CUT = 0x09,
573 HALMAC_CHIP_VER_K_CUT = 0x0A,
574 HALMAC_CHIP_VER_L_CUT = 0x0B,
575 HALMAC_CHIP_VER_M_CUT = 0x0C,
576 HALMAC_CHIP_VER_TEST = 0xFF,
577 HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
578 };
579
580 enum halmac_network_type_select {
581 HALMAC_NETWORK_NO_LINK = 0,
582 HALMAC_NETWORK_ADHOC = 1,
583 HALMAC_NETWORK_INFRASTRUCTURE = 2,
584 HALMAC_NETWORK_AP = 3,
585 HALMAC_NETWORK_UNDEFINE = 0x7F,
586 };
587
588 enum halmac_transfer_mode_select {
589 HALMAC_TRNSFER_NORMAL = 0x0,
590 HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
591 HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
592 HALMAC_TRNSFER_UNDEFINE = 0x7F,
593 };
594
595 enum halmac_dma_mapping {
596 HALMAC_DMA_MAPPING_EXTRA = 0,
597 HALMAC_DMA_MAPPING_LOW = 1,
598 HALMAC_DMA_MAPPING_NORMAL = 2,
599 HALMAC_DMA_MAPPING_HIGH = 3,
600 HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
601 };
602
603 enum halmac_io_size {
604 HALMAC_IO_BYTE = 0x0,
605 HALMAC_IO_WORD = 0x1,
606 HALMAC_IO_DWORD = 0x2,
607 HALMAC_IO_UNDEFINE = 0x7F,
608 };
609
610 #define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH
611 #define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL
612 #define HALMAC_MAP2_LQ HALMAC_DMA_MAPPING_LOW
613 #define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA
614 #define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE
615
616 enum halmac_txdesc_queue_tid {
617 HALMAC_TXDESC_QSEL_TID0 = 0,
618 HALMAC_TXDESC_QSEL_TID1 = 1,
619 HALMAC_TXDESC_QSEL_TID2 = 2,
620 HALMAC_TXDESC_QSEL_TID3 = 3,
621 HALMAC_TXDESC_QSEL_TID4 = 4,
622 HALMAC_TXDESC_QSEL_TID5 = 5,
623 HALMAC_TXDESC_QSEL_TID6 = 6,
624 HALMAC_TXDESC_QSEL_TID7 = 7,
625 HALMAC_TXDESC_QSEL_TID8 = 8,
626 HALMAC_TXDESC_QSEL_TID9 = 9,
627 HALMAC_TXDESC_QSEL_TIDA = 10,
628 HALMAC_TXDESC_QSEL_TIDB = 11,
629 HALMAC_TXDESC_QSEL_TIDC = 12,
630 HALMAC_TXDESC_QSEL_TIDD = 13,
631 HALMAC_TXDESC_QSEL_TIDE = 14,
632 HALMAC_TXDESC_QSEL_TIDF = 15,
633
634 HALMAC_TXDESC_QSEL_BEACON = 0x10,
635 HALMAC_TXDESC_QSEL_HIGH = 0x11,
636 HALMAC_TXDESC_QSEL_MGT = 0x12,
637 HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
638 HALMAC_TXDESC_QSEL_FWCMD = 0x14,
639
640 HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
641 };
642
643 enum halmac_pq_map_id {
644 HALMAC_PQ_MAP_VO = 0x0,
645 HALMAC_PQ_MAP_VI = 0x1,
646 HALMAC_PQ_MAP_BE = 0x2,
647 HALMAC_PQ_MAP_BK = 0x3,
648 HALMAC_PQ_MAP_MG = 0x4,
649 HALMAC_PQ_MAP_HI = 0x5,
650 HALMAC_PQ_MAP_NUM = 0x6,
651 HALMAC_PQ_MAP_UNDEF = 0x7F,
652 };
653
654 enum halmac_qsel {
655 HALMAC_QSEL_VO = HALMAC_TXDESC_QSEL_TID6,
656 HALMAC_QSEL_VI = HALMAC_TXDESC_QSEL_TID4,
657 HALMAC_QSEL_BE = HALMAC_TXDESC_QSEL_TID0,
658 HALMAC_QSEL_BK = HALMAC_TXDESC_QSEL_TID1,
659 HALMAC_QSEL_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
660 HALMAC_QSEL_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
661 HALMAC_QSEL_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
662 HALMAC_QSEL_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
663 HALMAC_QSEL_TID8 = HALMAC_TXDESC_QSEL_TID8,
664 HALMAC_QSEL_TID9 = HALMAC_TXDESC_QSEL_TID9,
665 HALMAC_QSEL_TIDA = HALMAC_TXDESC_QSEL_TIDA,
666 HALMAC_QSEL_TIDB = HALMAC_TXDESC_QSEL_TIDB,
667 HALMAC_QSEL_TIDC = HALMAC_TXDESC_QSEL_TIDC,
668 HALMAC_QSEL_TIDD = HALMAC_TXDESC_QSEL_TIDD,
669 HALMAC_QSEL_TIDE = HALMAC_TXDESC_QSEL_TIDE,
670 HALMAC_QSEL_TIDF = HALMAC_TXDESC_QSEL_TIDF,
671 HALMAC_QSEL_BCN = HALMAC_TXDESC_QSEL_BEACON,
672 HALMAC_QSEL_HIGH = HALMAC_TXDESC_QSEL_HIGH,
673 HALMAC_QSEL_MGNT = HALMAC_TXDESC_QSEL_MGT,
674 HALMAC_QSEL_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
675 HALMAC_QSEL_FWCMD = HALMAC_TXDESC_QSEL_FWCMD,
676 HALMAC_QSEL_UNDEFINE = 0x7F,
677 };
678
679 enum halmac_acq_id {
680 HALMAC_ACQ_ID_VO = 0,
681 HALMAC_ACQ_ID_VI = 1,
682 HALMAC_ACQ_ID_BE = 2,
683 HALMAC_ACQ_ID_BK = 3,
684 HALMAC_ACQ_ID_MAX = 0x7F,
685 };
686
687 enum halmac_txdesc_dma_ch {
688 HALMAC_TXDESC_DMA_CH0 = 0,
689 HALMAC_TXDESC_DMA_CH1 = 1,
690 HALMAC_TXDESC_DMA_CH2 = 2,
691 HALMAC_TXDESC_DMA_CH3 = 3,
692 HALMAC_TXDESC_DMA_CH4 = 4,
693 HALMAC_TXDESC_DMA_CH5 = 5,
694 HALMAC_TXDESC_DMA_CH6 = 6,
695 HALMAC_TXDESC_DMA_CH7 = 7,
696 HALMAC_TXDESC_DMA_CH8 = 8,
697 HALMAC_TXDESC_DMA_CH9 = 9,
698 HALMAC_TXDESC_DMA_CH10 = 10,
699 HALMAC_TXDESC_DMA_CH11 = 11,
700 HALMAC_TXDESC_DMA_CH12 = 12,
701 HALMAC_TXDESC_DMA_CH13 = 13,
702 HALMAC_TXDESC_DMA_CH14 = 14,
703 HALMAC_TXDESC_DMA_CH15 = 15,
704 HALMAC_TXDESC_DMA_CH16 = 16,
705 HALMAC_TXDESC_DMA_CH17 = 17,
706 HALMAC_TXDESC_DMA_CH18 = 18,
707 HALMAC_TXDESC_DMA_CH19 = 19,
708 HALMAC_TXDESC_DMA_CH20 = 20,
709 HALMAC_TXDESC_DMA_CHMAX,
710 HALMAC_TXDESC_DMA_CHUNDEFINE = 0x7F,
711 };
712
713 enum halmac_dma_ch {
714 HALMAC_DMA_CH_0 = HALMAC_TXDESC_DMA_CH0,
715 HALMAC_DMA_CH_1 = HALMAC_TXDESC_DMA_CH1,
716 HALMAC_DMA_CH_2 = HALMAC_TXDESC_DMA_CH2,
717 HALMAC_DMA_CH_3 = HALMAC_TXDESC_DMA_CH3,
718 HALMAC_DMA_CH_4 = HALMAC_TXDESC_DMA_CH4,
719 HALMAC_DMA_CH_5 = HALMAC_TXDESC_DMA_CH5,
720 HALMAC_DMA_CH_6 = HALMAC_TXDESC_DMA_CH6,
721 HALMAC_DMA_CH_7 = HALMAC_TXDESC_DMA_CH7,
722 HALMAC_DMA_CH_8 = HALMAC_TXDESC_DMA_CH8,
723 HALMAC_DMA_CH_9 = HALMAC_TXDESC_DMA_CH9,
724 HALMAC_DMA_CH_10 = HALMAC_TXDESC_DMA_CH10,
725 HALMAC_DMA_CH_11 = HALMAC_TXDESC_DMA_CH11,
726 HALMAC_DMA_CH_S0 = HALMAC_TXDESC_DMA_CH12,
727 HALMAC_DMA_CH_S1 = HALMAC_TXDESC_DMA_CH13,
728 HALMAC_DMA_CH_MGQ = HALMAC_TXDESC_DMA_CH14,
729 HALMAC_DMA_CH_HIGH = HALMAC_TXDESC_DMA_CH15,
730 HALMAC_DMA_CH_FWCMD = HALMAC_TXDESC_DMA_CH16,
731 HALMAC_DMA_CH_MGQ_BAND1 = HALMAC_TXDESC_DMA_CH17,
732 HALMAC_DMA_CH_HIGH_BAND1 = HALMAC_TXDESC_DMA_CH18,
733 HALMAC_DMA_CH_BCN = HALMAC_TXDESC_DMA_CH19,
734 HALMAC_DMA_CH_H2C = HALMAC_TXDESC_DMA_CH20,
735 HALMAC_DMA_CH_MAX = HALMAC_TXDESC_DMA_CHMAX,
736 HALMAC_DMA_CH_UNDEFINE = 0x7F,
737 };
738
739 enum halmac_interface {
740 HALMAC_INTERFACE_PCIE = 0x0,
741 HALMAC_INTERFACE_USB = 0x1,
742 HALMAC_INTERFACE_SDIO = 0x2,
743 HALMAC_INTERFACE_AXI = 0x3,
744 HALMAC_INTERFACE_UNDEFINE = 0x7F,
745 };
746
747 enum halmac_rx_agg_mode {
748 HALMAC_RX_AGG_MODE_NONE = 0x0,
749 HALMAC_RX_AGG_MODE_DMA = 0x1,
750 HALMAC_RX_AGG_MODE_USB = 0x2,
751 HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
752 };
753
754 struct halmac_rxagg_th {
755 u8 drv_define;
756 u8 timeout;
757 u8 size;
758 u8 size_limit_en;
759 };
760
761 struct halmac_rxagg_cfg {
762 enum halmac_rx_agg_mode mode;
763 struct halmac_rxagg_th threshold;
764 };
765
766 struct halmac_api_registry {
767 u8 rx_exp_en:1;
768 u8 la_mode_en:1;
769 u8 cfg_drv_rsvd_pg_en:1;
770 u8 sdio_cmd53_4byte_en:1;
771 u8 rsvd:4;
772 };
773
774 enum halmac_watcher_sel {
775 HALMAC_WATCHER_SDIO_RN_FOOL_PROOFING = 0x0,
776 HALMAC_WATCHER_UNDEFINE = 0x7F,
777 };
778
779 enum halmac_trx_mode {
780 HALMAC_TRX_MODE_NORMAL = 0x0,
781 HALMAC_TRX_MODE_TRXSHARE = 0x1,
782 HALMAC_TRX_MODE_WMM = 0x2,
783 HALMAC_TRX_MODE_P2P = 0x3,
784 HALMAC_TRX_MODE_LOOPBACK = 0x4,
785 HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
786 HALMAC_TRX_MODE_MAX = 0x6,
787 HALMAC_TRX_MODE_WMM_LINUX = 0x7E,
788 HALMAC_TRX_MODE_UNDEFINE = 0x7F,
789 };
790
791 enum halmac_wireless_mode {
792 HALMAC_WIRELESS_MODE_B = 0x0,
793 HALMAC_WIRELESS_MODE_G = 0x1,
794 HALMAC_WIRELESS_MODE_N = 0x2,
795 HALMAC_WIRELESS_MODE_AC = 0x3,
796 HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
797 };
798
799 enum halmac_bw {
800 HALMAC_BW_20 = 0x00,
801 HALMAC_BW_40 = 0x01,
802 HALMAC_BW_80 = 0x02,
803 HALMAC_BW_160 = 0x03,
804 HALMAC_BW_5 = 0x04,
805 HALMAC_BW_10 = 0x05,
806 HALMAC_BW_MAX = 0x06,
807 HALMAC_BW_UNDEFINE = 0x7F,
808 };
809
810 enum halmac_efuse_read_cfg {
811 HALMAC_EFUSE_R_AUTO = 0x00,
812 HALMAC_EFUSE_R_DRV = 0x01,
813 HALMAC_EFUSE_R_FW = 0x02,
814 HALMAC_EFUSE_R_UNDEFINE = 0x7F,
815 };
816
817 enum halmac_dlfw_mem {
818 HALMAC_DLFW_MEM_EMEM = 0x00,
819 HALMAC_DLFW_MEM_EMEM_RSVD_PG = 0x01,
820 HALMAC_DLFW_MEM_UNDEFINE = 0x7F,
821 };
822
823 struct halmac_tx_desc {
824 u32 dword0;
825 u32 dword1;
826 u32 dword2;
827 u32 dword3;
828 u32 dword4;
829 u32 dword5;
830 u32 dword6;
831 u32 dword7;
832 u32 dword8;
833 u32 dword9;
834 u32 dword10;
835 u32 dword11;
836 };
837
838 struct halmac_rx_desc {
839 u32 dword0;
840 u32 dword1;
841 u32 dword2;
842 u32 dword3;
843 u32 dword4;
844 u32 dword5;
845 };
846
847 struct halmac_bcn_ie_info {
848 u8 func_en;
849 u8 size_th;
850 u8 timeout;
851 u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
852 };
853
854 enum halmac_parameter_cmd {
855 /* HALMAC_PARAMETER_CMD_LLT = 0x1, */
856 /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */
857 /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */
858 HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
859 HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
860 HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
861 HALMAC_PARAMETER_CMD_RF_W = 0x7,
862 HALMAC_PARAMETER_CMD_BB_W8 = 0x8,
863 HALMAC_PARAMETER_CMD_BB_W16 = 0x9,
864 HALMAC_PARAMETER_CMD_BB_W32 = 0XA,
865 HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
866 HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
867 HALMAC_PARAMETER_CMD_END = 0XFF,
868 };
869
870 union halmac_parameter_content {
871 struct _MAC_REG_W {
872 u32 value;
873 u32 msk;
874 u16 offset;
875 u8 msk_en;
876 } MAC_REG_W;
877 struct _BB_REG_W {
878 u32 value;
879 u32 msk;
880 u16 offset;
881 u8 msk_en;
882 } BB_REG_W;
883 struct _RF_REG_W {
884 u32 value;
885 u32 msk;
886 u8 offset;
887 u8 msk_en;
888 u8 rf_path;
889 } RF_REG_W;
890 struct _DELAY_TIME {
891 u32 rsvd1;
892 u32 rsvd2;
893 u16 delay_time;
894 u8 rsvd3;
895 } DELAY_TIME;
896 };
897
898 struct halmac_phy_parameter_info {
899 enum halmac_parameter_cmd cmd_id;
900 union halmac_parameter_content content;
901 };
902
903 struct halmac_pg_efuse_info {
904 u8 *efuse_map;
905 u32 efuse_map_size;
906 u8 *efuse_mask;
907 u32 efuse_mask_size;
908 };
909
910 struct halmac_cfg_param_info {
911 u32 buf_size;
912 u8 *buf;
913 u8 *buf_wptr;
914 u32 num;
915 u32 avl_buf_size;
916 u32 offset_accum;
917 u32 value_accum;
918 enum halmac_data_type data_type;
919 u8 full_fifo_mode;
920 };
921
922 struct halmac_hw_cfg_info {
923 u32 efuse_size;
924 u32 eeprom_size;
925 u32 bt_efuse_size;
926 u32 tx_fifo_size;
927 u32 rx_fifo_size;
928 u32 rx_desc_fifo_size;
929 u32 page_size;
930 u16 tx_align_size;
931 u8 txdesc_size;
932 u8 rxdesc_size;
933 u8 cam_entry_num;
934 u8 chk_security_keyid;
935 u8 txdesc_ie_max_num;
936 u8 txdesc_body_size;
937 u8 ac_oqt_size;
938 u8 non_ac_oqt_size;
939 u8 acq_num;
940 u8 trx_mode;
941 u8 usb_txagg_num;
942 u32 prtct_efuse_size;
943 };
944
945 struct halmac_sdio_free_space {
946 u16 hiq_pg_num;
947 u16 miq_pg_num;
948 u16 lowq_pg_num;
949 u16 pubq_pg_num;
950 u16 exq_pg_num;
951 u8 ac_oqt_num;
952 u8 non_ac_oqt_num;
953 u8 ac_empty;
954 u8 *macid_map;
955 u32 macid_map_size;
956 };
957
958 enum hal_fifo_sel {
959 HAL_FIFO_SEL_TX,
960 HAL_FIFO_SEL_RX,
961 HAL_FIFO_SEL_RSVD_PAGE,
962 HAL_FIFO_SEL_REPORT,
963 HAL_FIFO_SEL_LLT,
964 HAL_FIFO_SEL_RXBUF_FW,
965 HAL_FIFO_SEL_RXBUF_PHY,
966 HAL_FIFO_SEL_RXDESC,
967 HAL_BUF_SECURITY_CAM,
968 HAL_BUF_WOW_CAM,
969 HAL_BUF_RX_FILTER_CAM,
970 HAL_BUF_BA_CAM,
971 HAL_BUF_MBSSID_CAM
972 };
973
974 enum halmac_drv_info {
975 /* No information is appended in rx_pkt */
976 HALMAC_DRV_INFO_NONE,
977 /* PHY status is appended after rx_desc */
978 HALMAC_DRV_INFO_PHY_STATUS,
979 /* PHY status and sniffer info are appended after rx_desc */
980 HALMAC_DRV_INFO_PHY_SNIFFER,
981 /* PHY status and plcp header are appended after rx_desc */
982 HALMAC_DRV_INFO_PHY_PLCP,
983 HALMAC_DRV_INFO_UNDEFINE,
984 };
985
986 enum halmac_pri_ch_idx {
987 HALMAC_CH_IDX_UNDEFINE = 0,
988 HALMAC_CH_IDX_1 = 1,
989 HALMAC_CH_IDX_2 = 2,
990 HALMAC_CH_IDX_3 = 3,
991 HALMAC_CH_IDX_4 = 4,
992 HALMAC_CH_IDX_MAX = 5,
993 };
994
995 struct halmac_ch_info {
996 enum halmac_cs_action_id action_id;
997 enum halmac_bw bw;
998 enum halmac_pri_ch_idx pri_ch_idx;
999 u8 channel;
1000 u8 timeout;
1001 u8 extra_info;
1002 };
1003
1004 struct halmac_ch_extra_info {
1005 u8 extra_info;
1006 enum halmac_cs_extra_action_id extra_action_id;
1007 u8 extra_info_size;
1008 u8 *extra_info_data;
1009 };
1010
1011 enum halmac_cs_periodic_option {
1012 HALMAC_CS_PERIODIC_NONE,
1013 HALMAC_CS_PERIODIC_NORMAL,
1014 HALMAC_CS_PERIODIC_2_PHASE,
1015 HALMAC_CS_PERIODIC_SEAMLESS,
1016 };
1017
1018 struct halmac_ch_switch_option {
1019 enum halmac_bw dest_bw;
1020 enum halmac_cs_periodic_option periodic_option;
1021 enum halmac_pri_ch_idx dest_pri_ch_idx;
1022 /* u32 tsf_high; */
1023 u32 tsf_low;
1024 u8 switch_en;
1025 u8 dest_ch_en;
1026 u8 absolute_time_en;
1027 u8 dest_ch;
1028 u8 scan_mode_en;
1029 u8 normal_period;
1030 u8 normal_period_sel;
1031 u8 normal_cycle;
1032 u8 phase_2_period;
1033 u8 phase_2_period_sel;
1034 u8 nlo_en;
1035 };
1036
1037 struct halmac_drop_pkt_option {
1038 u8 drop_all:1;
1039 u8 drop_single:1;
1040 u8 rsvd:6;
1041 u8 drop_index;
1042 };
1043
1044 struct halmac_p2pps {
1045 u8 offload_en:1;
1046 u8 role:1;
1047 u8 ctwindow_en:1;
1048 u8 noa_en:1;
1049 u8 noa_sel:1;
1050 u8 all_sta_sleep:1;
1051 u8 discovery:1;
1052 u8 disable_close_rf:1;
1053 u8 p2p_port_id;
1054 u8 p2p_group;
1055 u8 p2p_macid;
1056 u8 ctwindow_length;
1057 u8 rsvd3;
1058 u8 rsvd4;
1059 u8 rsvd5;
1060 u32 noa_duration_para;
1061 u32 noa_interval_para;
1062 u32 noa_start_time_para;
1063 u32 noa_count_para;
1064 };
1065
1066 struct halmac_fw_build_time {
1067 u16 year;
1068 u8 month;
1069 u8 date;
1070 u8 hour;
1071 u8 min;
1072 };
1073
1074 struct halmac_fw_version {
1075 u16 version;
1076 u8 sub_version;
1077 u8 sub_index;
1078 u16 h2c_version;
1079 struct halmac_fw_build_time build_time;
1080 };
1081
1082 enum halmac_rf_type {
1083 HALMAC_RF_1T2R = 0,
1084 HALMAC_RF_2T4R = 1,
1085 HALMAC_RF_2T2R = 2,
1086 HALMAC_RF_2T3R = 3,
1087 HALMAC_RF_1T1R = 4,
1088 HALMAC_RF_2T2R_GREEN = 5,
1089 HALMAC_RF_3T3R = 6,
1090 HALMAC_RF_3T4R = 7,
1091 HALMAC_RF_4T4R = 8,
1092 HALMAC_RF_MAX_TYPE = 0xF,
1093 };
1094
1095 struct halmac_general_info {
1096 u8 rfe_type;
1097 enum halmac_rf_type rf_type;
1098 u8 tx_ant_status;
1099 u8 rx_ant_status;
1100 u8 ext_pa;
1101 u8 package_type;
1102 u8 mp_mode;
1103 };
1104
1105 struct halmac_pwr_tracking_para {
1106 u8 enable;
1107 u8 tx_pwr_index;
1108 u8 pwr_tracking_offset_value;
1109 u8 tssi_value;
1110 };
1111
1112 struct halmac_pwr_tracking_option {
1113 u8 type;
1114 u8 bbswing_index;
1115 /* pathA, pathB, pathC, pathD */
1116 struct halmac_pwr_tracking_para pwr_tracking_para[4];
1117 };
1118
1119 struct halmac_fast_edca_cfg {
1120 enum halmac_acq_id acq_id;
1121 u8 queue_to; /* unit : 32us*/
1122 };
1123
1124 struct halmac_txfifo_lifetime_cfg {
1125 u8 enable;
1126 u32 lifetime;
1127 };
1128
1129 enum halmac_data_rate {
1130 HALMAC_CCK1,
1131 HALMAC_CCK2,
1132 HALMAC_CCK5_5,
1133 HALMAC_CCK11,
1134 HALMAC_OFDM6,
1135 HALMAC_OFDM9,
1136 HALMAC_OFDM12,
1137 HALMAC_OFDM18,
1138 HALMAC_OFDM24,
1139 HALMAC_OFDM36,
1140 HALMAC_OFDM48,
1141 HALMAC_OFDM54,
1142 HALMAC_MCS0,
1143 HALMAC_MCS1,
1144 HALMAC_MCS2,
1145 HALMAC_MCS3,
1146 HALMAC_MCS4,
1147 HALMAC_MCS5,
1148 HALMAC_MCS6,
1149 HALMAC_MCS7,
1150 HALMAC_MCS8,
1151 HALMAC_MCS9,
1152 HALMAC_MCS10,
1153 HALMAC_MCS11,
1154 HALMAC_MCS12,
1155 HALMAC_MCS13,
1156 HALMAC_MCS14,
1157 HALMAC_MCS15,
1158 HALMAC_MCS16,
1159 HALMAC_MCS17,
1160 HALMAC_MCS18,
1161 HALMAC_MCS19,
1162 HALMAC_MCS20,
1163 HALMAC_MCS21,
1164 HALMAC_MCS22,
1165 HALMAC_MCS23,
1166 HALMAC_MCS24,
1167 HALMAC_MCS25,
1168 HALMAC_MCS26,
1169 HALMAC_MCS27,
1170 HALMAC_MCS28,
1171 HALMAC_MCS29,
1172 HALMAC_MCS30,
1173 HALMAC_MCS31,
1174 HALMAC_VHT_NSS1_MCS0,
1175 HALMAC_VHT_NSS1_MCS1,
1176 HALMAC_VHT_NSS1_MCS2,
1177 HALMAC_VHT_NSS1_MCS3,
1178 HALMAC_VHT_NSS1_MCS4,
1179 HALMAC_VHT_NSS1_MCS5,
1180 HALMAC_VHT_NSS1_MCS6,
1181 HALMAC_VHT_NSS1_MCS7,
1182 HALMAC_VHT_NSS1_MCS8,
1183 HALMAC_VHT_NSS1_MCS9,
1184 HALMAC_VHT_NSS2_MCS0,
1185 HALMAC_VHT_NSS2_MCS1,
1186 HALMAC_VHT_NSS2_MCS2,
1187 HALMAC_VHT_NSS2_MCS3,
1188 HALMAC_VHT_NSS2_MCS4,
1189 HALMAC_VHT_NSS2_MCS5,
1190 HALMAC_VHT_NSS2_MCS6,
1191 HALMAC_VHT_NSS2_MCS7,
1192 HALMAC_VHT_NSS2_MCS8,
1193 HALMAC_VHT_NSS2_MCS9,
1194 HALMAC_VHT_NSS3_MCS0,
1195 HALMAC_VHT_NSS3_MCS1,
1196 HALMAC_VHT_NSS3_MCS2,
1197 HALMAC_VHT_NSS3_MCS3,
1198 HALMAC_VHT_NSS3_MCS4,
1199 HALMAC_VHT_NSS3_MCS5,
1200 HALMAC_VHT_NSS3_MCS6,
1201 HALMAC_VHT_NSS3_MCS7,
1202 HALMAC_VHT_NSS3_MCS8,
1203 HALMAC_VHT_NSS3_MCS9,
1204 HALMAC_VHT_NSS4_MCS0,
1205 HALMAC_VHT_NSS4_MCS1,
1206 HALMAC_VHT_NSS4_MCS2,
1207 HALMAC_VHT_NSS4_MCS3,
1208 HALMAC_VHT_NSS4_MCS4,
1209 HALMAC_VHT_NSS4_MCS5,
1210 HALMAC_VHT_NSS4_MCS6,
1211 HALMAC_VHT_NSS4_MCS7,
1212 HALMAC_VHT_NSS4_MCS8,
1213 HALMAC_VHT_NSS4_MCS9,
1214 /*FPGA only*/
1215 HALMAC_VHT_NSS5_MCS0,
1216 HALMAC_VHT_NSS6_MCS0,
1217 HALMAC_VHT_NSS7_MCS0,
1218 HALMAC_VHT_NSS8_MCS0
1219 };
1220
1221 enum halmac_rf_path {
1222 HALMAC_RF_PATH_A,
1223 HALMAC_RF_PATH_B,
1224 HALMAC_RF_PATH_C,
1225 HALMAC_RF_PATH_D,
1226 HALMAC_RF_SYN_0,
1227 HALMAC_RF_SYN_1
1228 };
1229
1230 enum hal_security_type {
1231 HAL_SECURITY_TYPE_NONE = 0,
1232 HAL_SECURITY_TYPE_WEP40 = 1,
1233 HAL_SECURITY_TYPE_WEP104 = 2,
1234 HAL_SECURITY_TYPE_TKIP = 3,
1235 HAL_SECURITY_TYPE_AES128 = 4,
1236 HAL_SECURITY_TYPE_WAPI = 5,
1237 HAL_SECURITY_TYPE_AES256 = 6,
1238 HAL_SECURITY_TYPE_GCMP128 = 7,
1239 HAL_SECURITY_TYPE_GCMP256 = 8,
1240 HAL_SECURITY_TYPE_GCMSMS4 = 9,
1241 HAL_SECURITY_TYPE_BIP = 10,
1242 HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
1243 };
1244
1245 enum hal_intf_phy {
1246 HAL_INTF_PHY_USB2 = 0,
1247 HAL_INTF_PHY_USB3 = 1,
1248 HAL_INTF_PHY_PCIE_GEN1 = 2,
1249 HAL_INTF_PHY_PCIE_GEN2 = 3,
1250 HAL_INTF_PHY_UNDEFINE = 0x7F,
1251 };
1252
1253 struct halmac_cut_amsdu_cfg {
1254 u8 cut_amsdu_en;
1255 u8 chk_len_en;
1256 u8 chk_len_def_val;
1257 u8 chk_len_l_th;
1258 u16 chk_len_h_th;
1259 };
1260
1261 enum halmac_dbg_msg_info {
1262 HALMAC_DBG_ALWAYS,
1263 HALMAC_DBG_ERR,
1264 HALMAC_DBG_WARN,
1265 HALMAC_DBG_TRACE,
1266 };
1267
1268 enum halmac_dbg_msg_type {
1269 HALMAC_MSG_INIT,
1270 HALMAC_MSG_EFUSE,
1271 HALMAC_MSG_FW,
1272 HALMAC_MSG_H2C,
1273 HALMAC_MSG_PWR,
1274 HALMAC_MSG_SND,
1275 HALMAC_MSG_COMMON,
1276 HALMAC_MSG_DBI,
1277 HALMAC_MSG_MDIO,
1278 HALMAC_MSG_USB,
1279 };
1280
1281 enum halmac_feature_id {
1282 HALMAC_FEATURE_CFG_PARA, /* Support */
1283 HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */
1284 HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */
1285 HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK, /* Support */
1286 HALMAC_FEATURE_UPDATE_PACKET, /* Support */
1287 HALMAC_FEATURE_SEND_SCAN_PACKET, /* Support */
1288 HALMAC_FEATURE_DROP_SCAN_PACKET, /* Support */
1289 HALMAC_FEATURE_UPDATE_DATAPACK,
1290 HALMAC_FEATURE_RUN_DATAPACK,
1291 HALMAC_FEATURE_CHANNEL_SWITCH, /* Support */
1292 HALMAC_FEATURE_IQK, /* Support */
1293 HALMAC_FEATURE_POWER_TRACKING, /* Support */
1294 HALMAC_FEATURE_PSD, /* Support */
1295 HALMAC_FEATURE_FW_SNDING, /* Support */
1296 HALMAC_FEATURE_DPK, /* Support */
1297 HALMAC_FEATURE_ALL, /* Support, only for reset */
1298 };
1299
1300 enum halmac_drv_rsvd_pg_num {
1301 HALMAC_RSVD_PG_NUM8, /* 1K */
1302 HALMAC_RSVD_PG_NUM16, /* 2K */
1303 HALMAC_RSVD_PG_NUM24, /* 3K */
1304 HALMAC_RSVD_PG_NUM32, /* 4K */
1305 HALMAC_RSVD_PG_NUM64, /* 8K */
1306 HALMAC_RSVD_PG_NUM128, /* 16K */
1307 HALMAC_RSVD_PG_NUM256, /* 32K */
1308 HALMAC_RSVD_PG_NUM512, /* 64K */
1309 HALMAC_RSVD_PG_NUM1024, /* 128K */
1310 HALMAC_RSVD_PG_NUM1460, /* 182K */
1311 };
1312
1313 enum halmac_pcie_cfg {
1314 HALMAC_PCIE_GEN1,
1315 HALMAC_PCIE_GEN2,
1316 HALMAC_PCIE_CFG_UNDEFINE,
1317 };
1318
1319 enum halmac_portid {
1320 HALMAC_PORTID0 = 0,
1321 HALMAC_PORTID1 = 1,
1322 HALMAC_PORTID2 = 2,
1323 HALMAC_PORTID3 = 3,
1324 HALMAC_PORTID4 = 4,
1325 HALMAC_PORTID_NUM = 5,
1326 };
1327
1328 struct halmac_bcn_ctrl {
1329 u8 dis_rx_bssid_fit;
1330 u8 en_txbcn_rpt;
1331 u8 dis_tsf_udt;
1332 u8 en_bcn;
1333 u8 en_rxbcn_rpt;
1334 u8 en_p2p_ctwin;
1335 u8 en_p2p_bcn_area;
1336 };
1337
1338 /* User only can use Address[6]*/
1339 /* Address[0] is lowest, Address[5] is highest */
1340 union halmac_wlan_addr {
1341 u8 addr[6];
1342 struct {
1343 union {
1344 __le32 low;
1345 u8 low_byte[4];
1346 };
1347 union {
1348 __le16 high;
1349 u8 high_byte[2];
1350 };
1351 } addr_l_h;
1352 };
1353
1354 struct halmac_platform_api {
1355 /* R/W register */
1356 u8 (*SDIO_CMD52_READ)(void *drv_adapter, u32 offset);
1357 u8 (*SDIO_CMD53_READ_8)(void *drv_adapter, u32 offset);
1358 u16 (*SDIO_CMD53_READ_16)(void *drv_adapter, u32 offset);
1359 u32 (*SDIO_CMD53_READ_32)(void *drv_adapter, u32 offset);
1360 u8 (*SDIO_CMD53_READ_N)(void *drv_adapter, u32 offset, u32 size,
1361 u8 *data);
1362 void (*SDIO_CMD52_WRITE)(void *drv_adapter, u32 offset, u8 value);
1363 void (*SDIO_CMD53_WRITE_8)(void *drv_adapter, u32 offset, u8 value);
1364 void (*SDIO_CMD53_WRITE_16)(void *drv_adapter, u32 offset, u16 value);
1365 void (*SDIO_CMD53_WRITE_32)(void *drv_adapter, u32 offset, u32 value);
1366 u8 (*REG_READ_8)(void *drv_adapter, u32 offset);
1367 u16 (*REG_READ_16)(void *drv_adapter, u32 offset);
1368 u32 (*REG_READ_32)(void *drv_adapter, u32 offset);
1369 void (*REG_WRITE_8)(void *drv_adapter, u32 offset, u8 value);
1370 void (*REG_WRITE_16)(void *drv_adapter, u32 offset, u16 value);
1371 void (*REG_WRITE_32)(void *drv_adapter, u32 offset, u32 value);
1372 u8 (*SDIO_CMD52_CIA_READ)(void *drv_adapter, u32 offset);
1373
1374 /* send pBuf to reserved page, the tx_desc is not included in pBuf */
1375 /* driver need to fill tx_desc with qsel = bcn */
1376 u8 (*SEND_RSVD_PAGE)(void *drv_adapter, u8 *buf, u32 size);
1377 /* send pBuf to h2c queue, the tx_desc is not included in pBuf */
1378 /* driver need to fill tx_desc with qsel = h2c */
1379 u8 (*SEND_H2C_PKT)(void *drv_adapter, u8 *buf, u32 size);
1380
1381 u8 (*RTL_FREE)(void *drv_adapter, void *buf, u32 size);
1382 void* (*RTL_MALLOC)(void *drv_adapter, u32 size);
1383 u8 (*RTL_MEMCPY)(void *drv_adapter, void *dest, void *src, u32 size);
1384 u8 (*RTL_MEMSET)(void *drv_adapter, void *addr, u8 value, u32 size);
1385 void (*RTL_DELAY_US)(void *drv_adapter, u32 us);
1386
1387 u8 (*MUTEX_INIT)(void *drv_adapter, HALMAC_MUTEX *mutex);
1388 u8 (*MUTEX_DEINIT)(void *drv_adapter, HALMAC_MUTEX *mutex);
1389 u8 (*MUTEX_LOCK)(void *drv_adapter, HALMAC_MUTEX *mutex);
1390 u8 (*MUTEX_UNLOCK)(void *drv_adapter, HALMAC_MUTEX *mutex);
1391
1392 u8 (*MSG_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level,
1393 s8 *fmt, ...);
1394 u8 (*BUFF_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level, s8 *buf,
1395 u32 size);
1396
1397 u8 (*EVENT_INDICATION)(void *drv_adapter,
1398 enum halmac_feature_id feature_id,
1399 enum halmac_cmd_process_status process_status,
1400 u8 *buf, u32 size);
1401 #if HALMAC_DBG_MONITOR_IO
1402 void (*READ_MONITOR)(void *drv_adapter, u32 offset, u32 byte, u32 val,
1403 const char *caller, const u32 line);
1404 void (*WRITE_MONITOR)(void *drv_adapter, u32 offset, u32 byte, u32 val,
1405 const char *caller, const u32 line);
1406 #endif
1407 #if HALMAC_PLATFORM_TESTPROGRAM
1408 struct halmisc_platform_api *halmisc_pltfm_api;
1409 #endif
1410 };
1411
1412 enum halmac_snd_role {
1413 HAL_BFER = 0,
1414 HAL_BFEE = 1,
1415 };
1416
1417 enum halmac_csi_seg_len {
1418 HAL_CSI_SEG_4K = 0,
1419 HAL_CSI_SEG_8K = 1,
1420 HAL_CSI_SEG_11K = 2,
1421 };
1422
1423 struct halmac_cfg_mumimo_para {
1424 enum halmac_snd_role role;
1425 u8 sounding_sts[6];
1426 u16 grouping_bitmap;
1427 u8 mu_tx_en;
1428 u32 given_gid_tab[2];
1429 u32 given_user_pos[4];
1430 };
1431
1432 struct halmac_su_bfer_init_para {
1433 u8 userid;
1434 u16 paid;
1435 u16 csi_para;
1436 union halmac_wlan_addr bfer_address;
1437 };
1438
1439 struct halmac_mu_bfee_init_para {
1440 u8 userid;
1441 u16 paid;
1442 u32 user_position_l; /*for gid 0~15*/
1443 u32 user_position_h; /*for gid 16~31*/
1444 u32 user_position_l_1; /*for gid 32~47*/
1445 u32 user_position_h_1; /*for gid 48~63*/
1446 };
1447
1448 struct halmac_mu_bfer_init_para {
1449 u16 paid;
1450 u16 csi_para;
1451 u16 my_aid;
1452 enum halmac_csi_seg_len csi_length_sel;
1453 union halmac_wlan_addr bfer_address;
1454 };
1455
1456 struct halmac_ch_sw_info {
1457 u8 *buf;
1458 u8 *buf_wptr;
1459 u8 scan_mode;
1460 u8 extra_info_en;
1461 u32 buf_size;
1462 u32 avl_buf_size;
1463 u32 total_size;
1464 u32 ch_num;
1465 };
1466
1467 struct halmac_ch_sw_extra_scan {
1468 u8 dwell_ext_val:7;
1469 u8 dwell_ext_en:1;
1470 u8 dwell_ext_c2h:1;
1471 u8 post_tx_c2h:1;
1472 u8 pre_tx_c2h:1;
1473 u8 post_switch_c2h:1;
1474 u8 pre_switch_c2h:1;
1475 u8 rsvd0:2;
1476 u8 wait_probrsp:1;
1477 u8 txid:7;
1478 u8 rsvd1:1;
1479 };
1480
1481 struct halmac_scan_rpt_info {
1482 u8 *buf;
1483 u8 *buf_wptr;
1484 u32 buf_size;
1485 u32 avl_buf_size;
1486 u32 total_size;
1487 u32 ack_tsf_low;
1488 u32 ack_tsf_high;
1489 u32 rpt_tsf_low;
1490 u32 rpt_tsf_high;
1491 };
1492
1493 struct halmac_event_trigger {
1494 u32 phy_efuse_map : 1;
1495 u32 log_efuse_map : 1;
1496 u32 log_efuse_mask : 1;
1497 u32 rsvd1 : 27;
1498 };
1499
1500 struct halmac_h2c_header_info {
1501 u16 sub_cmd_id;
1502 u16 content_size;
1503 u8 ack;
1504 };
1505
1506 struct halmac_ver {
1507 u8 major_ver;
1508 u8 prototype_ver;
1509 u8 minor_ver;
1510 u8 patch_ver;
1511 };
1512
1513 enum halmac_api_id {
1514 /*stuff, need to be the 1st*/
1515 HALMAC_API_STUFF = 0x0,
1516 /*stuff, need to be the 1st*/
1517 HALMAC_API_MAC_POWER_SWITCH = 0x1,
1518 HALMAC_API_DOWNLOAD_FIRMWARE = 0x2,
1519 HALMAC_API_CFG_MAC_ADDR = 0x3,
1520 HALMAC_API_CFG_BSSID = 0x4,
1521 HALMAC_API_CFG_MULTICAST_ADDR = 0x5,
1522 HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,
1523 HALMAC_API_INIT_SYSTEM_CFG = 0x7,
1524 HALMAC_API_INIT_TRX_CFG = 0x8,
1525 HALMAC_API_CFG_RX_AGGREGATION = 0x9,
1526 HALMAC_API_INIT_PROTOCOL_CFG = 0xA,
1527 HALMAC_API_INIT_EDCA_CFG = 0xB,
1528 HALMAC_API_CFG_OPERATION_MODE = 0xC,
1529 HALMAC_API_CFG_CH_BW = 0xD,
1530 HALMAC_API_CFG_BW = 0xE,
1531 HALMAC_API_INIT_WMAC_CFG = 0xF,
1532 HALMAC_API_INIT_MAC_CFG = 0x10,
1533 HALMAC_API_INIT_SDIO_CFG = 0x11,
1534 HALMAC_API_INIT_USB_CFG = 0x12,
1535 HALMAC_API_INIT_PCIE_CFG = 0x13,
1536 HALMAC_API_INIT_INTERFACE_CFG = 0x14,
1537 HALMAC_API_DEINIT_SDIO_CFG = 0x15,
1538 HALMAC_API_DEINIT_USB_CFG = 0x16,
1539 HALMAC_API_DEINIT_PCIE_CFG = 0x17,
1540 HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
1541 HALMAC_API_GET_EFUSE_SIZE = 0x19,
1542 HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
1543 HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
1544 HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
1545 HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
1546 HALMAC_API_READ_LOGICAL_EFUSE = 0x20,
1547 HALMAC_API_PG_EFUSE_BY_MAP = 0x21,
1548 HALMAC_API_GET_C2H_INFO = 0x22,
1549 HALMAC_API_CFG_FWLPS_OPTION = 0x23,
1550 HALMAC_API_CFG_FWIPS_OPTION = 0x24,
1551 HALMAC_API_ENTER_WOWLAN = 0x25,
1552 HALMAC_API_LEAVE_WOWLAN = 0x26,
1553 HALMAC_API_ENTER_PS = 0x27,
1554 HALMAC_API_LEAVE_PS = 0x28,
1555 HALMAC_API_H2C_LB = 0x29,
1556 HALMAC_API_DEBUG = 0x2A,
1557 HALMAC_API_CFG_PARAMETER = 0x2B,
1558 HALMAC_API_UPDATE_PACKET = 0x2C,
1559 HALMAC_API_BCN_IE_FILTER = 0x2D,
1560 HALMAC_API_REG_READ_8 = 0x2E,
1561 HALMAC_API_REG_WRITE_8 = 0x2F,
1562 HALMAC_API_REG_READ_16 = 0x30,
1563 HALMAC_API_REG_WRITE_16 = 0x31,
1564 HALMAC_API_REG_READ_32 = 0x32,
1565 HALMAC_API_REG_WRITE_32 = 0x33,
1566 HALMAC_API_TX_ALLOWED_SDIO = 0x34,
1567 HALMAC_API_SET_BULKOUT_NUM = 0x35,
1568 HALMAC_API_GET_SDIO_TX_ADDR = 0x36,
1569 HALMAC_API_GET_USB_BULKOUT_ID = 0x37,
1570 HALMAC_API_TIMER_2S = 0x38,
1571 HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,
1572 HALMAC_API_SEND_ORIGINAL_H2C = 0x3A,
1573 HALMAC_API_UPDATE_DATAPACK = 0x3B,
1574 HALMAC_API_RUN_DATAPACK = 0x3C,
1575 HALMAC_API_CFG_DRV_INFO = 0x3D,
1576 HALMAC_API_SEND_BT_COEX = 0x3E,
1577 HALMAC_API_VERIFY_PLATFORM_API = 0x3F,
1578 HALMAC_API_GET_FIFO_SIZE = 0x40,
1579 HALMAC_API_DUMP_FIFO = 0x41,
1580 HALMAC_API_CFG_TXBF = 0x42,
1581 HALMAC_API_CFG_MUMIMO = 0x43,
1582 HALMAC_API_CFG_SOUNDING = 0x44,
1583 HALMAC_API_DEL_SOUNDING = 0x45,
1584 HALMAC_API_SU_BFER_ENTRY_INIT = 0x46,
1585 HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,
1586 HALMAC_API_MU_BFER_ENTRY_INIT = 0x48,
1587 HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,
1588 HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,
1589 HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
1590 HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
1591 HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
1592 HALMAC_API_ADD_CH_INFO = 0x4E,
1593 HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
1594 HALMAC_API_CTRL_CH_SWITCH = 0x50,
1595 HALMAC_API_CLEAR_CH_INFO = 0x51,
1596 HALMAC_API_SEND_GENERAL_INFO = 0x52,
1597 HALMAC_API_START_IQK = 0x53,
1598 HALMAC_API_CTRL_PWR_TRACKING = 0x54,
1599 HALMAC_API_PSD = 0x55,
1600 HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
1601 HALMAC_API_QUERY_STATE = 0x57,
1602 HALMAC_API_RESET_FEATURE = 0x58,
1603 HALMAC_API_CHECK_FW_STATUS = 0x59,
1604 HALMAC_API_DUMP_FW_DMEM = 0x5A,
1605 HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
1606 HALMAC_API_INIT_OBJ = 0x5C,
1607 HALMAC_API_DEINIT_OBJ = 0x5D,
1608 HALMAC_API_CFG_LA_MODE = 0x5E,
1609 HALMAC_API_GET_HW_VALUE = 0x5F,
1610 HALMAC_API_SET_HW_VALUE = 0x60,
1611 HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
1612 HALMAC_API_WRITE_EFUSE_BT = 0x63,
1613 HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
1614 HALMAC_API_DL_DRV_RSVD_PG = 0x65,
1615 HALMAC_API_PCIE_SWITCH = 0x66,
1616 HALMAC_API_PHY_CFG = 0x67,
1617 HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68,
1618 HALMAC_API_CFG_CSI_RATE = 0x69,
1619 HALMAC_API_P2PPS = 0x6A,
1620 HALMAC_API_CFG_TX_ADDR = 0x6B,
1621 HALMAC_API_CFG_NET_TYPE = 0x6C,
1622 HALMAC_API_CFG_TSF_RESET = 0x6D,
1623 HALMAC_API_CFG_BCN_SPACE = 0x6E,
1624 HALMAC_API_CFG_BCN_CTRL = 0x6F,
1625 HALMAC_API_CFG_SIDEBAND_INT = 0x70,
1626 HALMAC_API_REGISTER_API = 0x71,
1627 HALMAC_API_FREE_DOWNLOAD_FIRMWARE = 0x72,
1628 HALMAC_API_GET_FW_VERSION = 0x73,
1629 HALMAC_API_GET_EFUSE_AVAL_SIZE = 0x74,
1630 HALMAC_API_CHK_TXDESC = 0x75,
1631 HALMAC_API_SDIO_CMD53_4BYTE = 0x76,
1632 HALMAC_API_CFG_TRANS_ADDR = 0x77,
1633 HALMAC_API_INTF_INTEGRA_TUNING = 0x78,
1634 HALMAC_API_TXFIFO_IS_EMPTY = 0x79,
1635 HALMAC_API_DOWNLOAD_FLASH = 0x7A,
1636 HALMAC_API_READ_FLASH = 0x7B,
1637 HALMAC_API_ERASE_FLASH = 0x7C,
1638 HALMAC_API_CHECK_FLASH = 0x7D,
1639 HALMAC_API_SDIO_HW_INFO = 0x80,
1640 HALMAC_API_READ_EFUSE_BT = 0x81,
1641 HALMAC_API_CFG_EFUSE_AUTO_CHECK = 0x82,
1642 HALMAC_API_CFG_PINMUX_GET_FUNC = 0x83,
1643 HALMAC_API_CFG_PINMUX_SET_FUNC = 0x84,
1644 HALMAC_API_CFG_PINMUX_FREE_FUNC = 0x85,
1645 HALMAC_API_CFG_PINMUX_WL_LED_MODE = 0x86,
1646 HALMAC_API_CFG_PINMUX_WL_LED_SW_CTRL = 0x87,
1647 HALMAC_API_CFG_PINMUX_SDIO_INT_POLARITY = 0x88,
1648 HALMAC_API_CFG_PINMUX_GPIO_MODE = 0x89,
1649 HALMAC_API_CFG_PINMUX_GPIO_OUTPUT = 0x90,
1650 HALMAC_API_REG_READ_INDIRECT_32 = 0x91,
1651 HALMAC_API_REG_SDIO_CMD53_READ_N = 0x92,
1652 HALMAC_API_PINMUX_PIN_STATUS = 0x94,
1653 HALMAC_API_OFLD_FUNC_CFG = 0x95,
1654 HALMAC_API_MASK_LOGICAL_EFUSE = 0x96,
1655 HALMAC_API_RX_CUT_AMSDU_CFG = 0x97,
1656 HALMAC_API_FW_SNDING = 0x98,
1657 HALMAC_API_ENTER_CPU_SLEEP_MODE = 0x99,
1658 HALMAC_API_GET_CPU_MODE = 0x9A,
1659 HALMAC_API_DRV_FWCTRL = 0x9B,
1660 HALMAC_API_EN_REF_AUTOK = 0x9C,
1661 HALMAC_API_RESET_WIFI_FW = 0x9D,
1662 HALMAC_API_CFGSPC_SET_PCIE = 0x9E,
1663 HALMAC_API_GET_WATCHER = 0x9F,
1664 HALMAC_API_DUMP_LOGICAL_EFUSE_MASK = 0xA0,
1665 HALMAC_API_WRITE_LOGICAL_EFUSE_WORD = 0xA1,
1666 HALMAC_API_READ_WIFI_PHY_EFUSE = 0xA2,
1667 HALMAC_API_WRITE_WIFI_PHY_EFUSE = 0xA3,
1668 HALMAC_API_START_DPK = 0xA4,
1669 HALMAC_API_MAX
1670 };
1671
1672 enum halmac_la_mode {
1673 HALMAC_LA_MODE_DISABLE = 0,
1674 HALMAC_LA_MODE_PARTIAL = 1,
1675 HALMAC_LA_MODE_FULL = 2,
1676 HALMAC_LA_MODE_UNDEFINE = 0x7F,
1677 };
1678
1679 enum halmac_rx_fifo_expanding_mode {
1680 HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0,
1681 HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1,
1682 HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2,
1683 HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3,
1684 HALMAC_RX_FIFO_EXPANDING_MODE_4_BLOCK = 4,
1685 HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F,
1686 };
1687
1688 enum halmac_sdio_cmd53_4byte_mode {
1689 HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0,
1690 HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1,
1691 HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2,
1692 HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3,
1693 HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F,
1694 };
1695
1696 enum halmac_usb_mode {
1697 HALMAC_USB_MODE_U2 = 1,
1698 HALMAC_USB_MODE_U3 = 2,
1699 };
1700
1701 enum halmac_sdio_tx_format {
1702 HALMAC_SDIO_AGG_MODE = 1,
1703 HALMAC_SDIO_DUMMY_BLOCK_MODE = 2,
1704 HALMAC_SDIO_DUMMY_AUTO_MODE = 3,
1705 };
1706
1707 enum halmac_sdio_clk_monitor {
1708 HALMAC_MONITOR_5US = 1,
1709 HALMAC_MONITOR_50US = 2,
1710 HALMAC_MONITOR_9MS = 3,
1711 };
1712
1713 enum halmac_hw_id {
1714 /* Get HW value */
1715 HALMAC_HW_RQPN_MAPPING = 0x00,
1716 HALMAC_HW_EFUSE_SIZE = 0x01,
1717 HALMAC_HW_EEPROM_SIZE = 0x02,
1718 HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03,
1719 HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04,
1720 HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05,
1721 HALMAC_HW_TXFIFO_SIZE = 0x06,
1722 HALMAC_HW_RXFIFO_SIZE = 0x07,
1723 HALMAC_HW_RSVD_PG_BNDY = 0x08,
1724 HALMAC_HW_CAM_ENTRY_NUM = 0x09,
1725 HALMAC_HW_IC_VERSION = 0x0A,
1726 HALMAC_HW_PAGE_SIZE = 0x0B,
1727 HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0C,
1728 HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0D,
1729 HALMAC_HW_DRV_INFO_SIZE = 0x0E,
1730 HALMAC_HW_TXFF_ALLOCATION = 0x0F,
1731 HALMAC_HW_RSVD_EFUSE_SIZE = 0x10,
1732 HALMAC_HW_FW_HDR_SIZE = 0x11,
1733 HALMAC_HW_TX_DESC_SIZE = 0x12,
1734 HALMAC_HW_RX_DESC_SIZE = 0x13,
1735 HALMAC_HW_FW_MAX_SIZE = 0x14,
1736 HALMAC_HW_ORI_H2C_SIZE = 0x15,
1737 HALMAC_HW_RSVD_DRV_PGNUM = 0x16,
1738 HALMAC_HW_TX_PAGE_SIZE = 0x17,
1739 HALMAC_HW_USB_TXAGG_DESC_NUM = 0x18,
1740 HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x19,
1741 HALMAC_HW_AC_OQT_SIZE = 0x1C,
1742 HALMAC_HW_NON_AC_OQT_SIZE = 0x1D,
1743 HALMAC_HW_AC_QUEUE_NUM = 0x1E,
1744 HALMAC_HW_RQPN_CH_MAPPING = 0x1F,
1745 HALMAC_HW_PWR_STATE = 0x20,
1746 HALMAC_HW_SDIO_INT_LAT = 0x21,
1747 HALMAC_HW_SDIO_CLK_CNT = 0x22,
1748 /* Set HW value */
1749 HALMAC_HW_USB_MODE = 0x60,
1750 HALMAC_HW_SEQ_EN = 0x61,
1751 HALMAC_HW_BANDWIDTH = 0x62,
1752 HALMAC_HW_CHANNEL = 0x63,
1753 HALMAC_HW_PRI_CHANNEL_IDX = 0x64,
1754 HALMAC_HW_EN_BB_RF = 0x65,
1755 HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66,
1756 HALMAC_HW_AMPDU_CONFIG = 0x67,
1757 HALMAC_HW_RX_SHIFT = 0x68,
1758 HALMAC_HW_TXDESC_CHECKSUM = 0x69,
1759 HALMAC_HW_RX_CLK_GATE = 0x6A,
1760 HALMAC_HW_RXGCK_FIFO = 0x6B,
1761 HALMAC_HW_RX_IGNORE = 0x6C,
1762 HALMAC_HW_SDIO_TX_FORMAT = 0x6D,
1763 HALMAC_HW_FAST_EDCA = 0x6E,
1764 HALMAC_HW_LDO25_EN = 0x6F,
1765 HALMAC_HW_PCIE_REF_AUTOK = 0x70,
1766 HALMAC_HW_RTS_FULL_BW = 0x71,
1767 HALMAC_HW_FREE_CNT_EN = 0x72,
1768 HALMAC_HW_SDIO_WT_EN = 0x73,
1769 HALMAC_HW_SDIO_CLK_MONITOR = 0x74,
1770 HALMAC_HW_TXFIFO_LIFETIME = 0x75,
1771 HALMAC_HW_ID_UNDEFINE = 0x7F,
1772 };
1773
1774 enum halmac_efuse_bank {
1775 HALMAC_EFUSE_BANK_WIFI = 0,
1776 HALMAC_EFUSE_BANK_BT = 1,
1777 HALMAC_EFUSE_BANK_BT_1 = 2,
1778 HALMAC_EFUSE_BANK_BT_2 = 3,
1779 HALMAC_EFUSE_BANK_MAX,
1780 HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
1781 };
1782
1783 enum halmac_sdio_spec_ver {
1784 HALMAC_SDIO_SPEC_VER_2_00 = 0,
1785 HALMAC_SDIO_SPEC_VER_3_00 = 1,
1786 HALMAC_SDIO_SPEC_VER_UNDEFINE = 0X7F,
1787 };
1788
1789 enum halmac_gpio_func {
1790 HALMAC_GPIO_FUNC_WL_LED = 0,
1791 HALMAC_GPIO_FUNC_SDIO_INT = 1,
1792 HALMAC_GPIO_FUNC_SW_IO_0 = 2,
1793 HALMAC_GPIO_FUNC_SW_IO_1 = 3,
1794 HALMAC_GPIO_FUNC_SW_IO_2 = 4,
1795 HALMAC_GPIO_FUNC_SW_IO_3 = 5,
1796 HALMAC_GPIO_FUNC_SW_IO_4 = 6,
1797 HALMAC_GPIO_FUNC_SW_IO_5 = 7,
1798 HALMAC_GPIO_FUNC_SW_IO_6 = 8,
1799 HALMAC_GPIO_FUNC_SW_IO_7 = 9,
1800 HALMAC_GPIO_FUNC_SW_IO_8 = 10,
1801 HALMAC_GPIO_FUNC_SW_IO_9 = 11,
1802 HALMAC_GPIO_FUNC_SW_IO_10 = 12,
1803 HALMAC_GPIO_FUNC_SW_IO_11 = 13,
1804 HALMAC_GPIO_FUNC_SW_IO_12 = 14,
1805 HALMAC_GPIO_FUNC_SW_IO_13 = 15,
1806 HALMAC_GPIO_FUNC_SW_IO_14 = 16,
1807 HALMAC_GPIO_FUNC_SW_IO_15 = 17,
1808 HALMAC_GPIO_FUNC_BT_HOST_WAKE1 = 18,
1809 HALMAC_GPIO_FUNC_BT_DEV_WAKE1 = 19,
1810 HALMAC_GPIO_FUNC_S0_PAPE = 20,
1811 HALMAC_GPIO_FUNC_S1_PAPE = 21,
1812 HALMAC_GPIO_FUNC_S0_TRSW = 22,
1813 HALMAC_GPIO_FUNC_S1_TRSW = 23,
1814 HALMAC_GPIO_FUNC_S0_TRSWB = 24,
1815 HALMAC_GPIO_FUNC_S1_TRSWB = 25,
1816 HALMAC_GPIO_FUNC_ANTSW = 26,
1817 HALMAC_GPIO_FUNC_ANTSWB = 27,
1818 HALMAC_GPIO_FUNC_UNDEFINE = 0X7F,
1819 };
1820
1821 enum halmac_wlled_mode {
1822 HALMAC_WLLED_MODE_TRX = 0,
1823 HALMAC_WLLED_MODE_TX = 1,
1824 HALMAC_WLLED_MODE_RX = 2,
1825 HALMAC_WLLED_MODE_SW_CTRL = 3,
1826 HALMAC_WLLED_MODE_UNDEFINE = 0X7F,
1827 };
1828
1829 enum halmac_psf_fcs_chk_thr {
1830 HALMAC_PSF_FCS_CHK_THR_4 = 1,
1831 HALMAC_PSF_FCS_CHK_THR_8 = 2,
1832 HALMAC_PSF_FCS_CHK_THR_12 = 3,
1833 HALMAC_PSF_FCS_CHK_THR_16 = 4,
1834 HALMAC_PSF_FCS_CHK_THR_20 = 5,
1835 HALMAC_PSF_FCS_CHK_THR_24 = 6,
1836 HALMAC_PSF_FCS_CHK_THR_28 = 7,
1837 };
1838
1839 enum halmac_func_ctrl {
1840 HALMAC_DISABLE = 0,
1841 HALMAC_ENABLE = 1,
1842 HALMAC_DEFAULT = 0xFE,
1843 HALMAC_IGNORE = 0xFF
1844 };
1845
1846 enum halmac_pcie_clkdly {
1847 HALMAC_CLKDLY_0 = 0,
1848 HALMAC_CLKDLY_5US = 1,
1849 HALMAC_CLKDLY_6US = 2,
1850 HALMAC_CLKDLY_11US = 3,
1851 HALMAC_CLKDLY_15US = 4,
1852 HALMAC_CLKDLY_19US = 5,
1853 HALMAC_CLKDLY_25US = 6,
1854 HALMAC_CLKDLY_30US = 7,
1855 HALMAC_CLKDLY_38US = 8,
1856 HALMAC_CLKDLY_50US = 9,
1857 HALMAC_CLKDLY_64US = 10,
1858 HALMAC_CLKDLY_100US = 11,
1859 HALMAC_CLKDLY_128US = 12,
1860 HALMAC_CLKDLY_150US = 13,
1861 HALMAC_CLKDLY_192US = 14,
1862 HALMAC_CLKDLY_200US = 15,
1863 HALMAC_CLKDLY_R_ERR = 0xFD,
1864 HALMAC_CLKDLY_DEF = 0xFE,
1865 HALMAC_CLKDLY_IGNORE = 0xFF
1866 };
1867
1868 enum halmac_pcie_l1dly {
1869 HALMAC_L1DLY_16US = 0,
1870 HALMAC_L1DLY_32US = 1,
1871 HALMAC_L1DLY_64US = 2,
1872 HALMAC_L1DLY_INFI = 3,
1873 HALMAC_L1DLY_R_ERR = 0xFD,
1874 HALMAC_L1DLY_DEF = 0xFE,
1875 HALMAC_L1DLY_IGNORE = 0xFF
1876 };
1877
1878 enum halmac_pcie_l0sdly {
1879 HALMAC_L0SDLY_1US = 0,
1880 HALMAC_L0SDLY_3US = 1,
1881 HALMAC_L0SDLY_5US = 2,
1882 HALMAC_L0SDLY_7US = 3,
1883 HALMAC_L0SDLY_R_ERR = 0xFD,
1884 HALMAC_L0SDLY_DEF = 0xFE,
1885 HALMAC_L0SDLY_IGNORE = 0xFF
1886 };
1887
1888 struct halmac_pcie_cfgspc_param {
1889 u8 write;
1890 u8 read;
1891 enum halmac_func_ctrl l0s_ctrl;
1892 enum halmac_func_ctrl l1_ctrl;
1893 enum halmac_func_ctrl l1ss_ctrl;
1894 enum halmac_func_ctrl wake_ctrl;
1895 enum halmac_func_ctrl crq_ctrl;
1896 enum halmac_pcie_clkdly clkdly_ctrl;
1897 enum halmac_pcie_l0sdly l0sdly_ctrl;
1898 enum halmac_pcie_l1dly l1dly_ctrl;
1899 };
1900
1901 struct halmac_txff_allocation {
1902 u16 tx_fifo_pg_num;
1903 u16 rsvd_pg_num;
1904 u16 rsvd_drv_pg_num;
1905 u16 acq_pg_num;
1906 u16 high_queue_pg_num;
1907 u16 low_queue_pg_num;
1908 u16 normal_queue_pg_num;
1909 u16 extra_queue_pg_num;
1910 u16 pub_queue_pg_num;
1911 u16 rsvd_boundary;
1912 u16 rsvd_drv_addr;
1913 u16 rsvd_h2c_info_addr;
1914 u16 rsvd_h2c_sta_info_addr;
1915 u16 rsvd_h2cq_addr;
1916 u16 rsvd_cpu_instr_addr;
1917 u16 rsvd_fw_txbuf_addr;
1918 u16 rsvd_csibuf_addr;
1919 enum halmac_la_mode la_mode;
1920 enum halmac_rx_fifo_expanding_mode rx_fifo_exp_mode;
1921 };
1922
1923 struct halmac_rqpn_map {
1924 enum halmac_dma_mapping dma_map_vo;
1925 enum halmac_dma_mapping dma_map_vi;
1926 enum halmac_dma_mapping dma_map_be;
1927 enum halmac_dma_mapping dma_map_bk;
1928 enum halmac_dma_mapping dma_map_mg;
1929 enum halmac_dma_mapping dma_map_hi;
1930 };
1931
1932 struct halmac_rqpn_ch_map {
1933 enum halmac_dma_ch dma_map_vo;
1934 enum halmac_dma_ch dma_map_vi;
1935 enum halmac_dma_ch dma_map_be;
1936 enum halmac_dma_ch dma_map_bk;
1937 enum halmac_dma_ch dma_map_mg;
1938 enum halmac_dma_ch dma_map_hi;
1939 };
1940
1941 struct halmac_security_setting {
1942 u8 tx_encryption;
1943 u8 rx_decryption;
1944 u8 bip_enable;
1945 u8 compare_keyid;
1946 };
1947
1948 struct halmac_cam_entry_info {
1949 enum hal_security_type security_type;
1950 u32 key[4];
1951 u32 key_ext[4];
1952 u8 mac_address[6];
1953 u8 unicast;
1954 u8 key_id;
1955 u8 valid;
1956 };
1957
1958 struct halmac_cam_entry_format {
1959 u16 key_id : 2;
1960 u16 type : 3;
1961 u16 mic : 1;
1962 u16 grp : 1;
1963 u16 spp_mode : 1;
1964 u16 rpt_md : 1;
1965 u16 ext_sectype : 1;
1966 u16 mgnt : 1;
1967 u16 rsvd1 : 4;
1968 u16 valid : 1;
1969 u8 mac_address[6];
1970 u32 key[4];
1971 u32 rsvd[2];
1972 };
1973
1974 struct halmac_tx_page_threshold_info {
1975 u32 threshold;
1976 enum halmac_dma_mapping dma_queue_sel;
1977 u8 enable;
1978 };
1979
1980 struct halmac_ampdu_config {
1981 u8 max_agg_num;
1982 u8 max_len_en;
1983 u32 ht_max_len;
1984 u32 vht_max_len;
1985 };
1986
1987 struct halmac_rqpn {
1988 enum halmac_trx_mode mode;
1989 enum halmac_dma_mapping dma_map_vo;
1990 enum halmac_dma_mapping dma_map_vi;
1991 enum halmac_dma_mapping dma_map_be;
1992 enum halmac_dma_mapping dma_map_bk;
1993 enum halmac_dma_mapping dma_map_mg;
1994 enum halmac_dma_mapping dma_map_hi;
1995 };
1996
1997 struct halmac_ch_mapping {
1998 enum halmac_trx_mode mode;
1999 enum halmac_dma_ch dma_map_vo;
2000 enum halmac_dma_ch dma_map_vi;
2001 enum halmac_dma_ch dma_map_be;
2002 enum halmac_dma_ch dma_map_bk;
2003 enum halmac_dma_ch dma_map_mg;
2004 enum halmac_dma_ch dma_map_hi;
2005 };
2006
2007 struct halmac_pg_num {
2008 enum halmac_trx_mode mode;
2009 u16 hq_num;
2010 u16 nq_num;
2011 u16 lq_num;
2012 u16 exq_num;
2013 u16 gap_num;/*used for loopback mode*/
2014 };
2015
2016 struct halmac_ch_pg_num {
2017 enum halmac_trx_mode mode;
2018 u16 ch_num[HALMAC_TXDESC_DMA_CH16 + 1];
2019 u16 gap_num;
2020 };
2021
2022 struct halmac_intf_phy_para {
2023 u16 offset;
2024 u16 value;
2025 u16 ip_sel;
2026 u16 cut;
2027 u16 plaform;
2028 };
2029
2030 struct halmac_iqk_para {
2031 u8 clear;
2032 u8 segment_iqk;
2033 };
2034
2035 struct halmac_txdesc_ie_param {
2036 u8 *start_offset;
2037 u8 *end_offset;
2038 u8 *ie_offset;
2039 u8 *ie_exist;
2040 };
2041
2042 struct halmac_sdio_hw_info {
2043 enum halmac_sdio_spec_ver spec_ver;
2044 u32 clock_speed;
2045 u8 io_hi_speed_flag; /* Halmac internal use */
2046 enum halmac_sdio_tx_format tx_addr_format;
2047 u16 block_size;
2048 u8 tx_seq;
2049 u8 io_indir_flag; /* Halmac internal use */
2050 u8 io_warn_flag; /* SW */
2051 };
2052
2053 struct halmac_edca_para {
2054 u8 aifs;
2055 u8 cw;
2056 u16 txop_limit;
2057 };
2058
2059 struct halmac_mac_rx_ignore_cfg {
2060 u8 hdr_chk_en;
2061 u8 fcs_chk_en;
2062 u8 cck_rst_en;
2063 enum halmac_psf_fcs_chk_thr fcs_chk_thr;
2064 };
2065
2066 struct halmac_rx_ignore_info {
2067 u8 hdr_chk_mask;
2068 u8 fcs_chk_mask;
2069 u8 hdr_chk_en;
2070 u8 fcs_chk_en;
2071 u8 cck_rst_en;
2072 enum halmac_psf_fcs_chk_thr fcs_chk_thr;
2073 };
2074
2075 struct halmac_get_watcher {
2076 u32 sdio_rn_not_align;
2077 };
2078
2079 struct halmac_watcher {
2080 struct halmac_get_watcher get_watcher;
2081 };
2082
2083 struct halmac_pinmux_info {
2084 /* byte0 */
2085 u8 wl_led:1;
2086 u8 sdio_int:1;
2087 u8 bt_host_wake:1;
2088 u8 bt_dev_wake:1;
2089 u8 rsvd1:4;
2090 /* byte1 */
2091 u8 sw_io_0:1;
2092 u8 sw_io_1:1;
2093 u8 sw_io_2:1;
2094 u8 sw_io_3:1;
2095 u8 sw_io_4:1;
2096 u8 sw_io_5:1;
2097 u8 sw_io_6:1;
2098 u8 sw_io_7:1;
2099 /* byte2 */
2100 u8 sw_io_8:1;
2101 u8 sw_io_9:1;
2102 u8 sw_io_10:1;
2103 u8 sw_io_11:1;
2104 u8 sw_io_12:1;
2105 u8 sw_io_13:1;
2106 u8 sw_io_14:1;
2107 u8 sw_io_15:1;
2108 /* byte3 */
2109 u8 s0_trsw:1;
2110 u8 s1_trsw:1;
2111 u8 s0_pape:1;
2112 u8 s1_pape:1;
2113 u8 s0_trswb:1;
2114 u8 s1_trswb:1;
2115 u8 antswb:1;
2116 u8 antsw:1;
2117 };
2118
2119 struct halmac_ofld_func_info {
2120 u32 halmac_malloc_max_sz;
2121 u32 rsvd_pg_drv_buf_max_sz;
2122 };
2123
2124 struct halmac_pltfm_cfg_info {
2125 u32 malloc_size;
2126 u32 rsvd_pg_size;
2127 };
2128
2129 struct halmac_su_snding_info {
2130 u8 su0_en;
2131 u8 *su0_ndpa_pkt;
2132 u32 su0_pkt_sz;
2133 };
2134
2135 struct halmac_mu_snding_info {
2136 u8 tmp;
2137 };
2138
2139 struct halmac_h2c_info {
2140 u32 buf_fs;
2141 u32 buf_size;
2142 u8 seq_num;
2143 };
2144
2145 struct halmac_adapter {
2146 enum halmac_dma_mapping pq_map[HALMAC_PQ_MAP_NUM];
2147 enum halmac_dma_ch ch_map[HALMAC_PQ_MAP_NUM];
2148 HALMAC_MUTEX h2c_seq_mutex; /* protect h2c seq num */
2149 HALMAC_MUTEX efuse_mutex; /*protect adapter efuse map */
2150 HALMAC_MUTEX sdio_indir_mutex; /*protect sdio indirect access */
2151 struct halmac_cfg_param_info cfg_param_info;
2152 struct halmac_ch_sw_info ch_sw_info;
2153 struct halmac_scan_rpt_info scan_rpt_info;
2154 struct halmac_event_trigger evnt;
2155 struct halmac_hw_cfg_info hw_cfg_info;
2156 struct halmac_sdio_free_space sdio_fs;
2157 struct halmac_api_registry api_registry;
2158 struct halmac_pinmux_info pinmux_info;
2159 struct halmac_pltfm_cfg_info pltfm_info;
2160 struct halmac_h2c_info h2c_info;
2161 void *drv_adapter;
2162 u8 *efuse_map;
2163 void *halmac_api;
2164 struct halmac_platform_api *pltfm_api;
2165 u32 efuse_end;
2166 u32 dlfw_pkt_size;
2167 enum halmac_chip_id chip_id;
2168 enum halmac_chip_ver chip_ver;
2169 struct halmac_fw_version fw_ver;
2170 struct halmac_state halmac_state;
2171 enum halmac_interface intf;
2172 enum halmac_trx_mode trx_mode;
2173 struct halmac_txff_allocation txff_alloc;
2174 u8 efuse_map_valid;
2175 u8 efuse_seg_size;
2176 u8 rpwm;
2177 u8 bulkout_num;
2178 u8 drv_info_size;
2179 enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte;
2180 struct halmac_sdio_hw_info sdio_hw_info;
2181 u8 tx_desc_transfer;
2182 u8 tx_desc_checksum;
2183 u8 efuse_auto_check_en;
2184 u8 pcie_refautok_en;
2185 u8 pwr_off_flow_flag;
2186 u8 nlo_flag;
2187 enum halmac_bw curr_bw;
2188 struct halmac_rx_ignore_info rx_ignore_info;
2189 struct halmac_watcher watcher;
2190 #if HALMAC_PLATFORM_TESTPROGRAM
2191 struct halmisc_adapter *halmisc_adapter;
2192 #endif
2193 };
2194
2195 struct halmac_api {
2196 enum halmac_ret_status
2197 (*halmac_register_api)(struct halmac_adapter *adapter,
2198 struct halmac_api_registry *registry);
2199 enum halmac_ret_status
2200 (*halmac_mac_power_switch)(struct halmac_adapter *adapter,
2201 enum halmac_mac_power pwr);
2202 enum halmac_ret_status
2203 (*halmac_download_firmware)(struct halmac_adapter *adapter, u8 *fw_bin,
2204 u32 size);
2205 enum halmac_ret_status
2206 (*halmac_free_download_firmware)(struct halmac_adapter *adapter,
2207 enum halmac_dlfw_mem mem_sel,
2208 u8 *fw_bin, u32 size);
2209 enum halmac_ret_status
2210 (*halmac_reset_wifi_fw)(struct halmac_adapter *adapter);
2211 enum halmac_ret_status
2212 (*halmac_get_fw_version)(struct halmac_adapter *adapter,
2213 struct halmac_fw_version *ver);
2214 enum halmac_ret_status
2215 (*halmac_cfg_mac_addr)(struct halmac_adapter *adapter,
2216 u8 port, union halmac_wlan_addr *addr);
2217 enum halmac_ret_status
2218 (*halmac_cfg_bssid)(struct halmac_adapter *adapter, u8 port,
2219 union halmac_wlan_addr *addr);
2220 enum halmac_ret_status
2221 (*halmac_cfg_multicast_addr)(struct halmac_adapter *adapter,
2222 union halmac_wlan_addr *addr);
2223 enum halmac_ret_status
2224 (*halmac_pre_init_system_cfg)(struct halmac_adapter *adapter);
2225 enum halmac_ret_status
2226 (*halmac_init_system_cfg)(struct halmac_adapter *adapter);
2227 enum halmac_ret_status
2228 (*halmac_init_trx_cfg)(struct halmac_adapter *adapter,
2229 enum halmac_trx_mode mode);
2230 enum halmac_ret_status
2231 (*halmac_init_h2c)(struct halmac_adapter *adapter);
2232 enum halmac_ret_status
2233 (*halmac_cfg_rx_aggregation)(struct halmac_adapter *adapter,
2234 struct halmac_rxagg_cfg *cfg);
2235 enum halmac_ret_status
2236 (*halmac_init_protocol_cfg)(struct halmac_adapter *adapter);
2237 enum halmac_ret_status
2238 (*halmac_init_edca_cfg)(struct halmac_adapter *adapter);
2239 enum halmac_ret_status
2240 (*halmac_cfg_operation_mode)(struct halmac_adapter *adapter,
2241 enum halmac_wireless_mode mode);
2242 enum halmac_ret_status
2243 (*halmac_cfg_ch_bw)(struct halmac_adapter *adapter, u8 ch,
2244 enum halmac_pri_ch_idx idx, enum halmac_bw bw);
2245 enum halmac_ret_status
2246 (*halmac_cfg_bw)(struct halmac_adapter *adapter, enum halmac_bw bw);
2247 enum halmac_ret_status
2248 (*halmac_init_wmac_cfg)(struct halmac_adapter *adapter);
2249 enum halmac_ret_status
2250 (*halmac_init_mac_cfg)(struct halmac_adapter *adapter,
2251 enum halmac_trx_mode mode);
2252 enum halmac_ret_status
2253 (*halmac_init_interface_cfg)(struct halmac_adapter *adapter);
2254 enum halmac_ret_status
2255 (*halmac_deinit_interface_cfg)(struct halmac_adapter *adapter);
2256 enum halmac_ret_status
2257 (*halmac_init_sdio_cfg)(struct halmac_adapter *adapter);
2258 enum halmac_ret_status
2259 (*halmac_init_usb_cfg)(struct halmac_adapter *adapter);
2260 enum halmac_ret_status
2261 (*halmac_init_pcie_cfg)(struct halmac_adapter *adapter);
2262 enum halmac_ret_status
2263 (*halmac_deinit_sdio_cfg)(struct halmac_adapter *adapter);
2264 enum halmac_ret_status
2265 (*halmac_deinit_usb_cfg)(struct halmac_adapter *adapter);
2266 enum halmac_ret_status
2267 (*halmac_deinit_pcie_cfg)(struct halmac_adapter *adapter);
2268 enum halmac_ret_status
2269 (*halmac_get_efuse_size)(struct halmac_adapter *adapter, u32 *size);
2270 enum halmac_ret_status
2271 (*halmac_get_efuse_available_size)(struct halmac_adapter *adapter,
2272 u32 *size);
2273 enum halmac_ret_status
2274 (*halmac_dump_efuse_map)(struct halmac_adapter *adapter,
2275 enum halmac_efuse_read_cfg cfg);
2276 enum halmac_ret_status
2277 (*halmac_dump_efuse_map_bt)(struct halmac_adapter *adapter,
2278 enum halmac_efuse_bank bank, u32 size,
2279 u8 *map);
2280 enum halmac_ret_status
2281 (*halmac_write_efuse_bt)(struct halmac_adapter *adapter, u32 offset,
2282 u8 value, enum halmac_efuse_bank bank);
2283 enum halmac_ret_status
2284 (*halmac_read_efuse_bt)(struct halmac_adapter *adapter, u32 offset,
2285 u8 *value, enum halmac_efuse_bank bank);
2286 enum halmac_ret_status
2287 (*halmac_cfg_efuse_auto_check)(struct halmac_adapter *adapter,
2288 u8 enable);
2289 enum halmac_ret_status
2290 (*halmac_get_logical_efuse_size)(struct halmac_adapter *adapter,
2291 u32 *size);
2292 enum halmac_ret_status
2293 (*halmac_dump_logical_efuse_map)(struct halmac_adapter *adapter,
2294 enum halmac_efuse_read_cfg cfg);
2295 enum halmac_ret_status
2296 (*halmac_dump_logical_efuse_mask)(struct halmac_adapter *adapter,
2297 enum halmac_efuse_read_cfg cfg);
2298 enum halmac_ret_status
2299 (*halmac_write_logical_efuse)(struct halmac_adapter *adapter,
2300 u32 offset, u8 value);
2301 enum halmac_ret_status
2302 (*halmac_write_logical_efuse_word)(struct halmac_adapter *adapter,
2303 u32 offset, u16 value);
2304 enum halmac_ret_status
2305 (*halmac_read_logical_efuse)(struct halmac_adapter *adapter, u32 offset,
2306 u8 *value);
2307 enum halmac_ret_status
2308 (*halmac_pg_efuse_by_map)(struct halmac_adapter *adapter,
2309 struct halmac_pg_efuse_info *info,
2310 enum halmac_efuse_read_cfg cfg);
2311 enum halmac_ret_status
2312 (*halmac_mask_logical_efuse)(struct halmac_adapter *adapter,
2313 struct halmac_pg_efuse_info *info);
2314 enum halmac_ret_status
2315 (*halmac_get_c2h_info)(struct halmac_adapter *adapter, u8 *buf,
2316 u32 size);
2317 enum halmac_ret_status
2318 (*halmac_h2c_lb)(struct halmac_adapter *adapter);
2319 enum halmac_ret_status
2320 (*halmac_debug)(struct halmac_adapter *adapter);
2321 enum halmac_ret_status
2322 (*halmac_cfg_parameter)(struct halmac_adapter *adapter,
2323 struct halmac_phy_parameter_info *info,
2324 u8 full_fifo);
2325 enum halmac_ret_status
2326 (*halmac_update_packet)(struct halmac_adapter *adapter,
2327 enum halmac_packet_id pkt_id, u8 *pkt,
2328 u32 size);
2329 enum halmac_ret_status
2330 (*halmac_bcn_ie_filter)(struct halmac_adapter *adapter,
2331 struct halmac_bcn_ie_info *info);
2332 u8
2333 (*halmac_reg_read_8)(struct halmac_adapter *adapter, u32 offset);
2334 enum halmac_ret_status
2335 (*halmac_reg_write_8)(struct halmac_adapter *adapter, u32 offset,
2336 u8 value);
2337 u16
2338 (*halmac_reg_read_16)(struct halmac_adapter *adapter, u32 offset);
2339 enum halmac_ret_status
2340 (*halmac_reg_write_16)(struct halmac_adapter *adapter, u32 offset,
2341 u16 value);
2342 u32
2343 (*halmac_reg_read_32)(struct halmac_adapter *adapter, u32 offset);
2344 enum halmac_ret_status
2345 (*halmac_reg_write_32)(struct halmac_adapter *adapter, u32 offset,
2346 u32 value);
2347 u32
2348 (*halmac_reg_read_indirect_32)(struct halmac_adapter *adapter,
2349 u32 offset);
2350 enum halmac_ret_status
2351 (*halmac_reg_sdio_cmd53_read_n)(struct halmac_adapter *adapter,
2352 u32 offset, u32 size, u8 *value);
2353 enum halmac_ret_status
2354 (*halmac_tx_allowed_sdio)(struct halmac_adapter *adapter, u8 *buf,
2355 u32 size);
2356 enum halmac_ret_status
2357 (*halmac_set_bulkout_num)(struct halmac_adapter *adapter, u8 num);
2358 enum halmac_ret_status
2359 (*halmac_get_sdio_tx_addr)(struct halmac_adapter *adapter, u8 *buf,
2360 u32 size, u32 *cmd53_addr);
2361 enum halmac_ret_status
2362 (*halmac_get_usb_bulkout_id)(struct halmac_adapter *adapter, u8 *buf,
2363 u32 size, u8 *id);
2364 enum halmac_ret_status
2365 (*halmac_fill_txdesc_checksum)(struct halmac_adapter *adapter,
2366 u8 *txdesc);
2367 enum halmac_ret_status
2368 (*halmac_update_datapack)(struct halmac_adapter *adapter,
2369 enum halmac_data_type data_type,
2370 struct halmac_phy_parameter_info *info);
2371 enum halmac_ret_status
2372 (*halmac_run_datapack)(struct halmac_adapter *adapter,
2373 enum halmac_data_type data_type);
2374 enum halmac_ret_status
2375 (*halmac_cfg_drv_info)(struct halmac_adapter *adapter,
2376 enum halmac_drv_info drv_info);
2377 enum halmac_ret_status
2378 (*halmac_send_bt_coex)(struct halmac_adapter *adapter, u8 *buf,
2379 u32 size, u8 ack);
2380 enum halmac_ret_status
2381 (*halmac_verify_platform_api)(struct halmac_adapter *adapter);
2382 u32
2383 (*halmac_get_fifo_size)(struct halmac_adapter *adapter,
2384 enum hal_fifo_sel sel);
2385 enum halmac_ret_status
2386 (*halmac_dump_fifo)(struct halmac_adapter *adapter,
2387 enum hal_fifo_sel sel, u32 start_addr, u32 size,
2388 u8 *data);
2389 enum halmac_ret_status
2390 (*halmac_cfg_txbf)(struct halmac_adapter *adapter, u8 userid,
2391 enum halmac_bw bw, u8 txbf_en);
2392 enum halmac_ret_status
2393 (*halmac_cfg_mumimo)(struct halmac_adapter *adapter,
2394 struct halmac_cfg_mumimo_para *param);
2395 enum halmac_ret_status
2396 (*halmac_cfg_sounding)(struct halmac_adapter *adapter,
2397 enum halmac_snd_role role,
2398 enum halmac_data_rate rate);
2399 enum halmac_ret_status
2400 (*halmac_del_sounding)(struct halmac_adapter *adapter,
2401 enum halmac_snd_role role);
2402 enum halmac_ret_status
2403 (*halmac_su_bfer_entry_init)(struct halmac_adapter *adapter,
2404 struct halmac_su_bfer_init_para *param);
2405 enum halmac_ret_status
2406 (*halmac_su_bfee_entry_init)(struct halmac_adapter *adapter, u8 userid,
2407 u16 paid);
2408 enum halmac_ret_status
2409 (*halmac_mu_bfer_entry_init)(struct halmac_adapter *adapter,
2410 struct halmac_mu_bfer_init_para *param);
2411 enum halmac_ret_status
2412 (*halmac_mu_bfee_entry_init)(struct halmac_adapter *adapter,
2413 struct halmac_mu_bfee_init_para *param);
2414 enum halmac_ret_status
2415 (*halmac_su_bfer_entry_del)(struct halmac_adapter *adapter, u8 userid);
2416 enum halmac_ret_status
2417 (*halmac_su_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid);
2418 enum halmac_ret_status
2419 (*halmac_mu_bfer_entry_del)(struct halmac_adapter *adapter);
2420 enum halmac_ret_status
2421 (*halmac_mu_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid);
2422 enum halmac_ret_status
2423 (*halmac_add_ch_info)(struct halmac_adapter *adapter,
2424 struct halmac_ch_info *info);
2425 enum halmac_ret_status
2426 (*halmac_add_extra_ch_info)(struct halmac_adapter *adapter,
2427 struct halmac_ch_extra_info *info);
2428 enum halmac_ret_status
2429 (*halmac_ctrl_ch_switch)(struct halmac_adapter *adapter,
2430 struct halmac_ch_switch_option *opt);
2431 enum halmac_ret_status
2432 (*halmac_send_scan_packet)(struct halmac_adapter *adapter, u8 index,
2433 u8 *pkt, u32 size);
2434 enum halmac_ret_status
2435 (*halmac_drop_scan_packet)(struct halmac_adapter *adapter,
2436 struct halmac_drop_pkt_option *opt);
2437 enum halmac_ret_status
2438 (*halmac_p2pps)(struct halmac_adapter *adapter,
2439 struct halmac_p2pps *info);
2440 enum halmac_ret_status
2441 (*halmac_clear_ch_info)(struct halmac_adapter *adapter);
2442 enum halmac_ret_status
2443 (*halmac_send_general_info)(struct halmac_adapter *adapter,
2444 struct halmac_general_info *info);
2445 enum halmac_ret_status
2446 (*halmac_start_iqk)(struct halmac_adapter *adapter,
2447 struct halmac_iqk_para *param);
2448 enum halmac_ret_status
2449 (*halmac_start_dpk)(struct halmac_adapter *adapter);
2450 enum halmac_ret_status
2451 (*halmac_ctrl_pwr_tracking)(struct halmac_adapter *adapter,
2452 struct halmac_pwr_tracking_option *opt);
2453 enum halmac_ret_status
2454 (*halmac_psd)(struct halmac_adapter *adapter, u16 start_psd,
2455 u16 end_psd);
2456 enum halmac_ret_status
2457 (*halmac_cfg_tx_agg_align)(struct halmac_adapter *adapter, u8 enable,
2458 u16 align_size);
2459 enum halmac_ret_status
2460 (*halmac_query_status)(struct halmac_adapter *adapter,
2461 enum halmac_feature_id feature_id,
2462 enum halmac_cmd_process_status *proc_status,
2463 u8 *data, u32 *size);
2464 enum halmac_ret_status
2465 (*halmac_reset_feature)(struct halmac_adapter *adapter,
2466 enum halmac_feature_id feature_id);
2467 enum halmac_ret_status
2468 (*halmac_check_fw_status)(struct halmac_adapter *adapter,
2469 u8 *fw_status);
2470 enum halmac_ret_status
2471 (*halmac_dump_fw_dmem)(struct halmac_adapter *adapter, u8 *dmem,
2472 u32 *size);
2473 enum halmac_ret_status
2474 (*halmac_cfg_max_dl_size)(struct halmac_adapter *adapter, u32 size);
2475 enum halmac_ret_status
2476 (*halmac_cfg_la_mode)(struct halmac_adapter *adapter,
2477 enum halmac_la_mode mode);
2478 enum halmac_ret_status
2479 (*halmac_cfg_rxff_expand_mode)(struct halmac_adapter *adapter,
2480 enum halmac_rx_fifo_expanding_mode mode);
2481 enum halmac_ret_status
2482 (*halmac_config_security)(struct halmac_adapter *adapter,
2483 struct halmac_security_setting *setting);
2484 u8
2485 (*halmac_get_used_cam_entry_num)(struct halmac_adapter *adapter,
2486 enum hal_security_type sec_type);
2487 enum halmac_ret_status
2488 (*halmac_write_cam)(struct halmac_adapter *adapter, u32 idx,
2489 struct halmac_cam_entry_info *info);
2490 enum halmac_ret_status
2491 (*halmac_read_cam_entry)(struct halmac_adapter *adapter, u32 idx,
2492 struct halmac_cam_entry_format *content);
2493 enum halmac_ret_status
2494 (*halmac_clear_cam_entry)(struct halmac_adapter *adapter, u32 idx);
2495 enum halmac_ret_status
2496 (*halmac_get_hw_value)(struct halmac_adapter *adapter,
2497 enum halmac_hw_id hw_id, void *value);
2498 enum halmac_ret_status
2499 (*halmac_set_hw_value)(struct halmac_adapter *adapter,
2500 enum halmac_hw_id hw_id, void *value);
2501 enum halmac_ret_status
2502 (*halmac_cfg_drv_rsvd_pg_num)(struct halmac_adapter *adapter,
2503 enum halmac_drv_rsvd_pg_num pg_num);
2504 enum halmac_ret_status
2505 (*halmac_get_chip_version)(struct halmac_adapter *adapter,
2506 struct halmac_ver *ver);
2507 enum halmac_ret_status
2508 (*halmac_chk_txdesc)(struct halmac_adapter *adapter, u8 *buf, u32 size);
2509 enum halmac_ret_status
2510 (*halmac_dl_drv_rsvd_page)(struct halmac_adapter *adapter, u8 pg_offset,
2511 u8 *buf, u32 size);
2512 enum halmac_ret_status
2513 (*halmac_pcie_switch)(struct halmac_adapter *adapter,
2514 enum halmac_pcie_cfg cfg);
2515 enum halmac_ret_status
2516 (*halmac_phy_cfg)(struct halmac_adapter *adapter,
2517 enum halmac_intf_phy_platform pltfm);
2518 enum halmac_ret_status
2519 (*halmac_cfg_csi_rate)(struct halmac_adapter *adapter, u8 rssi,
2520 u8 cur_rate, u8 fixrate_en, u8 *new_rate,
2521 u8 *bmp_ofdm54);
2522 #if HALMAC_SDIO_SUPPORT
2523 enum halmac_ret_status
2524 (*halmac_sdio_cmd53_4byte)(struct halmac_adapter *adapter,
2525 enum halmac_sdio_cmd53_4byte_mode mode);
2526 enum halmac_ret_status
2527 (*halmac_sdio_hw_info)(struct halmac_adapter *adapter,
2528 struct halmac_sdio_hw_info *info);
2529 #endif
2530 enum halmac_ret_status
2531 (*halmac_cfg_transmitter_addr)(struct halmac_adapter *adapter, u8 port,
2532 union halmac_wlan_addr *addr);
2533 enum halmac_ret_status
2534 (*halmac_cfg_net_type)(struct halmac_adapter *adapter, u8 port,
2535 enum halmac_network_type_select net_type);
2536 enum halmac_ret_status
2537 (*halmac_cfg_tsf_rst)(struct halmac_adapter *adapter, u8 port);
2538 enum halmac_ret_status
2539 (*halmac_cfg_bcn_space)(struct halmac_adapter *adapter, u8 port,
2540 u32 bcn_space);
2541 enum halmac_ret_status
2542 (*halmac_rw_bcn_ctrl)(struct halmac_adapter *adapter, u8 port,
2543 u8 write_en, struct halmac_bcn_ctrl *ctrl);
2544 enum halmac_ret_status
2545 (*halmac_interface_integration_tuning)(struct halmac_adapter *adapter);
2546 enum halmac_ret_status
2547 (*halmac_txfifo_is_empty)(struct halmac_adapter *adapter, u32 chk_num);
2548 enum halmac_ret_status
2549 (*halmac_download_flash)(struct halmac_adapter *adapter, u8 *fw_bin,
2550 u32 size, u32 rom_addr);
2551 enum halmac_ret_status
2552 (*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr,
2553 u32 length, u8 *data);
2554 enum halmac_ret_status
2555 (*halmac_erase_flash)(struct halmac_adapter *adapter, u8 erase_cmd,
2556 u32 addr);
2557 enum halmac_ret_status
2558 (*halmac_check_flash)(struct halmac_adapter *adapter, u8 *fw_bin,
2559 u32 size, u32 addr);
2560 enum halmac_ret_status
2561 (*halmac_cfg_edca_para)(struct halmac_adapter *adapter,
2562 enum halmac_acq_id acq_id,
2563 struct halmac_edca_para *param);
2564 enum halmac_ret_status
2565 (*halmac_pinmux_get_func)(struct halmac_adapter *adapter,
2566 enum halmac_gpio_func gpio_func, u8 *enable);
2567 enum halmac_ret_status
2568 (*halmac_pinmux_set_func)(struct halmac_adapter *adapter,
2569 enum halmac_gpio_func gpio_func);
2570 enum halmac_ret_status
2571 (*halmac_pinmux_free_func)(struct halmac_adapter *adapter,
2572 enum halmac_gpio_func gpio_func);
2573 enum halmac_ret_status
2574 (*halmac_pinmux_wl_led_mode)(struct halmac_adapter *adapter,
2575 enum halmac_wlled_mode mode);
2576 void
2577 (*halmac_pinmux_wl_led_sw_ctrl)(struct halmac_adapter *adapter, u8 on);
2578 void
2579 (*halmac_pinmux_sdio_int_polarity)(struct halmac_adapter *adapter,
2580 u8 low_active);
2581 enum halmac_ret_status
2582 (*halmac_pinmux_gpio_mode)(struct halmac_adapter *adapter, u8 gpio_id,
2583 u8 output);
2584 enum halmac_ret_status
2585 (*halmac_pinmux_gpio_output)(struct halmac_adapter *adapter, u8 gpio_id,
2586 u8 high);
2587 enum halmac_ret_status
2588 (*halmac_pinmux_pin_status)(struct halmac_adapter *adapter, u8 pin_id,
2589 u8 *high);
2590 enum halmac_ret_status
2591 (*halmac_ofld_func_cfg)(struct halmac_adapter *adapter,
2592 struct halmac_ofld_func_info *info);
2593 enum halmac_ret_status
2594 (*halmac_rx_cut_amsdu_cfg)(struct halmac_adapter *adapter,
2595 struct halmac_cut_amsdu_cfg *cfg);
2596 enum halmac_ret_status
2597 (*halmac_fw_snding)(struct halmac_adapter *adapter,
2598 struct halmac_su_snding_info *su_info,
2599 struct halmac_mu_snding_info *mu_info, u8 period);
2600 enum halmac_ret_status
2601 (*halmac_get_mac_addr)(struct halmac_adapter *adapter, u8 port,
2602 union halmac_wlan_addr *addr);
2603 enum halmac_ret_status
2604 (*halmac_init_low_pwr)(struct halmac_adapter *adapter);
2605 enum halmac_ret_status
2606 (*halmac_enter_cpu_sleep_mode)(struct halmac_adapter *adapter);
2607 enum halmac_ret_status
2608 (*halmac_get_cpu_mode)(struct halmac_adapter *adapter,
2609 enum halmac_wlcpu_mode *mode);
2610 enum halmac_ret_status
2611 (*halmac_drv_fwctrl)(struct halmac_adapter *adapter, u8 *payload,
2612 u32 size, u8 ack);
2613 enum halmac_ret_status
2614 (*halmac_read_efuse)(struct halmac_adapter *adapter, u32 offset,
2615 u8 *value);
2616 enum halmac_ret_status
2617 (*halmac_write_efuse)(struct halmac_adapter *adapter, u32 offset,
2618 u8 value);
2619 enum halmac_ret_status
2620 (*halmac_write_wifi_phy_efuse)(struct halmac_adapter *adapter,
2621 u32 offset, u8 value);
2622 enum halmac_ret_status
2623 (*halmac_read_wifi_phy_efuse)(struct halmac_adapter *adapter,
2624 u32 offset, u32 size, u8 *value);
2625 #if HALMAC_PCIE_SUPPORT
2626 enum halmac_ret_status
2627 (*halmac_cfgspc_set_pcie)(struct halmac_adapter *adapter,
2628 struct halmac_pcie_cfgspc_param *param);
2629 #endif
2630 enum halmac_ret_status
2631 (*halmac_en_ref_autok_pcie)(struct halmac_adapter *adapter, u8 en);
2632 enum halmac_ret_status
2633 (*halmac_get_watcher)(struct halmac_adapter *adapter,
2634 enum halmac_watcher_sel sel, void *vlue);
2635 enum halmac_ret_status
2636 (*halmac_cfg_rf_pinmux)(struct halmac_adapter *adapter,
2637 u8 value);
2638 #if HALMAC_DBG_MONITOR_IO
2639 u8
2640 (*halmac_mon_reg_read_8)(struct halmac_adapter *adapter, u32 offset,
2641 const char *func, const u32 line);
2642 u16
2643 (*halmac_mon_reg_read_16)(struct halmac_adapter *adapter, u32 offset,
2644 const char *func, const u32 line);
2645 u32
2646 (*halmac_mon_reg_read_32)(struct halmac_adapter *adapter, u32 offset,
2647 const char *func, const u32 line);
2648 enum halmac_ret_status
2649 (*halmac_mon_reg_sdio_cmd53_read_n)(struct halmac_adapter *adapter,
2650 u32 offset, u32 size, u8 *value,
2651 const char *func, const u32 line);
2652 enum halmac_ret_status
2653 (*halmac_mon_reg_write_8)(struct halmac_adapter *adapter, u32 offset,
2654 u8 value, const char *func, const u32 line);
2655 enum halmac_ret_status
2656 (*halmac_mon_reg_write_16)(struct halmac_adapter *adapter, u32 offset,
2657 u16 value, const char *func, const u32 line);
2658 enum halmac_ret_status
2659 (*halmac_mon_reg_write_32)(struct halmac_adapter *adapter, u32 offset,
2660 u32 value, const char *func, const u32 line);
2661 #endif
2662 #if HALMAC_PLATFORM_TESTPROGRAM
2663 struct halmisc_api *halmisc_api;
2664 #endif
2665 };
2666
2667 #define HALMAC_GET_API(halmac_adapter) \
2668 ((struct halmac_api *)halmac_adapter->halmac_api)
2669
2670 static HALMAC_INLINE enum halmac_ret_status
halmac_fw_validate(struct halmac_adapter * adapter)2671 halmac_fw_validate(struct halmac_adapter *adapter)
2672 {
2673 if (adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE &&
2674 adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT)
2675 return HALMAC_RET_NO_DLFW;
2676
2677 return HALMAC_RET_SUCCESS;
2678 }
2679
2680 #endif
2681