1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HDMI_REG_DPHY_H__ 19 #define __HDMI_REG_DPHY_H__ 20 #include "hi_type.h" 21 22 typedef union { 23 struct { 24 unsigned int reg_set : 24; /* [23:0] */ 25 unsigned int reg_set_load : 1; /* [24] */ 26 unsigned int reg_sscfifo_tune_en : 1; /* [25] */ 27 unsigned int reg_sscfifo_depth_clr : 1; /* [26] */ 28 unsigned int reg_deep_color : 2; /* [28:27] */ 29 unsigned int reg_ssc_mode : 1; /* [29] */ 30 unsigned int reg_pllfbmash111_en : 1; /* [30] */ 31 unsigned int reg_sscin_bypass_en : 1; /* [31] */ 32 } bits; 33 unsigned int u32; 34 } hdmitx_inssc_set; 35 36 typedef union { 37 struct { 38 unsigned int reg_tune_step : 8; /* [7:0] */ 39 unsigned int reg_sscfifo_lower_thresh : 10; /* [17:8] */ 40 unsigned int reg_sscfifo_upper_thresh : 10; /* [27:18] */ 41 unsigned int reg_tune_reverse : 1; /* [28] */ 42 unsigned int reg_ssc_sync : 1; /* [29] */ 43 unsigned int rsv_0 : 2; /* [31:30] */ 44 } bits; 45 unsigned int u32; 46 } hdmitx_inssc_fifo; 47 48 typedef union { 49 struct { 50 unsigned int reg_step : 10; /* [9:0] */ 51 unsigned int reg_span : 14; /* [23:10] */ 52 unsigned int reg_testd : 8; /* [31:24] */ 53 } bits; 54 unsigned int u32; 55 } hdmitx_inssc_step; 56 57 typedef union { 58 struct { 59 unsigned int reg_tune_interval : 32; /* [31:0] */ 60 } bits; 61 unsigned int u32; 62 } hdmitx_inssc_tune; 63 64 typedef union { 65 struct { 66 unsigned int reg_dphy_srst_req : 1; /* [0] */ 67 unsigned int rsv_0 : 31; /* [31:1] */ 68 } bits; 69 unsigned int u32; 70 } hdmitx_dphy_rst; 71 72 typedef union { 73 struct { 74 unsigned int reg_dnum : 5; /* [4:0] */ 75 unsigned int reg_hkmash_en : 1; /* [5] */ 76 unsigned int reg_mash111_hk_sel : 1; /* [6] */ 77 unsigned int rsv_1 : 25; /* [31:7] */ 78 } bits; 79 unsigned int u32; 80 } hdmitx_ssc_hk; 81 82 typedef union { 83 struct { 84 unsigned int sscin_span_cnt : 15; /* [14:0] */ 85 unsigned int sscin_segment : 2; /* [16:15] */ 86 unsigned int sscin_stop_flag : 1; /* [17] */ 87 unsigned int sscin_reverse_flag : 1; /* [18] */ 88 unsigned int sscin_div : 5; /* [23:19] */ 89 unsigned int rsv_2 : 8; /* [31:24] */ 90 } bits; 91 unsigned int u32; 92 } hdmitx_sscin_status0; 93 94 typedef union { 95 struct { 96 unsigned int sscin_ssc_offset : 24; /* [23:0] */ 97 unsigned int rsv_3 : 8; /* [31:24] */ 98 } bits; 99 unsigned int u32; 100 } hdmitx_sscin_status1; 101 102 typedef union { 103 struct { 104 unsigned int sscin_sscfifo_depth_max : 10; /* [9:0] */ 105 unsigned int sscin_sscfifo_depth_min : 10; /* [19:10] */ 106 unsigned int rsv_4 : 12; /* [31:20] */ 107 } bits; 108 unsigned int u32; 109 } hdmitx_sscin_status2; 110 111 typedef union { 112 struct { 113 unsigned int sscfb_span_cnt : 15; /* [14:0] */ 114 unsigned int sscfb_segment : 2; /* [16:15] */ 115 unsigned int sscfb_stop_flag : 1; /* [17] */ 116 unsigned int sscfb_reverse_flag : 1; /* [18] */ 117 unsigned int sscfb_div : 5; /* [23:19] */ 118 unsigned int rsv_5 : 8; /* [31:24] */ 119 } bits; 120 unsigned int u32; 121 } hdmitx_sscfb_status0; 122 123 typedef union { 124 struct { 125 unsigned int sscfb_ssc_offset : 24; /* [23:0] */ 126 unsigned int rsv_6 : 8; /* [31:24] */ 127 } bits; 128 unsigned int u32; 129 } hdmitx_sscfb_status1; 130 131 typedef union { 132 struct { 133 unsigned int sscfb_sscfifo_depth_max : 10; /* [9:0] */ 134 unsigned int sscfb_sscfifo_depth_min : 10; /* [19:10] */ 135 unsigned int rsv_7 : 12; /* [31:20] */ 136 } bits; 137 unsigned int u32; 138 } hdmitx_sscfb_status2; 139 140 typedef union { 141 struct { 142 unsigned int fbmash_span_cnt : 15; /* [14:0] */ 143 unsigned int fbmash_segment : 2; /* [16:15] */ 144 unsigned int fbmash_stop_flag : 1; /* [17] */ 145 unsigned int fbmash_reverse_flag : 1; /* [18] */ 146 unsigned int fbmash_div : 5; /* [23:19] */ 147 unsigned int rsv_8 : 8; /* [31:24] */ 148 } bits; 149 unsigned int u32; 150 } hdmitx_sscfbmash111_status0; 151 152 typedef union { 153 struct { 154 unsigned int fbmash_ssc_offset : 24; /* [23:0] */ 155 unsigned int rsv_9 : 8; /* [31:24] */ 156 } bits; 157 unsigned int u32; 158 } hdmitx_sscfbmash111_status1; 159 160 typedef union { 161 struct { 162 unsigned int fbmash_sscfifo_depth_max : 10; /* [9:0] */ 163 unsigned int fbmash_sscfifo_depth_min : 10; /* [19:10] */ 164 unsigned int rsv_10 : 12; /* [31:20] */ 165 } bits; 166 unsigned int u32; 167 } hdmitx_sscfbmash111_status2; 168 169 typedef union { 170 struct { 171 unsigned int reg_aphy_data_ch0_h : 10; /* [9:0] */ 172 unsigned int reg_aphy_data_ch1_h : 10; /* [19:10] */ 173 unsigned int reg_aphy_data_ch2_h : 10; /* [29:20] */ 174 unsigned int rsv_11 : 2; /* [31:30] */ 175 } bits; 176 unsigned int u32; 177 } hdmitx_afifo_data_high; 178 179 typedef union { 180 struct { 181 unsigned int reg_txafifo_status_rst : 1; /* [0] */ 182 unsigned int reg_txafifo_rst : 1; /* [1] */ 183 unsigned int reg_aphy_data_ch0_sel : 1; /* [2] */ 184 unsigned int reg_aphy_data_ch1_sel : 1; /* [3] */ 185 unsigned int reg_aphy_data_ch2_sel : 1; /* [4] */ 186 unsigned int txafifo_aful_status : 1; /* [5] */ 187 unsigned int txafifo_full_status : 1; /* [6] */ 188 unsigned int txafifo_aempt_status : 1; /* [7] */ 189 unsigned int txafifo_empt_status : 1; /* [8] */ 190 unsigned int reg_aphy_data_clk_h : 10; /* [18:9] */ 191 unsigned int rsv_12 : 13; /* [31:19] */ 192 } bits; 193 unsigned int u32; 194 } hdmitx_afifo_data_sel; 195 196 typedef union { 197 struct { 198 unsigned int reg_aphy_data_clk_l : 30; /* [29:0] */ 199 unsigned int rsv_13 : 2; /* [31:30] */ 200 } bits; 201 unsigned int u32; 202 } hdmitx_afifo_clk; 203 204 typedef union { 205 struct { 206 unsigned int reg_aphy_data_ch0 : 10; /* [9:0] */ 207 unsigned int reg_aphy_data_ch1 : 10; /* [19:10] */ 208 unsigned int reg_aphy_data_ch2 : 10; /* [29:20] */ 209 unsigned int rsv_14 : 2; /* [31:30] */ 210 } bits; 211 unsigned int u32; 212 } hdmitx_afifo_data_low; 213 214 typedef union { 215 struct { 216 unsigned int reg_prbs7_en : 1; /* [0] */ 217 unsigned int reg_prbs7_clr : 1; /* [1] */ 218 unsigned int reg_prbs7_errinject : 1; /* [2] */ 219 unsigned int reg_ck_dataout_sel : 3; /* [5:3] */ 220 unsigned int reg_d0_dataout_sel : 3; /* [8:6] */ 221 unsigned int reg_d1_dataout_sel : 3; /* [11:9] */ 222 unsigned int reg_d2_dataout_sel : 3; /* [14:12] */ 223 unsigned int rsv_15 : 17; /* [31:15] */ 224 } bits; 225 unsigned int u32; 226 } hdmitx_afifo_channel; 227 228 typedef union { 229 struct { 230 unsigned int ad_rxsense : 1; /* [0] */ 231 unsigned int ad_txpll_hvflag : 1; /* [1] */ 232 unsigned int ad_txpll_lock : 1; /* [2] */ 233 unsigned int rsv_16 : 29; /* [31:3] */ 234 } bits; 235 unsigned int u32; 236 } aphy_status0; 237 238 typedef union { 239 struct { 240 unsigned int reg_gc_pd : 4; /* [3:0] */ 241 unsigned int reg_gc_pd_bist : 1; /* [4] */ 242 unsigned int reg_gc_pd_de : 4; /* [8:5] */ 243 unsigned int reg_gc_pd_ldo : 2; /* [10:9] */ 244 unsigned int reg_gc_pd_rterm : 8; /* [18:11] */ 245 unsigned int reg_gc_pd_rxsense : 1; /* [19] */ 246 unsigned int reg_gc_txpll_pd : 1; /* [20] */ 247 unsigned int reg_divsel : 2; /* [22:21] */ 248 unsigned int rsv_17 : 9; /* [31:23] */ 249 } bits; 250 unsigned int u32; 251 } aphy_top_pd; 252 253 typedef union { 254 struct { 255 unsigned int reg_isel_main_clk : 6; /* [5:0] */ 256 unsigned int reg_isel_main_d0 : 6; /* [11:6] */ 257 unsigned int reg_isel_main_d1 : 6; /* [17:12] */ 258 unsigned int reg_isel_main_d2 : 6; /* [23:18] */ 259 unsigned int reg_isel_main_de_clk : 6; /* [29:24] */ 260 unsigned int rsv_18 : 2; /* [31:30] */ 261 } bits; 262 unsigned int u32; 263 } aphy_driver_imain; 264 265 typedef union { 266 struct { 267 unsigned int reg_isel_main_de_d0 : 6; /* [5:0] */ 268 unsigned int reg_isel_main_de_d1 : 6; /* [11:6] */ 269 unsigned int reg_isel_main_de_d2 : 6; /* [17:12] */ 270 unsigned int reg_isel_pre_clk : 6; /* [23:18] */ 271 unsigned int reg_isel_pre_d0 : 6; /* [29:24] */ 272 unsigned int rsv_19 : 2; /* [31:30] */ 273 } bits; 274 unsigned int u32; 275 } aphy_driver_ipre; 276 277 typedef union { 278 struct { 279 unsigned int reg_isel_pre_d1 : 6; /* [5:0] */ 280 unsigned int reg_isel_pre_d2 : 6; /* [11:6] */ 281 unsigned int reg_isel_pre_de_clk : 6; /* [17:12] */ 282 unsigned int reg_isel_pre_de_d0 : 6; /* [23:18] */ 283 unsigned int reg_isel_pre_de_d1 : 6; /* [29:24] */ 284 unsigned int rsv_20 : 2; /* [31:30] */ 285 } bits; 286 unsigned int u32; 287 } aphy_driver_iprede; 288 289 typedef union { 290 struct { 291 unsigned int reg_isel_pre_de_d2 : 6; /* [5:0] */ 292 unsigned int reg_rsel_pre_clk : 3; /* [8:6] */ 293 unsigned int reg_rsel_pre_d0 : 3; /* [11:9] */ 294 unsigned int reg_rsel_pre_d1 : 3; /* [14:12] */ 295 unsigned int reg_rsel_pre_d2 : 3; /* [17:15] */ 296 unsigned int reg_rsel_pre_de_clk : 3; /* [20:18] */ 297 unsigned int reg_rsel_pre_de_d0 : 3; /* [23:21] */ 298 unsigned int reg_rsel_pre_de_d1 : 3; /* [26:24] */ 299 unsigned int reg_rsel_pre_de_d2 : 3; /* [29:27] */ 300 unsigned int rsv_21 : 2; /* [31:30] */ 301 } bits; 302 unsigned int u32; 303 } aphy_driver_rpre; 304 305 typedef union { 306 struct { 307 unsigned int reg_rt_clk : 8; /* [7:0] */ 308 unsigned int reg_rt_d0 : 8; /* [15:8] */ 309 unsigned int reg_rt_d1 : 8; /* [23:16] */ 310 unsigned int reg_rt_d2 : 8; /* [31:24] */ 311 } bits; 312 unsigned int u32; 313 } aphy_rterm_ctrl; 314 315 typedef union { 316 struct { 317 unsigned int reg_sel_ldo : 6; /* [5:0] */ 318 unsigned int reg_sel_rxsense : 3; /* [8:6] */ 319 unsigned int reg_sr_clk : 2; /* [10:9] */ 320 unsigned int rsv_22 : 21; /* [31:11] */ 321 } bits; 322 unsigned int u32; 323 } aphy_misc_ctrl; 324 325 typedef union { 326 struct { 327 unsigned int reg_test : 16; /* [15:0] */ 328 unsigned int reg_test_dc : 16; /* [31:16] */ 329 } bits; 330 unsigned int u32; 331 } aphy_test_ctrl; 332 333 typedef union { 334 struct { 335 unsigned int reg_txpll_clkin_sel : 2; /* [1:0] */ 336 unsigned int reg_txpll_divsel_in : 3; /* [4:2] */ 337 unsigned int reg_txpll_divsel_loop : 7; /* [11:5] */ 338 unsigned int reg_txpll_divsel_post : 2; /* [13:12] */ 339 unsigned int reg_txpll_icp_ictrl : 4; /* [17:14] */ 340 unsigned int reg_gc_txpll_en_ref_fb_div2 : 1; /* [18] */ 341 unsigned int reg_gc_txpll_en_sscdiv : 1; /* [19] */ 342 unsigned int rsv_23 : 12; /* [31:20] */ 343 } bits; 344 unsigned int u32; 345 } aphy_txpll_ctrl; 346 347 typedef union { 348 struct { 349 unsigned int reg_txpll_test : 20; /* [19:0] */ 350 unsigned int rsv_24 : 12; /* [31:20] */ 351 } bits; 352 unsigned int u32; 353 } aphy_txpll_test; 354 355 typedef union { 356 struct { 357 unsigned int reg_fb_div_sel : 2; /* [1:0] */ 358 unsigned int reg_fb_prd_sel : 2; /* [3:2] */ 359 unsigned int reg_ref_lock_timer : 8; /* [11:4] */ 360 unsigned int reg_ref_unlock_timer : 8; /* [19:12] */ 361 unsigned int reg_pll_lock_sel : 2; /* [21:20] */ 362 unsigned int reg_pll_unlock_sel : 1; /* [22] */ 363 unsigned int reg_pll_lockext_sel : 3; /* [25:23] */ 364 unsigned int reg_pll_lock_times : 1; /* [26] */ 365 unsigned int rsv_25 : 5; /* [31:27] */ 366 } bits; 367 unsigned int u32; 368 } pll_lock_ctrl; 369 370 typedef union { 371 struct { 372 unsigned int clk_fb_exist : 1; /* [0] */ 373 unsigned int pll_ena_edge : 1; /* [1] */ 374 unsigned int test_pll_cnt : 17; /* [18:2] */ 375 unsigned int pll_lock_oneshot : 1; /* [19] */ 376 unsigned int hdmi_clk_lock : 1; /* [20] */ 377 unsigned int rsv_26 : 11; /* [31:21] */ 378 } bits; 379 unsigned int u32; 380 } pll_lock_status; 381 382 typedef union { 383 struct { 384 unsigned int reg_txdphy_dummy_ctrl : 32; /* [31:0] */ 385 } bits; 386 unsigned int u32; 387 } reg_txdphy_dummy_ctrl; 388 389 typedef union { 390 struct { 391 unsigned int reg_set_fb : 24; /* [23:0] */ 392 unsigned int reg_set_load_fb : 1; /* [24] */ 393 unsigned int reg_sscfifo_tune_en_fb : 1; /* [25] */ 394 unsigned int reg_sscfifo_depth_clr_fb : 1; /* [26] */ 395 unsigned int reg_ssc_mode_fb : 1; /* [27] */ 396 unsigned int rsv_27 : 4; /* [31:28] */ 397 } bits; 398 unsigned int u32; 399 } hdmitx_fbssc_set; 400 401 typedef union { 402 struct { 403 unsigned int reg_tune_step_fb : 8; /* [7:0] */ 404 unsigned int reg_sscfifo_lower_thresh_fb : 10; /* [17:8] */ 405 unsigned int reg_sscfifo_upper_thresh_fb : 10; /* [27:18] */ 406 unsigned int reg_tune_reverse_fb : 1; /* [28] */ 407 unsigned int reg_ssc_sync_fb : 1; /* [29] */ 408 unsigned int rsv_28 : 2; /* [31:30] */ 409 } bits; 410 unsigned int u32; 411 } hdmitx_fbssc_fifo; 412 413 typedef union { 414 struct { 415 unsigned int reg_step_fb : 10; /* [9:0] */ 416 unsigned int reg_span_fb : 14; /* [23:10] */ 417 unsigned int reg_testd_fb : 8; /* [31:24] */ 418 } bits; 419 unsigned int u32; 420 } hdmitx_fbssc_step; 421 422 typedef union { 423 struct { 424 unsigned int reg_tune_interval_fb : 32; /* [31:0] */ 425 } bits; 426 unsigned int u32; 427 } hdmitx_fbssc_tune; 428 429 typedef struct { 430 volatile hdmitx_inssc_set ssc_in_set; /* 0 */ 431 volatile hdmitx_inssc_fifo ssc_in_fifo; /* 4 */ 432 volatile hdmitx_inssc_step ssc_in_step; /* 8 */ 433 volatile hdmitx_inssc_tune ssc_in_tune; /* C */ 434 volatile hdmitx_dphy_rst dphy_rst; /* 0x10 */ 435 volatile hdmitx_ssc_hk ssc_hk; /* 14 */ 436 volatile unsigned int reserved_1[2]; /* 0x18~0x1c */ 437 volatile hdmitx_sscin_status0 ssc_in_st0; /* 20 */ 438 volatile hdmitx_sscin_status1 ssc_in_st1; /* 24 */ 439 volatile hdmitx_sscin_status2 ssc_in_st2; /* 28 */ 440 volatile hdmitx_sscfb_status0 ssc_fb_st0; /* 2C */ 441 volatile hdmitx_sscfb_status1 ssc_fb_st1; /* 30 */ 442 volatile hdmitx_sscfb_status2 ssc_fb_st2; /* 34 */ 443 volatile hdmitx_sscfbmash111_status0 ssc_fb_mash111_st0; /* 38 */ 444 volatile hdmitx_sscfbmash111_status1 ssc_fb_mash111_st1; /* 3C */ 445 volatile hdmitx_sscfbmash111_status2 ssc_fb_mash111_st2; /* 40 */ 446 volatile unsigned int reserved_2[2]; /* 0x44~0x48 */ 447 volatile hdmitx_afifo_data_high afifo_data_high; /* 4C */ 448 volatile hdmitx_afifo_data_sel afifo_data_sel; /* 50 */ 449 volatile hdmitx_afifo_clk afifo_data_clk; /* 54 */ 450 volatile hdmitx_afifo_data_low afifo_data_low; /* 58 */ 451 volatile hdmitx_afifo_channel afifo_chn; /* 5C */ 452 volatile aphy_status0 aphy_st0; /* 60 */ 453 volatile aphy_top_pd aphy_top_misc_ctrl; /* 64 */ 454 volatile aphy_driver_imain aphy_imain; /* 68 */ 455 volatile aphy_driver_ipre aphy_ipre; /* 6C */ 456 volatile aphy_driver_iprede aphy_iprede; /* 70 */ 457 volatile aphy_driver_rpre aphy_rpre; /* 74 */ 458 volatile aphy_rterm_ctrl rterm_ctrl; /* 78 */ 459 volatile aphy_misc_ctrl misc_ctrl; /* 7C */ 460 volatile aphy_test_ctrl test_ctrl_aphy; /* 80 */ 461 volatile unsigned int reserved_3[2]; /* 0x84~0x88 */ 462 volatile aphy_txpll_ctrl txpll_ctrl; /* 8C */ 463 volatile aphy_txpll_test txpll_test; /* 90 */ 464 volatile pll_lock_ctrl lock_ctrl; /* 94 */ 465 volatile pll_lock_status lock_st; /* 98 */ 466 volatile reg_txdphy_dummy_ctrl dphy_dummy_ctrl; /* 9C */ 467 volatile unsigned int reserved_4[4]; /* 0xa0~0xac */ 468 volatile hdmitx_fbssc_set fb_ssc_set; /* B0 */ 469 volatile hdmitx_fbssc_fifo fb_ssc_fifo; /* B4 */ 470 volatile hdmitx_fbssc_step fb_ssc_step; /* B8 */ 471 volatile hdmitx_fbssc_tune fb_ssc_tune; /* 0xbc */ 472 } hdmi2tx_dphy_reg_type; 473 474 hi_s32 hdmi_reg_tx_phy_init(hi_char *addr); 475 hi_s32 hdmi_reg_tx_phy_deinit(hi_void); 476 hi_s32 hdmi_reg_pllfbmash111_en_set(hi_u32 reg_pllfbmash111_en); 477 hi_s32 hdmi_reg_sscin_bypass_en_set(hi_u32 reg_sscin_bypass_en); 478 hi_s32 hdmi_reg_dphy_rst_set(hi_u32 reg_rst); 479 hi_s32 hdmi_reg_aphy_data_clk_height_set(hi_u32 reg_aphy_data_clk_h); 480 hi_s32 hdmi_reg_aphy_data_clk_low_set(hi_u32 reg_aphy_data_clk_l); 481 hi_s32 hdmi_reg_gc_pd_set(hi_u32 reg_gc_pd); 482 hi_u32 hdmi_reg_gc_pd_get(hi_void); 483 hi_s32 hdmi_reg_gc_pd_bist_set(hi_u32 reg_gc_pd_bist); 484 hi_u32 hdmi_reg_gc_pd_bist_get(hi_void); 485 hi_s32 hdmi_reg_gc_pd_de_set(hi_u32 reg_gc_pd_de); 486 hi_u32 hdmi_reg_gc_pd_de_get(hi_void); 487 hi_s32 hdmi_reg_gc_pd_ldo_set(hi_u32 reg_gc_pd_ldo); 488 hi_u32 hdmi_reg_gc_pd_ldo_get(hi_void); 489 hi_u32 hdmi_reg_gc_pd_rterm_get(hi_void); 490 hi_s32 hdmi_reg_gc_pd_rterm_set(hi_u32 reg_gc_pd_rterm); 491 hi_s32 hdmi_reg_gc_pd_rxsense_set(hi_u32 reg_gc_pd_rxsense); 492 hi_u32 hdmi_reg_gc_pd_rxsense_get(hi_void); 493 hi_s32 hdmi_reg_gc_txpll_pd_set(hi_u32 reg_gc_txpll_pd); 494 hi_u32 hdmi_reg_gc_txpll_pd_get(hi_void); 495 hi_s32 hdmi_reg_divsel_set(hi_u32 reg_divsel); 496 hi_s32 hdmi_reg_isel_main_clk_set(hi_u32 reg_isel_main_clk); 497 hi_s32 hdmi_reg_isel_main_d0_set(hi_u32 reg_isel_main_d0); 498 hi_s32 hdmi_reg_isel_main_d1_set(hi_u32 reg_isel_main_d1); 499 hi_s32 hdmi_reg_isel_main_d2_set(hi_u32 reg_isel_main_d2); 500 hi_s32 hdmi_reg_isel_main_de_clk_set(hi_u32 reg_isel_main_de_clk); 501 hi_u32 hdmi_reg_isel_main_de_clk_get(hi_void); 502 hi_s32 hdmi_reg_isel_main_de_d0_set(hi_u32 reg_isel_main_de_d0); 503 hi_u32 hdmi_reg_isel_main_de_d0_get(hi_void); 504 hi_s32 hdmi_reg_isel_main_de_d1_set(hi_u32 reg_isel_main_de_d1); 505 hi_u32 hdmi_reg_isel_main_de_d1_get(hi_void); 506 hi_s32 hdmi_reg_isel_main_de_d2_set(hi_u32 reg_isel_main_de_d2); 507 hi_u32 hdmi_reg_isel_main_de_d2_get(hi_void); 508 hi_s32 hdmi_reg_isel_pre_clk_set(hi_u32 reg_isel_pre_clk); 509 hi_s32 hdmi_reg_isel_pre_d0_set(hi_u32 reg_isel_pre_d0); 510 hi_s32 hdmi_reg_isel_pre_d1_set(hi_u32 reg_isel_pre_d1); 511 hi_s32 hdmi_reg_isel_pre_d2_set(hi_u32 reg_isel_pre_d2); 512 hi_s32 hdmi_reg_isel_pre_de_clk_set(hi_u32 reg_isel_pre_de_clk); 513 hi_s32 hdmi_reg_isel_pre_de_d0_set(hi_u32 reg_isel_pre_de_d0); 514 hi_s32 hdmi_reg_isel_pre_de_d1_set(hi_u32 reg_isel_pre_de_d1); 515 hi_s32 hdmi_reg_isel_pre_de_d2_set(hi_u32 reg_isel_pre_de_d2); 516 hi_s32 hdmi_reg_rsel_pre_clk_set(hi_u32 reg_rsel_pre_clk); 517 hi_s32 hdmi_reg_rsel_pre_d0_set(hi_u32 reg_rsel_pre_d0); 518 hi_s32 hdmi_reg_rsel_pre_d1_set(hi_u32 reg_rsel_pre_d1); 519 hi_s32 hdmi_reg_rsel_pre_d2_set(hi_u32 reg_rsel_pre_d2); 520 hi_s32 hdmi_reg_rsel_pre_de_clk_set(hi_u32 reg_rsel_pre_de_clk); 521 hi_s32 hdmi_reg_rsel_pre_de_d0_set(hi_u32 reg_rsel_pre_de_d0); 522 hi_s32 hdmi_reg_rsel_pre_de_d1_set(hi_u32 reg_rsel_pre_de_d1); 523 hi_s32 hdmi_reg_rsel_pre_de_d2_set(hi_u32 reg_rsel_pre_de_d2); 524 hi_s32 hdmi_reg_rt_clk_set(hi_u32 reg_rt_clk); 525 hi_s32 hdmi_reg_rt_d0_set(hi_u32 reg_rt_d0); 526 hi_s32 hdmi_reg_rt_d1_set(hi_u32 reg_rt_d1); 527 hi_s32 hdmi_reg_rt_d2_set(hi_u32 reg_rt_d2); 528 hi_s32 hdmi_reg_txpll_divsel_loop_set(hi_u32 reg_txpll_divsel_loop); 529 hi_s32 hdmi_reg_txpll_icp_ictrl_set(hi_u32 reg_txpll_icp_ictrl); 530 hi_s32 hdmi_reg_gc_txpll_en_sscdiv_set(hi_u32 reg_gc_txpll_en_sscdiv); 531 hi_s32 hdmi_reg_gc_txpll_test_set(hi_u32 reg_txpll_test); 532 hi_s32 hdmi_reg_fb_set(hi_u32 reg_set_fb); 533 hi_s32 hdmi_reg_load_fb_set(hi_u32 reg_set_load_fb); 534 hi_s32 hdmi_reg_ssc_mode_fb_set(hi_u32 reg_ssc_mode_fb); 535 hi_s32 hdmi_reg_step_fb_set(hi_u32 reg_step_fb); 536 hi_u32 hdmi_reg_step_fb_get(hi_void); 537 hi_s32 hdmi_reg_span_fb_set(hi_u32 reg_span_fb); 538 hi_u32 hdmi_reg_span_fb_get(hi_void); 539 hi_u32 hdmi_reg_isel_main_clk_get(hi_void); 540 hi_u32 hdmi_reg_isel_main_d0_get(hi_void); 541 hi_s32 hdmi_reg_test_set(hi_u32 reg_test); 542 hi_u32 hdmi_reg_rsel_pre_d0_get(hi_void); 543 hi_u32 hdmi_reg_rsel_pre_clk_get(hi_void); 544 545 #endif /* __HDMI_REG_DPHY_H__ */ 546 547