1 /* 2 * Copyright (c) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef HI_GO_SURFACE_H 17 #define HI_GO_SURFACE_H 18 19 #include "hi_go_comm.h" 20 21 #ifdef __cplusplus 22 #if __cplusplus 23 extern "C" { 24 #endif /* __cplusplus */ 25 #endif /* __cplusplus */ 26 27 typedef enum { 28 HIGO_PF_CLUT8 = 0, /* Palette */ 29 HIGO_PF_CLUT1, 30 HIGO_PF_CLUT4, 31 HIGO_PF_4444, /* 32 * Each pixel occupies 16 bits, and the A/R/G/B components each occupies 4 bits. They are sorted 33 * by address in descending order. 34 * 35 */ 36 HIGO_PF_0444, /* 37 * Each pixel occupies 16 bits, and the A/R/G/B components each occupies 4 bits. They are sorted 38 * by address in descending order. The A component does not take effect. 39 * ռ16bitARGBÿռ4bitַɸ, A 40 */ 41 42 HIGO_PF_1555, /* 43 * Each pixel occupies 16 bits, the R/G/B components each occupies 5 bits, and the A component 44 * occupies 1 bit. They are sorted by address in descending order. 45 * 16bitRGBÿռ5bitA1bitַɸ 46 */ 47 HIGO_PF_0555, /* 48 * Each pixel occupies 16 bits, the R/G/B components each occupies 5 bits, and the A component 49 * occupies 1 bit. They are sorted by address in descending order. The A component does not take 50 * effect. 51 * A 52 */ 53 HIGO_PF_565, /* 54 * Each pixel occupies 16 bits, and the R/G/B components each occupies 5 bits, 6 bits, and 5 bits 55 * respectively. They are sorted by address in descending order. 56 * 16bitRGBÿֱռ5bit6bit5bitַɸ 57 */ 58 HIGO_PF_8565, /* 59 * Each pixel occupies 24 bits, and the A/R/G/B components each occupies 8 bits, 5 bits, 6 bits, 60 * and 5 bits respectively. They are sorted by address in descending order. 61 * ռ24bitARGBÿֱռ8bit, 5bit6bit5bitַɸ 62 */ 63 HIGO_PF_8888, /* 64 * Each pixel occupies 32 bits, and the A/R/G/B components each occupies 8 bits. They are sorted 65 * by address in descending order. 66 * 67 */ 68 HIGO_PF_0888, /* 69 * Each pixel occupies 24 bits, and the A/R/G/B components each occupies 8 bits. They are sorted 70 * by address in descending order. The A component does not take effect. 71 * ռ24bitARGBÿռ8bitַɸУA 72 */ 73 74 HIGO_PF_YUV400, /* 75 * Semi-planar YUV 400 format defined by HiSilicon 76 * YUV 400ʽ 77 */ 78 HIGO_PF_YUV420, /* 79 * Semi-planar YUV 420 format defined by HiSilicon 80 * YUV 420ʽ 81 */ 82 HIGO_PF_YUV422, /* 83 * Semi-planar YUV 422 format and horizontal sampling format defined by 84 * 85 */ 86 HIGO_PF_YUV422_V, /* 87 * Semi-planar YUV 422 format and vertical sampling format defined by 88 * 89 */ 90 HIGO_PF_YUV444, /* 91 * Semi-planar YUV 444 format defined by HiSilicon, 92 * ˼semi-planar YUV 444ʽ 93 */ 94 95 HIGO_PF_A1, 96 HIGO_PF_A8, 97 98 HIGO_PF_YUV888, 99 HIGO_PF_YUV8888, 100 HIGO_PF_RLE8, 101 HIGO_PF_BUTT 102 } HIGO_PF_E; 103 104 /* Component type */ 105 /* */ 106 typedef enum { 107 HIGO_PDFORMAT_RGB = 0, 108 HIGO_PDFORMAT_RGB_PM, /* pre-multiplied */ 109 HIGO_PDFORMAT_Y, 110 HIGO_PDFORMAT_UV, 111 HIGO_PDFORMAT_UV_LE, 112 113 HIGO_PDFORMAT_BUTT 114 } HIGO_PDFORMAT_E; 115 116 typedef struct { 117 HIGO_PDFORMAT_E Format; /* Component type */ 118 HI_VOID *pData; /* Pointer to the virtual address of a component */ 119 HI_VOID *pPhyData; /* Pointer to the physical address of a component */ 120 HI_U32 Pitch; /* Component pitch */ 121 HI_U32 Bpp; /* Bytes per pixel */ 122 HI_U32 Offset; 123 } HIGO_PIXELDATA_S; 124 125 /* Maximum number of data components */ 126 /* */ 127 #define MAX_PARTPIXELDATA 3 128 129 /* The following sync modes can be used together. The non-automatic sync mode is also available. */ 130 /* */ 131 typedef enum { 132 HIGO_SYNC_MODE_CPU = 0x01, /* Sync mode. In this mode, CPU operations are required. */ 133 /* */ 134 HIGO_SYNC_MODE_TDE = 0x02, /* Sync mode. In this mode, the 2D acceleration operation is required. */ 135 /* */ 136 HIGO_SYNC_MODE_BUTT, 137 } HIGO_SYNC_MODE_E; 138 139 typedef enum { 140 HIGO_MEMTYPE_MMZ = 0, /* The memory is an media memory zone (MMZ) memory. */ 141 HIGO_MEMTYPE_OS, /* The memory is an operating system (OS) memory. */ 142 HIGO_MEMTYPE_BUTT 143 }HIGO_MEMTYPE_E; 144 145 typedef enum { 146 HIGO_OWNER_USER = 0, /* The memory is managed by users. the memory is allocated and destroyed by users. 147 * 148 */ 149 HIGO_OWNER_HIGO, /* 150 * The memory is managed by the HiGo module rather than users. 151 * 152 */ 153 HIGO_OWNER_BUTT 154 }HIGO_OWNER_E; 155 156 typedef struct { 157 HI_S32 Width; /* Surface width */ 158 HI_S32 Height; /* Surface height */ 159 HIGO_PF_E PixelFormat; /* Pixel format of a surface */ 160 HI_U32 Pitch[MAX_PARTPIXELDATA]; /* Pitch of a surface */ 161 HI_CHAR* pPhyAddr[MAX_PARTPIXELDATA]; /* Physical address of a surface */ 162 HI_CHAR* pVirAddr[MAX_PARTPIXELDATA]; /* Virtual address of a surface */ 163 HIGO_MEMTYPE_E MemType; /* Type of the surface memory */ 164 HI_BOOL bPubPalette; /* 165 * Use common Palette or not 166 * ֻClutʽЧ.ʹùĵɫ,ʹԴĵɫ 167 */ 168 }HIGO_SURINFO_S; 169 170 typedef struct { 171 HI_S32 Width; /* Surface width */ 172 HI_S32 Height; /* Surface height */ 173 HIGO_PF_E PixelFormat; /* Pixel format of a surface */ 174 175 /* 176 * Pitch of a surface 177 * Pitch[0] indicates the pitch in RGB format or the pitch of the Y component in semi-planar format. 178 * Pitch[1] indicates the pitch of the C component in semi-planar format. 179 * Pitch[2] is reserved. 180 */ 181 /* 182 * 183 * Pitch[0]ʾRGBʽм࣬ Semi-plannerYм 184 * Pitch[1]ʾSemi-plannerCм 185 * Pitch[2]ʱʹ 186 */ 187 HI_U32 Pitch[MAX_PARTPIXELDATA]; 188 189 /* 190 * Physical address of a surface 191 * pPhyAddr[0] indicates the physical address in RGB format or the physical address of the Y component in 192 * semi-planar format. 193 * pPhyAddr[1] indicates the physical address of the C component in semi-planar format. 194 */ 195 /* 196 * 197 * pPhyAddr[0]ʾRGBʽַ Semi-plannerYַ 198 * pPhyAddr[1]ʾSemi-plannerCַ 199 */ 200 HI_CHAR* pPhyAddr[MAX_PARTPIXELDATA]; 201 202 /* 203 * Virtual address of a surface 204 * pVirAddr[0] indicates the virtual address in RGB format or the virtual address of the Y component in semi-planar 205 * format. 206 * pVirAddr[1] indicates the virtual address of the C component in semi-planar format. 207 */ 208 /* 209 * 210 * pVirAddr[0]ʾRGBʽַ Semi-plannerYַ 211 * pVirAddr[1]ʾSemi-plannerCַ 212 */ 213 HI_CHAR* pVirAddr[MAX_PARTPIXELDATA]; /* 214 * 215 * pVirAddr[0]ʾRGBʽַ Semi-plannerYַ 216 * pVirAddr[1]ʾSemi-plannerCַ 217 */ 218 HIGO_MEMTYPE_E MemType; /* Type of the surface memory */ 219 HI_BOOL bPubPalette; /* Use common Palette or not */ 220 HIGO_OWNER_E MemOwner; /* Memory source. For example, the memory is allocated by users or the HiGo module. */ 221 /* */ 222 }HIGO_SURINFOEX_S; 223 224 /* Data component structure */ 225 /* */ 226 typedef HIGO_PIXELDATA_S HI_PIXELDATA[MAX_PARTPIXELDATA]; 227 228 HI_S32 HI_GO_InitSurface(HI_VOID); 229 230 HI_S32 HI_GO_DeinitSurface(HI_VOID); 231 232 HI_S32 HI_GO_SetSurfaceAlpha(HI_HANDLE Surface, HI_U8 Alpha); 233 234 HI_S32 HI_GO_GetSurfaceAlpha(HI_HANDLE Surface, HI_U8 *pAlpha); 235 236 HI_S32 HI_GO_EnableSurfaceColorKey(HI_HANDLE Surface, HI_BOOL Enable); 237 238 HI_S32 HI_GO_SetSurfaceColorKey(HI_HANDLE Surface, HI_COLOR ColorKey); 239 240 HI_S32 HI_GO_GetSurfaceColorKey(HI_HANDLE Surface, HI_COLOR *pColorKey); 241 242 HI_S32 HI_GO_SetSurfacePalette(HI_HANDLE Surface, const HI_PALETTE Palette); 243 244 HI_S32 HI_GO_GetSurfacePalette(HI_HANDLE Surface, HI_PALETTE Palette); 245 246 HI_S32 HI_GO_LockSurface(HI_HANDLE Surface, HI_PIXELDATA pData, HI_BOOL bSync); 247 248 HI_S32 HI_GO_UnlockSurface(HI_HANDLE Surface); 249 250 HI_S32 HI_GO_GetSurfaceSize(HI_HANDLE Surface, HI_S32 *pWidth, HI_S32 *pHeight); 251 252 HI_S32 HI_GO_GetSurfacePixelFormat(HI_HANDLE Surface, HIGO_PF_E *pPixelFormat); 253 254 HI_S32 HI_GO_CreateSurfaceFromMem(const HIGO_SURINFO_S *pSurInfo, HI_HANDLE *pSurface); 255 256 HI_S32 HI_GO_CreateSurface(HI_S32 Width, HI_S32 Height, HIGO_PF_E PixelFormat, HI_HANDLE *pSurface); 257 258 HI_S32 HI_GO_CreateSubSurface(HI_HANDLE Surface, const HI_RECT *pRect, HI_HANDLE *pSubSurface); 259 260 HI_S32 HI_GO_FreeSurface(HI_HANDLE Surface); 261 262 HI_S32 HI_GO_EnableSurfaceAutoSync(HI_HANDLE hSurface, HI_BOOL bAutoSync); 263 264 HI_S32 HI_GO_SyncSurface(HI_HANDLE hSurface, HIGO_SYNC_MODE_E mode); 265 266 HI_S32 HI_GO_SetSurfaceName(HI_HANDLE hSurface, const HI_CHAR *pName); 267 268 HI_S32 HI_GO_GetSurfaceName(HI_HANDLE hSurface, HI_CHAR *pNameBuf, HI_U32 BufLen); 269 270 HI_S32 HI_GO_GetSurfaceMemType(HI_HANDLE Surface, HIGO_MEMTYPE_E *pMemType); 271 272 HI_S32 HI_GO_GetSurfaceOwner(HI_HANDLE Surface, HIGO_OWNER_E *pOwner); 273 274 HI_S32 HI_GO_CreateSurfaceEx(const HIGO_SURINFOEX_S *pSurInfo, HI_HANDLE *pSurface); 275 276 HI_S32 HI_GO_SetPubPalette(const HI_PALETTE Palette); 277 278 HI_S32 HI_GO_GetPubPalette(HI_PALETTE Palette); 279 280 HI_S32 HI_GO_SetSurfaceClipRgn(HI_HANDLE Surface, const HI_REGION *pRegion, HI_U32 u32Num); 281 282 HI_S32 HI_GO_GetSurfaceClipRgn(HI_HANDLE Surface, HI_REGION **ppRegion, HI_U32 *pu32Num); 283 284 HI_S32 HI_GO_SetSurfaceClipRect(HI_HANDLE hSurface, const HI_RECT *pRect); 285 286 #ifdef __cplusplus 287 #if __cplusplus 288 } 289 #endif 290 #endif 291 292 #endif /* HI_GO_SURFACE_H */ 293