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1 /*
2  * Copyright (c) 2021-2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_CONCTL_H
10 #define HPM_CONCTL_H
11 
12 typedef struct {
13     __RW uint32_t CTRL0;                       /* 0x0:  */
14     __R  uint8_t  RESERVED0[4];                /* 0x4 - 0x7: Reserved */
15     __RW uint32_t CTRL2;                       /* 0x8:  */
16     __RW uint32_t CTRL3;                       /* 0xC:  */
17     __RW uint32_t CTRL4;                       /* 0x10:  */
18     __RW uint32_t CTRL5;                       /* 0x14:  */
19 } CONCTL_Type;
20 
21 
22 /* Bitfield definition for register: CTRL0 */
23 /*
24  * ENET1_RXCLK_DLY_SEL (RW)
25  *
26  */
27 #define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK (0xF8000UL)
28 #define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT (15U)
29 #define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK)
30 #define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT)
31 
32 /*
33  * ENET1_TXCLK_DLY_SEL (RW)
34  *
35  */
36 #define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK (0x7C00U)
37 #define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT (10U)
38 #define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK)
39 #define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT)
40 
41 /*
42  * ENET0_RXCLK_DLY_SEL (RW)
43  *
44  */
45 #define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3E0U)
46 #define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (5U)
47 #define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK)
48 #define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT)
49 
50 /*
51  * ENET0_TXCLK_DLY_SEL (RW)
52  *
53  */
54 #define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x1FU)
55 #define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U)
56 #define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK)
57 #define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT)
58 
59 /* Bitfield definition for register: CTRL2 */
60 /*
61  * ENET0_LPI_IRQ_EN (RW)
62  *
63  * ENET0 LPI IRQ Enable
64  */
65 #define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL)
66 #define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U)
67 #define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK)
68 #define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT)
69 
70 /*
71  * ENET0_REFCLK_OE (RW)
72  *
73  */
74 #define CONCTL_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL)
75 #define CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT (19U)
76 #define CONCTL_CTRL2_ENET0_REFCLK_OE_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK)
77 #define CONCTL_CTRL2_ENET0_REFCLK_OE_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK) >> CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT)
78 
79 /*
80  * ENET0_PHY_INTF_SEL (RW)
81  *
82  * 000:Reserved
83  * 001:RGMII
84  * 100:RMII
85  * 111:Reserved
86  */
87 #define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK (0xE000U)
88 #define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT (13U)
89 #define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK)
90 #define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK) >> CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT)
91 
92 /*
93  * ENET0_FLOWCTRL (RW)
94  *
95  */
96 #define CONCTL_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U)
97 #define CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT (12U)
98 #define CONCTL_CTRL2_ENET0_FLOWCTRL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK)
99 #define CONCTL_CTRL2_ENET0_FLOWCTRL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK) >> CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT)
100 
101 /*
102  * ENET0_RMII_TXCLK_SEL (RW)
103  *
104  * default to use internal clk.
105  * set from pad， two option here:
106  *   internal 50MHz clock out to pad then in;
107  *   use external clock;
108  */
109 #define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U)
110 #define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U)
111 #define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK)
112 #define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT)
113 
114 /* Bitfield definition for register: CTRL3 */
115 /*
116  * ENET1_LPI_IRQ_EN (RW)
117  *
118  * ENET1 LPI Interrupt Enable
119  */
120 #define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK (0x20000000UL)
121 #define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT (29U)
122 #define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK)
123 #define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK) >> CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT)
124 
125 /*
126  * ENET1_REFCLK_OE (RW)
127  *
128  */
129 #define CONCTL_CTRL3_ENET1_REFCLK_OE_MASK (0x80000UL)
130 #define CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT (19U)
131 #define CONCTL_CTRL3_ENET1_REFCLK_OE_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK)
132 #define CONCTL_CTRL3_ENET1_REFCLK_OE_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK) >> CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT)
133 
134 /*
135  * ENET1_PHY_INTF_SEL (RW)
136  *
137  */
138 #define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK (0xE000U)
139 #define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT (13U)
140 #define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK)
141 #define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK) >> CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT)
142 
143 /*
144  * ENET1_FLOWCTRL (RW)
145  *
146  */
147 #define CONCTL_CTRL3_ENET1_FLOWCTRL_MASK (0x1000U)
148 #define CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT (12U)
149 #define CONCTL_CTRL3_ENET1_FLOWCTRL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK)
150 #define CONCTL_CTRL3_ENET1_FLOWCTRL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK) >> CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT)
151 
152 /*
153  * ENET1_RMII_TXCLK_SEL (RW)
154  *
155  */
156 #define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK (0x400U)
157 #define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT (10U)
158 #define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK)
159 #define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT)
160 
161 /* Bitfield definition for register: CTRL4 */
162 /*
163  * SDXC0_SYS_IRQ_EN (RW)
164  *
165  * system irq enable
166  */
167 #define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK (0x80000000UL)
168 #define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT (31U)
169 #define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK)
170 #define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT)
171 
172 /*
173  * SDXC0_WKP_IRQ_EN (RW)
174  *
175  * wakeup irq enable
176  */
177 #define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK (0x40000000UL)
178 #define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT (30U)
179 #define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK)
180 #define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT)
181 
182 /*
183  * SDXC0_CARDCLK_INV_EN (RW)
184  *
185  * card clock inverter enable
186  */
187 #define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK (0x10000000UL)
188 #define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT (28U)
189 #define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK)
190 #define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT)
191 
192 /*
193  * SDXC0_GPR_TUNING_CARD_CLK_SEL (RW)
194  *
195  * for card clock DLL, default 0
196  */
197 #define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK (0xF800000UL)
198 #define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT (23U)
199 #define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK)
200 #define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT)
201 
202 /*
203  * SDXC0_GPR_TUNING_STROBE_SEL (RW)
204  *
205  * for strobe DLL, default 7taps(1ns)
206  */
207 #define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK (0x7C0000UL)
208 #define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT (18U)
209 #define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK)
210 #define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT)
211 
212 /*
213  * SDXC0_GPR_STROBE_IN_ENABLE (RW)
214  *
215  * enable strobe clock, maybe used when update strobe DLL
216  */
217 #define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK (0x20000UL)
218 #define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT (17U)
219 #define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK)
220 #define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT)
221 
222 /*
223  * SDXC0_GPR_CCLK_RX_DLY_SW_SEL (RW)
224  *
225  */
226 #define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK (0x1F000UL)
227 #define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT (12U)
228 #define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK)
229 #define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT)
230 
231 /*
232  * SDXC0_GPR_CCLK_RX_DLY_SW_FORCE (RW)
233  *
234  * force use sw DLL config
235  */
236 #define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK (0x800U)
237 #define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT (11U)
238 #define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK)
239 #define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT)
240 
241 /* Bitfield definition for register: CTRL5 */
242 /*
243  * SDXC1_SYS_IRQ_EN (RW)
244  *
245  * system irq enable
246  */
247 #define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK (0x80000000UL)
248 #define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT (31U)
249 #define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK)
250 #define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT)
251 
252 /*
253  * SDXC1_WKP_IRQ_EN (RW)
254  *
255  * wakeup irq enable
256  */
257 #define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK (0x40000000UL)
258 #define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT (30U)
259 #define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK)
260 #define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT)
261 
262 /*
263  * SDXC1_CARDCLK_INV_EN (RW)
264  *
265  * card clock inverter enable
266  */
267 #define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK (0x10000000UL)
268 #define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT (28U)
269 #define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK)
270 #define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT)
271 
272 /*
273  * SDXC1_GPR_TUNING_CARD_CLK_SEL (RW)
274  *
275  */
276 #define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK (0xF800000UL)
277 #define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT (23U)
278 #define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK)
279 #define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT)
280 
281 /*
282  * SDXC1_GPR_TUNING_STROBE_SEL (RW)
283  *
284  */
285 #define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK (0x7C0000UL)
286 #define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT (18U)
287 #define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK)
288 #define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT)
289 
290 /*
291  * SDXC1_GPR_STROBE_IN_ENABLE (RW)
292  *
293  */
294 #define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK (0x20000UL)
295 #define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT (17U)
296 #define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK)
297 #define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT)
298 
299 /*
300  * SDXC1_GPR_CCLK_RX_DLY_SW_SEL (RW)
301  *
302  */
303 #define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK (0x1F000UL)
304 #define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT (12U)
305 #define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK)
306 #define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT)
307 
308 /*
309  * SDXC1_GPR_CCLK_RX_DLY_SW_FORCE (RW)
310  *
311  */
312 #define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK (0x800U)
313 #define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT (11U)
314 #define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK)
315 #define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT)
316 
317 
318 
319 
320 #endif /* HPM_CONCTL_H */
321