1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_GPIO_H 10 #define HPM_GPIO_H 11 12 typedef struct { 13 struct { 14 __R uint32_t VALUE; /* 0x0: GPIO input value */ 15 __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ 16 } DI[16]; 17 struct { 18 __RW uint32_t VALUE; /* 0x100: GPIO output value */ 19 __RW uint32_t SET; /* 0x104: GPIO output set */ 20 __RW uint32_t CLEAR; /* 0x108: GPIO output clear */ 21 __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */ 22 } DO[16]; 23 struct { 24 __RW uint32_t VALUE; /* 0x200: GPIO direction value */ 25 __RW uint32_t SET; /* 0x204: GPIO direction set */ 26 __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */ 27 __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */ 28 } OE[16]; 29 struct { 30 __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ 31 __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */ 32 } IF[16]; 33 struct { 34 __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ 35 __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */ 36 __RW uint32_t CLEAR; /* 0x408: GPIO interrupt enable clear */ 37 __RW uint32_t TOGGLE; /* 0x40C: GPIO interrupt enable toggle */ 38 } IE[16]; 39 struct { 40 __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ 41 __RW uint32_t SET; /* 0x504: GPIO interrupt polarity set */ 42 __RW uint32_t CLEAR; /* 0x508: GPIO interrupt polarity clear */ 43 __RW uint32_t TOGGLE; /* 0x50C: GPIO interrupt polarity toggle */ 44 } PL[16]; 45 struct { 46 __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ 47 __RW uint32_t SET; /* 0x604: GPIO interrupt type set */ 48 __RW uint32_t CLEAR; /* 0x608: GPIO interrupt type clear */ 49 __RW uint32_t TOGGLE; /* 0x60C: GPIO interrupt type toggle */ 50 } TP[16]; 51 struct { 52 __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ 53 __RW uint32_t SET; /* 0x704: GPIO interrupt asynchronous set */ 54 __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ 55 __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ 56 } AS[16]; 57 struct { 58 __RW uint32_t VALUE; /* 0x800: GPIO dual edge interrupt enable value */ 59 __RW uint32_t SET; /* 0x804: GPIO dual edge interrupt enable set */ 60 __RW uint32_t CLEAR; /* 0x808: GPIO dual edge interrupt enable clear */ 61 __RW uint32_t TOGGLE; /* 0x80C: GPIO dual edge interrupt enable toggle */ 62 } PD[16]; 63 } GPIO_Type; 64 65 66 /* Bitfield definition for register of struct array DI: VALUE */ 67 /* 68 * INPUT (RO) 69 * 70 * GPIO input bus value, each bit represents a bus bit 71 * 0: low level presents on chip pin 72 * 1: high level presents on chip pin 73 */ 74 #define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) 75 #define GPIO_DI_VALUE_INPUT_SHIFT (0U) 76 #define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) 77 78 /* Bitfield definition for register of struct array DO: VALUE */ 79 /* 80 * OUTPUT (RW) 81 * 82 * GPIO output register value, each bit represents a bus bit 83 * 0: chip pin output low level when direction is output 84 * 1: chip pin output high level when direction is output 85 */ 86 #define GPIO_DO_VALUE_OUTPUT_MASK (0xFFFFFFFFUL) 87 #define GPIO_DO_VALUE_OUTPUT_SHIFT (0U) 88 #define GPIO_DO_VALUE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_VALUE_OUTPUT_SHIFT) & GPIO_DO_VALUE_OUTPUT_MASK) 89 #define GPIO_DO_VALUE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_VALUE_OUTPUT_MASK) >> GPIO_DO_VALUE_OUTPUT_SHIFT) 90 91 /* Bitfield definition for register of struct array DO: SET */ 92 /* 93 * OUTPUT (RW) 94 * 95 * GPIO output register value, each bit represents a bus bit 96 * 0: chip pin output low level when direction is output 97 * 1: chip pin output high level when direction is output 98 */ 99 #define GPIO_DO_SET_OUTPUT_MASK (0xFFFFFFFFUL) 100 #define GPIO_DO_SET_OUTPUT_SHIFT (0U) 101 #define GPIO_DO_SET_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_SET_OUTPUT_SHIFT) & GPIO_DO_SET_OUTPUT_MASK) 102 #define GPIO_DO_SET_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_SET_OUTPUT_MASK) >> GPIO_DO_SET_OUTPUT_SHIFT) 103 104 /* Bitfield definition for register of struct array DO: CLEAR */ 105 /* 106 * OUTPUT (RW) 107 * 108 * GPIO output register value, each bit represents a bus bit 109 * 0: chip pin output low level when direction is output 110 * 1: chip pin output high level when direction is output 111 */ 112 #define GPIO_DO_CLEAR_OUTPUT_MASK (0xFFFFFFFFUL) 113 #define GPIO_DO_CLEAR_OUTPUT_SHIFT (0U) 114 #define GPIO_DO_CLEAR_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_CLEAR_OUTPUT_SHIFT) & GPIO_DO_CLEAR_OUTPUT_MASK) 115 #define GPIO_DO_CLEAR_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_CLEAR_OUTPUT_MASK) >> GPIO_DO_CLEAR_OUTPUT_SHIFT) 116 117 /* Bitfield definition for register of struct array DO: TOGGLE */ 118 /* 119 * OUTPUT (RW) 120 * 121 * GPIO output register value, each bit represents a bus bit 122 * 0: chip pin output low level when direction is output 123 * 1: chip pin output high level when direction is output 124 */ 125 #define GPIO_DO_TOGGLE_OUTPUT_MASK (0xFFFFFFFFUL) 126 #define GPIO_DO_TOGGLE_OUTPUT_SHIFT (0U) 127 #define GPIO_DO_TOGGLE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_TOGGLE_OUTPUT_SHIFT) & GPIO_DO_TOGGLE_OUTPUT_MASK) 128 #define GPIO_DO_TOGGLE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_TOGGLE_OUTPUT_MASK) >> GPIO_DO_TOGGLE_OUTPUT_SHIFT) 129 130 /* Bitfield definition for register of struct array OE: VALUE */ 131 /* 132 * DIRECTION (RW) 133 * 134 * GPIO direction, each bit represents a bus bit 135 * 0: input 136 * 1: output 137 */ 138 #define GPIO_OE_VALUE_DIRECTION_MASK (0xFFFFFFFFUL) 139 #define GPIO_OE_VALUE_DIRECTION_SHIFT (0U) 140 #define GPIO_OE_VALUE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_VALUE_DIRECTION_SHIFT) & GPIO_OE_VALUE_DIRECTION_MASK) 141 #define GPIO_OE_VALUE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_VALUE_DIRECTION_MASK) >> GPIO_OE_VALUE_DIRECTION_SHIFT) 142 143 /* Bitfield definition for register of struct array OE: SET */ 144 /* 145 * DIRECTION (RW) 146 * 147 * GPIO direction, each bit represents a bus bit 148 * 0: input 149 * 1: output 150 */ 151 #define GPIO_OE_SET_DIRECTION_MASK (0xFFFFFFFFUL) 152 #define GPIO_OE_SET_DIRECTION_SHIFT (0U) 153 #define GPIO_OE_SET_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_SET_DIRECTION_SHIFT) & GPIO_OE_SET_DIRECTION_MASK) 154 #define GPIO_OE_SET_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_SET_DIRECTION_MASK) >> GPIO_OE_SET_DIRECTION_SHIFT) 155 156 /* Bitfield definition for register of struct array OE: CLEAR */ 157 /* 158 * DIRECTION (RW) 159 * 160 * GPIO direction, each bit represents a bus bit 161 * 0: input 162 * 1: output 163 */ 164 #define GPIO_OE_CLEAR_DIRECTION_MASK (0xFFFFFFFFUL) 165 #define GPIO_OE_CLEAR_DIRECTION_SHIFT (0U) 166 #define GPIO_OE_CLEAR_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_CLEAR_DIRECTION_SHIFT) & GPIO_OE_CLEAR_DIRECTION_MASK) 167 #define GPIO_OE_CLEAR_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_CLEAR_DIRECTION_MASK) >> GPIO_OE_CLEAR_DIRECTION_SHIFT) 168 169 /* Bitfield definition for register of struct array OE: TOGGLE */ 170 /* 171 * DIRECTION (RW) 172 * 173 * GPIO direction, each bit represents a bus bit 174 * 0: input 175 * 1: output 176 */ 177 #define GPIO_OE_TOGGLE_DIRECTION_MASK (0xFFFFFFFFUL) 178 #define GPIO_OE_TOGGLE_DIRECTION_SHIFT (0U) 179 #define GPIO_OE_TOGGLE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_TOGGLE_DIRECTION_SHIFT) & GPIO_OE_TOGGLE_DIRECTION_MASK) 180 #define GPIO_OE_TOGGLE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_TOGGLE_DIRECTION_MASK) >> GPIO_OE_TOGGLE_DIRECTION_SHIFT) 181 182 /* Bitfield definition for register of struct array IF: VALUE */ 183 /* 184 * IRQ_FLAG (W1C) 185 * 186 * GPIO interrupt flag, write 1 to clear this flag 187 * 0: no irq 188 * 1: irq pending 189 */ 190 #define GPIO_IF_VALUE_IRQ_FLAG_MASK (0xFFFFFFFFUL) 191 #define GPIO_IF_VALUE_IRQ_FLAG_SHIFT (0U) 192 #define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) 193 #define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) 194 195 /* Bitfield definition for register of struct array IE: VALUE */ 196 /* 197 * IRQ_EN (RW) 198 * 199 * GPIO interrupt enable, each bit represents a bus bit 200 * 0: irq is disabled 201 * 1: irq is enable 202 */ 203 #define GPIO_IE_VALUE_IRQ_EN_MASK (0xFFFFFFFFUL) 204 #define GPIO_IE_VALUE_IRQ_EN_SHIFT (0U) 205 #define GPIO_IE_VALUE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_VALUE_IRQ_EN_SHIFT) & GPIO_IE_VALUE_IRQ_EN_MASK) 206 #define GPIO_IE_VALUE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_VALUE_IRQ_EN_MASK) >> GPIO_IE_VALUE_IRQ_EN_SHIFT) 207 208 /* Bitfield definition for register of struct array IE: SET */ 209 /* 210 * IRQ_EN (RW) 211 * 212 * GPIO interrupt enable, each bit represents a bus bit 213 * 0: irq is disabled 214 * 1: irq is enable 215 */ 216 #define GPIO_IE_SET_IRQ_EN_MASK (0xFFFFFFFFUL) 217 #define GPIO_IE_SET_IRQ_EN_SHIFT (0U) 218 #define GPIO_IE_SET_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_SET_IRQ_EN_SHIFT) & GPIO_IE_SET_IRQ_EN_MASK) 219 #define GPIO_IE_SET_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_SET_IRQ_EN_MASK) >> GPIO_IE_SET_IRQ_EN_SHIFT) 220 221 /* Bitfield definition for register of struct array IE: CLEAR */ 222 /* 223 * IRQ_EN (RW) 224 * 225 * GPIO interrupt enable, each bit represents a bus bit 226 * 0: irq is disabled 227 * 1: irq is enable 228 */ 229 #define GPIO_IE_CLEAR_IRQ_EN_MASK (0xFFFFFFFFUL) 230 #define GPIO_IE_CLEAR_IRQ_EN_SHIFT (0U) 231 #define GPIO_IE_CLEAR_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_CLEAR_IRQ_EN_SHIFT) & GPIO_IE_CLEAR_IRQ_EN_MASK) 232 #define GPIO_IE_CLEAR_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_CLEAR_IRQ_EN_MASK) >> GPIO_IE_CLEAR_IRQ_EN_SHIFT) 233 234 /* Bitfield definition for register of struct array IE: TOGGLE */ 235 /* 236 * IRQ_EN (RW) 237 * 238 * GPIO interrupt enable, each bit represents a bus bit 239 * 0: irq is disabled 240 * 1: irq is enable 241 */ 242 #define GPIO_IE_TOGGLE_IRQ_EN_MASK (0xFFFFFFFFUL) 243 #define GPIO_IE_TOGGLE_IRQ_EN_SHIFT (0U) 244 #define GPIO_IE_TOGGLE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_TOGGLE_IRQ_EN_SHIFT) & GPIO_IE_TOGGLE_IRQ_EN_MASK) 245 #define GPIO_IE_TOGGLE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_TOGGLE_IRQ_EN_MASK) >> GPIO_IE_TOGGLE_IRQ_EN_SHIFT) 246 247 /* Bitfield definition for register of struct array PL: VALUE */ 248 /* 249 * IRQ_POL (RW) 250 * 251 * GPIO interrupt polarity, each bit represents a bus bit 252 * 0: irq is high level or rising edge 253 * 1: irq is low level or falling edge 254 */ 255 #define GPIO_PL_VALUE_IRQ_POL_MASK (0xFFFFFFFFUL) 256 #define GPIO_PL_VALUE_IRQ_POL_SHIFT (0U) 257 #define GPIO_PL_VALUE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_VALUE_IRQ_POL_SHIFT) & GPIO_PL_VALUE_IRQ_POL_MASK) 258 #define GPIO_PL_VALUE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_VALUE_IRQ_POL_MASK) >> GPIO_PL_VALUE_IRQ_POL_SHIFT) 259 260 /* Bitfield definition for register of struct array PL: SET */ 261 /* 262 * IRQ_POL (RW) 263 * 264 * GPIO interrupt polarity, each bit represents a bus bit 265 * 0: irq is high level or rising edge 266 * 1: irq is low level or falling edge 267 */ 268 #define GPIO_PL_SET_IRQ_POL_MASK (0xFFFFFFFFUL) 269 #define GPIO_PL_SET_IRQ_POL_SHIFT (0U) 270 #define GPIO_PL_SET_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_SET_IRQ_POL_SHIFT) & GPIO_PL_SET_IRQ_POL_MASK) 271 #define GPIO_PL_SET_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_SET_IRQ_POL_MASK) >> GPIO_PL_SET_IRQ_POL_SHIFT) 272 273 /* Bitfield definition for register of struct array PL: CLEAR */ 274 /* 275 * IRQ_POL (RW) 276 * 277 * GPIO interrupt polarity, each bit represents a bus bit 278 * 0: irq is high level or rising edge 279 * 1: irq is low level or falling edge 280 */ 281 #define GPIO_PL_CLEAR_IRQ_POL_MASK (0xFFFFFFFFUL) 282 #define GPIO_PL_CLEAR_IRQ_POL_SHIFT (0U) 283 #define GPIO_PL_CLEAR_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_CLEAR_IRQ_POL_SHIFT) & GPIO_PL_CLEAR_IRQ_POL_MASK) 284 #define GPIO_PL_CLEAR_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_CLEAR_IRQ_POL_MASK) >> GPIO_PL_CLEAR_IRQ_POL_SHIFT) 285 286 /* Bitfield definition for register of struct array PL: TOGGLE */ 287 /* 288 * IRQ_POL (RW) 289 * 290 * GPIO interrupt polarity, each bit represents a bus bit 291 * 0: irq is high level or rising edge 292 * 1: irq is low level or falling edge 293 */ 294 #define GPIO_PL_TOGGLE_IRQ_POL_MASK (0xFFFFFFFFUL) 295 #define GPIO_PL_TOGGLE_IRQ_POL_SHIFT (0U) 296 #define GPIO_PL_TOGGLE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_TOGGLE_IRQ_POL_SHIFT) & GPIO_PL_TOGGLE_IRQ_POL_MASK) 297 #define GPIO_PL_TOGGLE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_TOGGLE_IRQ_POL_MASK) >> GPIO_PL_TOGGLE_IRQ_POL_SHIFT) 298 299 /* Bitfield definition for register of struct array TP: VALUE */ 300 /* 301 * IRQ_TYPE (RW) 302 * 303 * GPIO interrupt type, each bit represents a bus bit 304 * 0: irq is triggered by level 305 * 1: irq is triggered by edge 306 */ 307 #define GPIO_TP_VALUE_IRQ_TYPE_MASK (0xFFFFFFFFUL) 308 #define GPIO_TP_VALUE_IRQ_TYPE_SHIFT (0U) 309 #define GPIO_TP_VALUE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_VALUE_IRQ_TYPE_SHIFT) & GPIO_TP_VALUE_IRQ_TYPE_MASK) 310 #define GPIO_TP_VALUE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_VALUE_IRQ_TYPE_MASK) >> GPIO_TP_VALUE_IRQ_TYPE_SHIFT) 311 312 /* Bitfield definition for register of struct array TP: SET */ 313 /* 314 * IRQ_TYPE (RW) 315 * 316 * GPIO interrupt type, each bit represents a bus bit 317 * 0: irq is triggered by level 318 * 1: irq is triggered by edge 319 */ 320 #define GPIO_TP_SET_IRQ_TYPE_MASK (0xFFFFFFFFUL) 321 #define GPIO_TP_SET_IRQ_TYPE_SHIFT (0U) 322 #define GPIO_TP_SET_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_SET_IRQ_TYPE_SHIFT) & GPIO_TP_SET_IRQ_TYPE_MASK) 323 #define GPIO_TP_SET_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_SET_IRQ_TYPE_MASK) >> GPIO_TP_SET_IRQ_TYPE_SHIFT) 324 325 /* Bitfield definition for register of struct array TP: CLEAR */ 326 /* 327 * IRQ_TYPE (RW) 328 * 329 * GPIO interrupt type, each bit represents a bus bit 330 * 0: irq is triggered by level 331 * 1: irq is triggered by edge 332 */ 333 #define GPIO_TP_CLEAR_IRQ_TYPE_MASK (0xFFFFFFFFUL) 334 #define GPIO_TP_CLEAR_IRQ_TYPE_SHIFT (0U) 335 #define GPIO_TP_CLEAR_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) 336 #define GPIO_TP_CLEAR_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) >> GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) 337 338 /* Bitfield definition for register of struct array TP: TOGGLE */ 339 /* 340 * IRQ_TYPE (RW) 341 * 342 * GPIO interrupt type, each bit represents a bus bit 343 * 0: irq is triggered by level 344 * 1: irq is triggered by edge 345 */ 346 #define GPIO_TP_TOGGLE_IRQ_TYPE_MASK (0xFFFFFFFFUL) 347 #define GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT (0U) 348 #define GPIO_TP_TOGGLE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) 349 #define GPIO_TP_TOGGLE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) >> GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) 350 351 /* Bitfield definition for register of struct array AS: VALUE */ 352 /* 353 * IRQ_ASYNC (RW) 354 * 355 * GPIO interrupt asynchronous, each bit represents a bus bit 356 * 0: irq is triggered base on system clock 357 * 1: irq is triggered combinational 358 * Note: combinational interrupt is sensitive to environment noise 359 */ 360 #define GPIO_AS_VALUE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) 361 #define GPIO_AS_VALUE_IRQ_ASYNC_SHIFT (0U) 362 #define GPIO_AS_VALUE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) 363 #define GPIO_AS_VALUE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) >> GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) 364 365 /* Bitfield definition for register of struct array AS: SET */ 366 /* 367 * IRQ_ASYNC (RW) 368 * 369 * GPIO interrupt asynchronous, each bit represents a bus bit 370 * 0: irq is triggered base on system clock 371 * 1: irq is triggered combinational 372 * Note: combinational interrupt is sensitive to environment noise 373 */ 374 #define GPIO_AS_SET_IRQ_ASYNC_MASK (0xFFFFFFFFUL) 375 #define GPIO_AS_SET_IRQ_ASYNC_SHIFT (0U) 376 #define GPIO_AS_SET_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_SET_IRQ_ASYNC_SHIFT) & GPIO_AS_SET_IRQ_ASYNC_MASK) 377 #define GPIO_AS_SET_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_SET_IRQ_ASYNC_MASK) >> GPIO_AS_SET_IRQ_ASYNC_SHIFT) 378 379 /* Bitfield definition for register of struct array AS: CLEAR */ 380 /* 381 * IRQ_ASYNC (RW) 382 * 383 * GPIO interrupt asynchronous, each bit represents a bus bit 384 * 0: irq is triggered base on system clock 385 * 1: irq is triggered combinational 386 * Note: combinational interrupt is sensitive to environment noise 387 */ 388 #define GPIO_AS_CLEAR_IRQ_ASYNC_MASK (0xFFFFFFFFUL) 389 #define GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT (0U) 390 #define GPIO_AS_CLEAR_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) 391 #define GPIO_AS_CLEAR_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) >> GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) 392 393 /* Bitfield definition for register of struct array AS: TOGGLE */ 394 /* 395 * IRQ_ASYNC (RW) 396 * 397 * GPIO interrupt asynchronous, each bit represents a bus bit 398 * 0: irq is triggered base on system clock 399 * 1: irq is triggered combinational 400 * Note: combinational interrupt is sensitive to environment noise 401 */ 402 #define GPIO_AS_TOGGLE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) 403 #define GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT (0U) 404 #define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) 405 #define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) 406 407 /* Bitfield definition for register of struct array PD: VALUE */ 408 /* 409 * IRQ_DUAL (RW) 410 * 411 * GPIO dual edge interrupt enable 412 * 0: single edge interrupt 413 * 1: dual edge interrupt enable 414 */ 415 #define GPIO_PD_VALUE_IRQ_DUAL_MASK (0x1U) 416 #define GPIO_PD_VALUE_IRQ_DUAL_SHIFT (0U) 417 #define GPIO_PD_VALUE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_VALUE_IRQ_DUAL_SHIFT) & GPIO_PD_VALUE_IRQ_DUAL_MASK) 418 #define GPIO_PD_VALUE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_VALUE_IRQ_DUAL_MASK) >> GPIO_PD_VALUE_IRQ_DUAL_SHIFT) 419 420 /* Bitfield definition for register of struct array PD: SET */ 421 /* 422 * IRQ_DUAL (RW) 423 * 424 * GPIO dual edge interrupt enable set 425 * 0: keep original edge interrupt type 426 * 1: dual edge interrupt enable 427 */ 428 #define GPIO_PD_SET_IRQ_DUAL_MASK (0x1U) 429 #define GPIO_PD_SET_IRQ_DUAL_SHIFT (0U) 430 #define GPIO_PD_SET_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_SET_IRQ_DUAL_SHIFT) & GPIO_PD_SET_IRQ_DUAL_MASK) 431 #define GPIO_PD_SET_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_SET_IRQ_DUAL_MASK) >> GPIO_PD_SET_IRQ_DUAL_SHIFT) 432 433 /* Bitfield definition for register of struct array PD: CLEAR */ 434 /* 435 * IRQ_DUAL (RW) 436 * 437 * GPIO dual edge interrupt enable clear 438 * 0: keep original edge interrupt type 439 * 1: single edge interrupt enable 440 */ 441 #define GPIO_PD_CLEAR_IRQ_DUAL_MASK (0x1U) 442 #define GPIO_PD_CLEAR_IRQ_DUAL_SHIFT (0U) 443 #define GPIO_PD_CLEAR_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) 444 #define GPIO_PD_CLEAR_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) >> GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) 445 446 /* Bitfield definition for register of struct array PD: TOGGLE */ 447 /* 448 * IRQ_DUAL (RW) 449 * 450 * GPIO dual edge interrupt enable toggle 451 * 0: keep original edge interrupt type 452 * 1: change original edge interrupt type to another one. 453 */ 454 #define GPIO_PD_TOGGLE_IRQ_DUAL_MASK (0x1U) 455 #define GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT (0U) 456 #define GPIO_PD_TOGGLE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) 457 #define GPIO_PD_TOGGLE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) >> GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) 458 459 460 461 /* DI register group index macro definition */ 462 #define GPIO_DI_GPIOA (0UL) 463 #define GPIO_DI_GPIOB (1UL) 464 #define GPIO_DI_GPIOC (2UL) 465 #define GPIO_DI_GPIOD (3UL) 466 #define GPIO_DI_GPIOE (4UL) 467 #define GPIO_DI_GPIOF (5UL) 468 #define GPIO_DI_GPIOX (13UL) 469 #define GPIO_DI_GPIOY (14UL) 470 #define GPIO_DI_GPIOZ (15UL) 471 472 /* DO register group index macro definition */ 473 #define GPIO_DO_GPIOA (0UL) 474 #define GPIO_DO_GPIOB (1UL) 475 #define GPIO_DO_GPIOC (2UL) 476 #define GPIO_DO_GPIOD (3UL) 477 #define GPIO_DO_GPIOE (4UL) 478 #define GPIO_DO_GPIOF (5UL) 479 #define GPIO_DO_GPIOX (13UL) 480 #define GPIO_DO_GPIOY (14UL) 481 #define GPIO_DO_GPIOZ (15UL) 482 483 /* OE register group index macro definition */ 484 #define GPIO_OE_GPIOA (0UL) 485 #define GPIO_OE_GPIOB (1UL) 486 #define GPIO_OE_GPIOC (2UL) 487 #define GPIO_OE_GPIOD (3UL) 488 #define GPIO_OE_GPIOE (4UL) 489 #define GPIO_OE_GPIOF (5UL) 490 #define GPIO_OE_GPIOX (13UL) 491 #define GPIO_OE_GPIOY (14UL) 492 #define GPIO_OE_GPIOZ (15UL) 493 494 /* IF register group index macro definition */ 495 #define GPIO_IF_GPIOA (0UL) 496 #define GPIO_IF_GPIOB (1UL) 497 #define GPIO_IF_GPIOC (2UL) 498 #define GPIO_IF_GPIOD (3UL) 499 #define GPIO_IF_GPIOE (4UL) 500 #define GPIO_IF_GPIOF (5UL) 501 #define GPIO_IF_GPIOX (13UL) 502 #define GPIO_IF_GPIOY (14UL) 503 #define GPIO_IF_GPIOZ (15UL) 504 505 /* IE register group index macro definition */ 506 #define GPIO_IE_GPIOA (0UL) 507 #define GPIO_IE_GPIOB (1UL) 508 #define GPIO_IE_GPIOC (2UL) 509 #define GPIO_IE_GPIOD (3UL) 510 #define GPIO_IE_GPIOE (4UL) 511 #define GPIO_IE_GPIOF (5UL) 512 #define GPIO_IE_GPIOX (13UL) 513 #define GPIO_IE_GPIOY (14UL) 514 #define GPIO_IE_GPIOZ (15UL) 515 516 /* PL register group index macro definition */ 517 #define GPIO_PL_GPIOA (0UL) 518 #define GPIO_PL_GPIOB (1UL) 519 #define GPIO_PL_GPIOC (2UL) 520 #define GPIO_PL_GPIOD (3UL) 521 #define GPIO_PL_GPIOE (4UL) 522 #define GPIO_PL_GPIOF (5UL) 523 #define GPIO_PL_GPIOX (13UL) 524 #define GPIO_PL_GPIOY (14UL) 525 #define GPIO_PL_GPIOZ (15UL) 526 527 /* TP register group index macro definition */ 528 #define GPIO_TP_GPIOA (0UL) 529 #define GPIO_TP_GPIOB (1UL) 530 #define GPIO_TP_GPIOC (2UL) 531 #define GPIO_TP_GPIOD (3UL) 532 #define GPIO_TP_GPIOE (4UL) 533 #define GPIO_TP_GPIOF (5UL) 534 #define GPIO_TP_GPIOX (13UL) 535 #define GPIO_TP_GPIOY (14UL) 536 #define GPIO_TP_GPIOZ (15UL) 537 538 /* AS register group index macro definition */ 539 #define GPIO_AS_GPIOA (0UL) 540 #define GPIO_AS_GPIOB (1UL) 541 #define GPIO_AS_GPIOC (2UL) 542 #define GPIO_AS_GPIOD (3UL) 543 #define GPIO_AS_GPIOE (4UL) 544 #define GPIO_AS_GPIOF (5UL) 545 #define GPIO_AS_GPIOX (13UL) 546 #define GPIO_AS_GPIOY (14UL) 547 #define GPIO_AS_GPIOZ (15UL) 548 549 /* PD register group index macro definition */ 550 #define GPIO_PD_GPIOA (0UL) 551 #define GPIO_PD_GPIOB (1UL) 552 #define GPIO_PD_GPIOC (2UL) 553 #define GPIO_PD_GPIOD (3UL) 554 #define GPIO_PD_GPIOE (4UL) 555 #define GPIO_PD_GPIOF (5UL) 556 #define GPIO_PD_GPIOX (13UL) 557 #define GPIO_PD_GPIOY (14UL) 558 #define GPIO_PD_GPIOZ (15UL) 559 560 561 #endif /* HPM_GPIO_H */ 562