1 #ifndef HPM_ROMAPI_XPI_RAM_DEF_H 2 #define HPM_ROMAPI_XPI_RAM_DEF_H 3 4 /** 5 * @brief XPI RAM ROM APIs 6 * @defgroup xpi_ram_interface XPI RAM driver APIs 7 * @ingroup romapi_interfaces 8 * @{ 9 */ 10 11 #include "hpm_common.h" 12 #include "hpm_romapi_xpi_def.h" 13 14 /********************************************************************************************************************** 15 * Definitions 16 *********************************************************************************************************************/ 17 18 /** 19 * @brief XPI RAM configuration option tag 20 */ 21 #define XPI_RAM_CFG_OPTION_TAG (0xfcf91U) 22 23 /** 24 * @brief XPI RAM Configuration block tag 25 */ 26 #define XPI_RAM_CFG_TAG (0x4D415258U) 27 28 /** 29 * @brief XPI RAM safe frequency option 30 */ 31 enum { 32 xpi_ram_safe_clk_freq = 1, 33 }; 34 35 /** 36 * @brief XPI RAM configuration option 37 * The ROM SW can detect the FLASH configuration based on the following structure specified by the end-user 38 */ 39 typedef struct { 40 union { 41 struct { 42 uint32_t words: 4; /**< Option words, exclude the header itself */ 43 uint32_t instance: 4; /**< 0 - Instance 0, 1 - Instance 1 */ 44 uint32_t reserved: 4; /**< Reserved for future use */ 45 uint32_t tag: 20; /**< Must be 0xfcf91 */ 46 }; 47 uint32_t U; 48 } header; 49 union { 50 struct { 51 uint32_t freq_opt: 4; /**< 1 - 30MHz, others, SoC specific setting */ 52 uint32_t misc: 4; /**< Not used for now */ 53 uint32_t ram_size : 8; /**< 0 - Auto detected, others - User specified size in MB */ 54 uint32_t pin_group: 4; /**< Pin group, 0 - 1st group, 1 - 2nd group */ 55 uint32_t read_dummy_cycles: 4; /**< Dummy cycyles for read command, 0 - default, 1 - user specified value */ 56 uint32_t write_dummy_cycles:4; /**< Dummy cycyles for write command, 0 - default, 1 - user specified value */ 57 uint32_t probe_type: 4; /**< 0 - HyperRAM 1 - APMemory X8 devices */ 58 }; 59 uint32_t U; 60 } option0; 61 union { 62 struct { 63 uint32_t drive_strength: 4; /**< Drive strength */ 64 uint32_t max_cs_low_time: 4; /**< Maximum CS low time, in terms of microseconds */ 65 uint32_t pin_group_sel: 4; /**< Pin group selection */ 66 uint32_t channel: 4; /**< Channel */ 67 uint32_t skip_ahb_buf_cfg:4; /**< Skip AHB buffer configuration */ 68 uint32_t reserved: 12; 69 }; 70 uint32_t U; 71 } option1; 72 } xpi_ram_config_option_t; 73 74 75 /** 76 * @brief XPI RAM type options 77 */ 78 enum { 79 xpi_ram_type_apmemory_x8 = 0, /**< APMemory PSRAM X8 */ 80 xpi_ram_type_hyperram = 1, /**< HyperRAM */ 81 xpi_ram_type_apmemory_x4 = 2, /**< APMemory PSRAM X4 */ 82 }; 83 84 /** 85 * @brief HyperRAM voltage options 86 */ 87 enum { 88 xpi_ram_option_misc_hyperram_3v0, 89 xpi_ram_option_misc_hyperram_1v8, 90 }; 91 92 93 /** 94 * @brief XPI RAM maximum CS low time definition 95 */ 96 enum { 97 xpi_ram_default_max_cs_low_time_us = 4, /**< Default Maximum CS low internal is 4us */ 98 }; 99 100 /** 101 * @brief XPI RAM pad definitions 102 */ 103 enum { 104 xpi_ram_opi = XPI_8PADS, /**< XPI RAM PAD option: Octal pads */ 105 xpi_ram_qpi = XPI_4PADS, /**< XPI RAM PAD option: Quad pads */ 106 }; 107 108 /** 109 * @brief XPI RAM Configuration command type 110 */ 111 enum { 112 xpi_ram_cfg_cmd_type_generic = 1, /**< Generic configuration command */ 113 xpi_ram_cfg_cmd_type_spi2xpi = 2, /**< SPI to XPI configuration command */ 114 }; 115 116 /** 117 * @brief XPI RAM device configuration structure 118 */ 119 typedef struct { 120 uint8_t cmd_type; /**< Command type */ 121 uint8_t param_size; /**< Size of the parameter */ 122 } device_config_t; 123 124 /** 125 * @brief XPI RAM information structure 126 */ 127 typedef struct { 128 uint32_t size_in_kbytes; /**< Device Size in Kilobytes, offset 0x00 */ 129 uint8_t data_pads; /**< Device Size in Kilobytes, offset 0x04 */ 130 uint8_t en_ddr_mode; /**< Enable DDR mode, offset 0x05 */ 131 uint8_t clk_freq_for_device_cfg; /**< Clk frequency for device configuration, offset 0x6 */ 132 uint8_t working_mode_por; /**< Offset 0x7 */ 133 uint8_t working_mode; /**< The device working mode, offset 0x08 */ 134 uint8_t en_diff_clk; /**< Enable Differential clock, offset 0x09 */ 135 uint8_t data_valid_time; /**< Data valid time, in 0.1ns, offset 0x0a */ 136 uint8_t cs_hold_time; /**< CS hold time, 0 - default value, others - user specified value, offset 0xb */ 137 uint8_t cs_setup_time; /**< CS setup time, 0 - default value, others - user specified value, offset 0xc */ 138 uint8_t cs_interval; /**< CS interval, intervals between to CS active, offset 0x0d */ 139 uint8_t io_voltage; /**< Device IO voltage, offset 0x0e*/ 140 uint8_t reserved0; /**< Reserved for future use, offset 0xf */ 141 device_config_t device_cfg_list[2]; /**< Device configuration list, offset 0x10 */ 142 uint32_t reserved1; /**< Reserved, offset 0x14 */ 143 uint32_t device_config_params[2]; /**< device config params, offset 0x18 */ 144 xpi_instr_seq_t device_cfg_instr_seq[2];/**< Device configuration instruction sequence, offset 0x20 */ 145 uint32_t device_cfg_addr[2]; /**< Device Configuration address, offset 0x40 */ 146 uint32_t reserved2[2]; /**< Reserved for future use, offset 0x48 */ 147 } xpi_ram_info_t; 148 149 /** 150 * @brief XPI RAM configuration structure 151 */ 152 typedef struct { 153 uint32_t tag; /**< Must be "XRAM", offset 0x000 */ 154 uint32_t reserved0; /**< Reserved for future use, offset 0x004 */ 155 uint8_t rxclk_src; /**< RXCLKSRC value, offset 0x008 */ 156 uint8_t clk_freq; /**< Clock frequency, offset 0x009 */ 157 uint8_t drive_strength; /**< Drive strength, offset 0x0a */ 158 uint8_t column_addr_size; /**< Column address size, offset 0x0b */ 159 uint8_t rxclk_src_for_init; /**< RXCLKSRC during initialization, offset 0x0c */ 160 uint8_t enable_word_addr; /**< Enable word address mode, offset 0x0d */ 161 uint8_t max_cs_low_time; /**< Max CS low time in terms of us, offset 0x0e */ 162 uint8_t skip_ahb_buf_cfg; /**< Skip Configuring AHB buffer, offset 0x0f */ 163 struct { 164 uint8_t enable; /**< Enable the port, 0 - disable, 1 - enable */ 165 uint8_t group; /**< 0 - 1st IO group, 1 - 2nd IO group */ 166 uint8_t reserved[2]; 167 } port_info[4]; /**< Device connection information */ 168 xpi_ram_info_t device_info; /**< Device info, offset 0x20 */ 169 xpi_instr_seq_t instr_set[2]; /**< XPI RAM read and write instruction sequences */ 170 } xpi_ram_config_t; 171 172 /** 173 * @} 174 */ 175 176 #endif /* HPM_ROMAPI_XPI_RAM_DEF_H */ 177