1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 #include <stdio.h> 21 #include <driver/int_types.h> 22 #include <soc/soc.h> 23 24 #define GROUP0 0 25 #define GROUP1 1 26 #define INVALID 0 27 28 /* 29 * 1.NOTICE: help confirm this array sequence is the same as icu_int_src_t, 30 * because the code in API of "bk_int_isr_register" uses the value as index of INT_SRC. 31 * 2.The PRIOURITY in this array is inherit from ARM(IRQ/FIQ), not valid in RISC-V. 32 * so here uses the default value which is 1.We'll modify it after the priourity 33 * feature is finish. 34 * 3.There aren't exist some IRQ numbers: 28,42~47,51,56~63 35 */ 36 #define ICU_DEV_MAP \ 37 {\ 38 {INT_SRC_UART1, 4, IQR_PRI_DEFAULT,GROUP0}, \ 39 {INT_SRC_UART2, 15, IQR_PRI_DEFAULT,GROUP0}, \ 40 {INT_SRC_I2C0, 14, IQR_PRI_DEFAULT, GROUP0}, \ 41 {INT_SRC_IRDA, 9, IQR_PRI_DEFAULT, GROUP0}, \ 42 {INT_SRC_I2S, 24, IQR_PRI_DEFAULT,GROUP0}, \ 43 {INT_SRC_I2C1, 6, IQR_PRI_DEFAULT, GROUP0}, \ 44 {INT_SRC_SPI, 7, IQR_PRI_DEFAULT,GROUP0}, \ 45 {INT_SRC_GPIO, 55, IQR_PRI_DEFAULT, GROUP1}, \ 46 {INT_SRC_TIMER, 3, IQR_PRI_DEFAULT,GROUP0}, \ 47 {INT_SRC_PWM, 5, IQR_PRI_DEFAULT,GROUP0}, \ 48 {INT_SRC_AUDIO, 23, IQR_PRI_DEFAULT, GROUP0}, \ 49 {INT_SRC_SARADC, 8, IQR_PRI_DEFAULT, GROUP0}, \ 50 {INT_SRC_SDIO, 10, IQR_PRI_DEFAULT, GROUP0}, \ 51 {INT_SRC_USB, 19, IQR_PRI_DEFAULT, GROUP0}, \ 52 {INT_SRC_FFT, 21, IQR_PRI_DEFAULT, GROUP0}, \ 53 {INT_SRC_GDMA, 11, IQR_PRI_DEFAULT, GROUP0}, \ 54 {INT_SRC_MODEM, 29, IQR_PRI_DEFAULT, GROUP0}, \ 55 {INT_SRC_MAC_TXRX_TIMER, 31, IQR_PRI_DEFAULT, GROUP0}, \ 56 {INT_SRC_MAC_TXRX_MISC, 32, IQR_PRI_DEFAULT, GROUP1}, \ 57 {INT_SRC_MAC_RX_TRIGGER, 33, IQR_PRI_DEFAULT, GROUP1}, \ 58 {INT_SRC_MAC_TX_TRIGGER, 34, IQR_PRI_DEFAULT, GROUP1}, \ 59 {INT_SRC_MAC_PROT_TRIGGER, 35, IQR_PRI_DEFAULT, GROUP1}, \ 60 {INT_SRC_MAC_GENERAL, 36, IQR_PRI_DEFAULT, GROUP1}, \ 61 {INT_SRC_SDIO_DMA, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 62 {INT_SRC_USB_PLUG_INOUT, 53, IQR_PRI_DEFAULT, GROUP1}, \ 63 {INT_SRC_SECURITY, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 64 {INT_SRC_MAC_WAKEUP, 38, IQR_PRI_DEFAULT, GROUP1}, \ 65 {INT_SRC_HSSPI_SLAVE, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 66 {INT_SRC_PLL_UNLOCK, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 67 {INT_SRC_JPEG_DEC, 26, IQR_PRI_DEFAULT, GROUP0}, \ 68 {INT_SRC_BLE, 40, IQR_PRI_DEFAULT, GROUP1}, \ 69 {INT_SRC_PSRAM, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 70 {INT_SRC_LA, 12, IQR_PRI_DEFAULT, GROUP0}, \ 71 {INT_SRC_BTDM, 39, IQR_PRI_DEFAULT, GROUP1}, \ 72 {INT_SRC_BT, 41, IQR_PRI_DEFAULT, GROUP1}, \ 73 {INT_SRC_UART3, 16, IQR_PRI_DEFAULT, GROUP0}, \ 74 {INT_SRC_I2C2, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 75 {INT_SRC_SPI2, 17, IQR_PRI_DEFAULT, GROUP0}, \ 76 {INT_SRC_SPI3, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 77 {INT_SRC_PWM2, 5, IQR_PRI_DEFAULT, GROUP0}, \ 78 {INT_SRC_USB2, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 79 {INT_SRC_MAILBOX0, 48, IQR_PRI_DEFAULT, GROUP1}, \ 80 {INT_SRC_MAILBOX1, 49, IQR_PRI_DEFAULT, GROUP1}, \ 81 {INT_SRC_BT_WDT, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 82 {INT_SRC_DSP_WDT, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 83 {INT_SRC_RTC, 54, IQR_PRI_DEFAULT, GROUP1}, \ 84 {INT_SRC_TOUCH, 52, IQR_PRI_DEFAULT, GROUP1}, \ 85 {INT_SRC_CEC, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 86 {INT_SRC_MODEM_RC, 30, IQR_PRI_DEFAULT, GROUP0}, \ 87 {INT_SRC_MAC_HSU, 37, IQR_PRI_DEFAULT, GROUP1}, \ 88 {INT_SRC_TIMER1, 13, ICU_PRI_IRQ_TIMER,GROUP0}, \ 89 {INT_SRC_MAC_INTN_PHY, INVALID, IQR_PRI_DEFAULT, GROUP0}, \ 90 {INT_SRC_MAC_INT_GEN, INVALID, IQR_PRI_DEFAULT, GROUP1}, \ 91 {INT_SRC_MAC_INT_RESERVED0, INVALID, IQR_PRI_DEFAULT, GROUP1}, \ 92 {INT_SRC_JPEG_ENC,25, IQR_PRI_DEFAULT, GROUP0}, \ 93 {INT_SRC_EIP130_SEC,2, IQR_PRI_DEFAULT, GROUP0}, \ 94 {INT_SRC_EIP130, 1, IQR_PRI_DEFAULT, GROUP0}, \ 95 {INT_SRC_LCD, 27, IQR_PRI_DEFAULT, GROUP0}, \ 96 {INT_SRC_QSPI, 20, ICU_PRI_IRQ_QSPI, GROUP0}, \ 97 {INT_SRC_CAN, 18, IQR_PRI_DEFAULT, GROUP0}, \ 98 {INT_SRC_SBC, 22, IQR_PRI_DEFAULT, GROUP0}, \ 99 {INT_SRC_BMC32, 0, IQR_PRI_DEFAULT, GROUP0}, \ 100 {INT_SRC_BMC64, 50, IQR_PRI_DEFAULT, GROUP1}, \ 101 } 102 103 #ifdef __cplusplus 104 } 105 #endif 106