1 /*
2 * include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
3 *
4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18 #ifndef _HDMI_TX_MODULE_H
19 #define _HDMI_TX_MODULE_H
20 #include "hdmi_info_global.h"
21 #include "hdmi_config.h"
22 #include "hdmi_tx_notify.h"
23 #include <linux/wait.h>
24 #include <linux/clk.h>
25 #include <linux/cdev.h>
26 #include <linux/clk-provider.h>
27 #include <linux/device.h>
28 #include <linux/pinctrl/consumer.h>
29
30 /* HDMITX driver version */
31 #define HDMITX_VER "20200122"
32
33 /* chip type */
34 #define MESON_CPU_ID_M8B 0
35 #define MESON_CPU_ID_GXBB 1
36 #define MESON_CPU_ID_GXTVBB 2
37 #define MESON_CPU_ID_GXL 3
38 #define MESON_CPU_ID_GXM 4
39 #define MESON_CPU_ID_TXL 5
40 #define MESON_CPU_ID_TXLX 6
41 #define MESON_CPU_ID_AXG 7
42 #define MESON_CPU_ID_GXLX 8
43 #define MESON_CPU_ID_TXHD 9
44 #define MESON_CPU_ID_G12A 10
45 #define MESON_CPU_ID_G12B 11
46 #define MESON_CPU_ID_SM1 12
47 #define MESON_CPU_ID_TM2 13
48 #define MESON_CPU_ID_TM2B 14
49
50
51 /*****************************
52 * hdmitx attr management
53 ******************************/
54
55 /************************************
56 * hdmitx device structure
57 *************************************/
58 /* VIC_MAX_VALID_MODE and VIC_MAX_NUM are associated with
59 * HDMITX_VIC420_OFFSET and HDMITX_VIC_MASK in hdmi_common.h
60 */
61 #define VIC_MAX_VALID_MODE 256 /* consider 4k2k */
62 /* half for valid vic, half for vic with y420*/
63 #define VIC_MAX_NUM 512
64 #define AUD_MAX_NUM 60
65 struct rx_audiocap {
66 unsigned char audio_format_code;
67 unsigned char channel_num_max;
68 unsigned char freq_cc;
69 unsigned char cc3;
70 };
71
72 #define MAX_RAW_LEN 64
73 struct raw_block {
74 int len;
75 char raw[MAX_RAW_LEN];
76 };
77
78 enum hd_ctrl {
79 VID_EN, VID_DIS, AUD_EN, AUD_DIS, EDID_EN, EDID_DIS, HDCP_EN, HDCP_DIS,
80 };
81
82 struct hdr_dynamic_struct {
83 unsigned int type;
84 unsigned int hd_len;/*hdr_dynamic_length*/
85 unsigned char support_flags;
86 unsigned char optional_fields[20];
87 };
88 #define VESA_MAX_TIMING 64
89
90 struct rx_cap {
91 unsigned int native_Mode;
92 /*video*/
93 unsigned int VIC[VIC_MAX_NUM];
94 unsigned int VIC_count;
95 unsigned int native_VIC;
96 enum hdmi_vic vesa_timing[VESA_MAX_TIMING]; /* Max 64 */
97 /*audio*/
98 struct rx_audiocap RxAudioCap[AUD_MAX_NUM];
99 unsigned char AUD_count;
100 unsigned char RxSpeakerAllocation;
101 /*vendor*/
102 unsigned int ieeeoui;
103 unsigned char Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */
104 unsigned int hf_ieeeoui; /* For HDMI Forum */
105 unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */
106 /* CEA861-F, Table 56, Colorimetry Data Block */
107 unsigned int colorimetry_data;
108 unsigned int scdc_present:1;
109 unsigned int scdc_rr_capable:1; /* SCDC read request */
110 unsigned int lte_340mcsc_scramble:1;
111 unsigned int dc_y444:1;
112 unsigned int dc_30bit:1;
113 unsigned int dc_36bit:1;
114 unsigned int dc_48bit:1;
115 unsigned int dc_30bit_420:1;
116 unsigned int dc_36bit_420:1;
117 unsigned int dc_48bit_420:1;
118 unsigned int max_frl_rate:4;
119 unsigned int fpap_start_loc:1;
120 unsigned int allm:1;
121 unsigned int cnc0:1; /* Graphics */
122 unsigned int cnc1:1; /* Photo */
123 unsigned int cnc2:1; /* Cinema */
124 unsigned int cnc3:1; /* Game */
125 unsigned int mdelta:1;
126 unsigned int fva:1;
127 unsigned int hdr_sup_eotf_sdr:1;
128 unsigned int hdr_sup_eotf_hdr:1;
129 unsigned int hdr_sup_eotf_smpte_st_2084:1;
130 unsigned int hdr_sup_eotf_hlg:1;
131 unsigned int hdr_sup_SMD_type1:1;
132 unsigned int hdmi2ver;
133 unsigned char hdr_lum_max;
134 unsigned char hdr_lum_avg;
135 unsigned char hdr_lum_min;
136 unsigned char hdr_rawdata[7];
137 struct hdr_dynamic_struct hdr_dynamic_info[4];
138 struct hdr10_plus_info hdr10plus_info;
139 unsigned char IDManufacturerName[4];
140 unsigned char IDProductCode[2];
141 unsigned char IDSerialNumber[4];
142 unsigned char ReceiverProductName[16];
143 unsigned char manufacture_week;
144 unsigned char manufacture_year;
145 unsigned char physcial_weight;
146 unsigned char physcial_height;
147 unsigned char edid_version;
148 unsigned char edid_revision;
149 unsigned char ColorDeepSupport;
150 unsigned int vLatency;
151 unsigned int aLatency;
152 unsigned int i_vLatency;
153 unsigned int i_aLatency;
154 unsigned int threeD_present;
155 unsigned int threeD_Multi_present;
156 unsigned int hdmi_vic_LEN;
157 unsigned int HDMI_3D_LEN;
158 unsigned int threeD_Structure_ALL_15_0;
159 unsigned int threeD_MASK_15_0;
160 struct {
161 unsigned char frame_packing;
162 unsigned char top_and_bottom;
163 unsigned char side_by_side;
164 } support_3d_format[VIC_MAX_NUM];
165 struct dv_info dv_info;
166 /* When hdr_priority is 1, then dv_info will be all 0
167 * And select HDR10 to DolbyVision from HDR priority,
168 * System won't get real dv_cap, but can get real dv_cap2
169 */
170 struct dv_info dv_info2;
171 enum hdmi_vic preferred_mode;
172 struct dtd dtd[16];
173 unsigned char dtd_idx;
174 unsigned char flag_vfpdb;
175 unsigned char number_of_dtd;
176 struct raw_block asd;
177 struct raw_block vsd;
178 /*blk0 check sum*/
179 unsigned char blk0_chksum;
180 unsigned char chksum[10];
181 };
182
183 struct cts_conftab {
184 unsigned int fixed_n;
185 unsigned int tmds_clk;
186 unsigned int fixed_cts;
187 };
188
189 struct vic_attrmap {
190 enum hdmi_vic VIC;
191 unsigned int tmds_clk;
192 };
193
194 enum hdmi_event_t {
195 HDMI_TX_NONE = 0,
196 HDMI_TX_HPD_PLUGIN = 1,
197 HDMI_TX_HPD_PLUGOUT = 2,
198 HDMI_TX_INTERNAL_INTR = 4,
199 };
200
201 struct hdmi_phy_t {
202 unsigned long reg;
203 unsigned long val_sleep;
204 unsigned long val_save;
205 };
206
207 struct audcts_log {
208 unsigned int val:20;
209 unsigned int stable:1;
210 };
211
212 struct frac_rate_table {
213 char *hz;
214 u32 sync_num_int;
215 u32 sync_den_int;
216 u32 sync_num_dec;
217 u32 sync_den_dec;
218 };
219
220 struct ced_cnt {
221 bool ch0_valid;
222 u16 ch0_cnt:15;
223 bool ch1_valid;
224 u16 ch1_cnt:15;
225 bool ch2_valid;
226 u16 ch2_cnt:15;
227 u8 chksum;
228 };
229
230 struct scdc_locked_st {
231 u8 clock_detected:1;
232 u8 ch0_locked:1;
233 u8 ch1_locked:1;
234 u8 ch2_locked:1;
235 };
236
237 enum hdmi_hdr_transfer {
238 T_UNKNOWN = 0,
239 T_BT709,
240 T_UNDEF,
241 T_BT601,
242 T_BT470M,
243 T_BT470BG,
244 T_SMPTE170M,
245 T_SMPTE240M,
246 T_LINEAR,
247 T_LOG100,
248 T_LOG316,
249 T_IEC61966_2_4,
250 T_BT1361E,
251 T_IEC61966_2_1,
252 T_BT2020_10,
253 T_BT2020_12,
254 T_SMPTE_ST_2084,
255 T_SMPTE_ST_28,
256 T_HLG,
257 };
258
259 enum hdmi_hdr_color {
260 C_UNKNOWN = 0,
261 C_BT709,
262 C_UNDEF,
263 C_BT601,
264 C_BT470M,
265 C_BT470BG,
266 C_SMPTE170M,
267 C_SMPTE240M,
268 C_FILM,
269 C_BT2020,
270 };
271
272 struct hdmitx_clk_tree_s {
273 /* hdmitx clk tree */
274 struct clk *hdmi_clk_vapb;
275 struct clk *hdmi_clk_vpu;
276 struct clk *hdcp22_tx_skp;
277 struct clk *hdcp22_tx_esm;
278 struct clk *venci_top_gate;
279 struct clk *venci_0_gate;
280 struct clk *venci_1_gate;
281 };
282
283 /* 2kB should be enough to record */
284 #define HDCP_LOG_SIZE (1024 * 2)
285 struct hdcplog_buf {
286 int idx;
287 unsigned char buf[HDCP_LOG_SIZE + 64]; /* padding 8 bytes */
288 };
289
290 enum hdcp_ver_e {
291 HDCPVER_NONE = 0,
292 HDCPVER_14,
293 HDCPVER_22,
294 };
295
296 #define MAX_KSV_LISTS 127
297 struct hdcprp14_topo {
298 unsigned char max_cascade_exceeded:1;
299 unsigned char depth:3;
300 unsigned char max_devs_exceeded:1;
301 unsigned char device_count:7; /* 1 ~ 127 */
302 unsigned char ksv_list[MAX_KSV_LISTS * 5];
303 };
304
305 struct hdcprp22_topo {
306 unsigned int depth;
307 unsigned int device_count;
308 unsigned int v1_X_device_down;
309 unsigned int v2_0_repeater_down;
310 unsigned int max_devs_exceeded;
311 unsigned int max_cascade_exceeded;
312 unsigned char id_num;
313 unsigned char id_lists[MAX_KSV_LISTS * 5];
314 };
315
316 struct hdcprp_topo {
317 /* hdcp_ver currently used */
318 enum hdcp_ver_e hdcp_ver;
319 union {
320 struct hdcprp14_topo topo14;
321 struct hdcprp22_topo topo22;
322 } topo;
323 };
324
325 #define EDID_MAX_BLOCK 4
326 #define HDMI_TMP_BUF_SIZE 1024
327 struct hdmitx_dev {
328 struct cdev cdev; /* The cdev structure */
329 dev_t hdmitx_id;
330 struct proc_dir_entry *proc_file;
331 struct task_struct *task;
332 struct task_struct *task_monitor;
333 struct task_struct *task_hdcp;
334 struct notifier_block nb;
335 struct workqueue_struct *hdmi_wq;
336 struct workqueue_struct *rxsense_wq;
337 struct workqueue_struct *cedst_wq;
338 struct device *hdtx_dev;
339 struct device *pdev; /* for pinctrl*/
340 struct pinctrl_state *pinctrl_i2c;
341 struct pinctrl_state *pinctrl_default;
342 struct delayed_work work_hpd_plugin;
343 struct delayed_work work_hpd_plugout;
344 struct delayed_work work_rxsense;
345 struct delayed_work work_internal_intr;
346 struct delayed_work work_cedst;
347 struct work_struct work_hdr;
348 struct delayed_work work_do_hdcp;
349 #ifdef CONFIG_AML_HDMI_TX_14
350 struct delayed_work cec_work;
351 #endif
352 struct timer_list hdcp_timer;
353 int chip_type;
354 int hdmi_init;
355 int hpdmode;
356 /* -1, no hdcp; 0, NULL; 1, 1.4; 2, 2.2 */
357 int hdcp_mode;
358 int hdcp_bcaps_repeater;
359 int ready; /* 1, hdmi stable output, others are 0 */
360 int hdcp_hpd_stick; /* 1 not init & reset at plugout */
361 int hdcp_tst_sig;
362 unsigned int div40;
363 unsigned int lstore;
364 struct {
365 void (*setpacket)(int type, unsigned char *DB,
366 unsigned char *HB);
367 void (*disablepacket)(int type);
368 /* In original setpacket, there are many policys, like
369 * if ((DB[4] >> 4) == T3D_FRAME_PACKING)
370 * Need a only pure data packet to call
371 */
372 void (*setdatapacket)(int type, unsigned char *DB,
373 unsigned char *HB);
374 void (*setaudioinfoframe)(unsigned char *AUD_DB,
375 unsigned char *CHAN_STAT_BUF);
376 int (*setdispmode)(struct hdmitx_dev *hdmitx_device);
377 int (*setaudmode)(struct hdmitx_dev *hdmitx_device,
378 struct hdmitx_audpara *audio_param);
379 void (*setupirq)(struct hdmitx_dev *hdmitx_device);
380 void (*debugfun)(struct hdmitx_dev *hdmitx_device,
381 const char *buf);
382 void (*uninit)(struct hdmitx_dev *hdmitx_device);
383 int (*cntlpower)(struct hdmitx_dev *hdmitx_device,
384 unsigned int cmd, unsigned int arg);
385 /* edid/hdcp control */
386 int (*cntlddc)(struct hdmitx_dev *hdmitx_device,
387 unsigned int cmd, unsigned long arg);
388 /* Audio/Video/System Status */
389 int (*getstate)(struct hdmitx_dev *hdmitx_device,
390 unsigned int cmd, unsigned int arg);
391 int (*cntlpacket)(struct hdmitx_dev *hdmitx_device,
392 unsigned int cmd,
393 unsigned int arg); /* Packet control */
394 int (*cntlconfig)(struct hdmitx_dev *hdmitx_device,
395 unsigned int cmd,
396 unsigned int arg); /* Configure control */
397 int (*cntlmisc)(struct hdmitx_dev *hdmitx_device,
398 unsigned int cmd, unsigned int arg);
399 int (*cntl)(struct hdmitx_dev *hdmitx_device, unsigned int cmd,
400 unsigned int arg); /* Other control */
401 } hwop;
402 struct {
403 unsigned int hdcp14_en;
404 unsigned int hdcp14_rslt;
405 } hdcpop;
406 struct hdmi_config_platform_data config_data;
407 enum hdmi_event_t hdmitx_event;
408 unsigned int irq_hpd;
409 /*EDID*/
410 unsigned int cur_edid_block;
411 unsigned int cur_phy_block_ptr;
412 unsigned char EDID_buf[EDID_MAX_BLOCK * 128];
413 unsigned char EDID_buf1[EDID_MAX_BLOCK*128]; /* for second read */
414 unsigned char tmp_edid_buf[128*EDID_MAX_BLOCK];
415 unsigned char *edid_ptr;
416 unsigned int edid_parsing; /* Indicator that RX edid data integrated */
417 unsigned char EDID_hash[20];
418 struct rx_cap rxcap;
419 struct hdmitx_vidpara *cur_video_param;
420 int vic_count;
421 struct hdmitx_clk_tree_s hdmitx_clk_tree;
422 /*audio*/
423 struct hdmitx_audpara cur_audio_param;
424 int audio_param_update_flag;
425 unsigned char unplug_powerdown;
426 unsigned short physical_addr;
427 unsigned int cur_VIC;
428 char fmt_attr[16];
429 atomic_t kref_video_mute;
430 atomic_t kref_audio_mute;
431 /**/
432 unsigned char hpd_event; /* 1, plugin; 2, plugout */
433 unsigned char hpd_state; /* 1, connect; 0, disconnect */
434 unsigned char drm_mode_setting; /* 1, setting; 0, keeping */
435 unsigned char rhpd_state; /* For repeater use only, no delay */
436 unsigned char hdcp_max_exceed_state;
437 unsigned int hdcp_max_exceed_cnt;
438 unsigned char force_audio_flag;
439 unsigned char mux_hpd_if_pin_high_flag;
440 int auth_process_timer;
441 struct hdmitx_info hdmi_info;
442 unsigned char tmp_buf[HDMI_TMP_BUF_SIZE];
443 unsigned int log;
444 unsigned int tx_aud_cfg; /* 0, off; 1, on */
445 /* For some un-well-known TVs, no edid at all */
446 unsigned int tv_no_edid;
447 unsigned int hpd_lock;
448 struct hdmi_format_para *para;
449 /* 0: RGB444 1: Y444 2: Y422 3: Y420 */
450 /* 4: 24bit 5: 30bit 6: 36bit 7: 48bit */
451 /* if equals to 1, means current video & audio output are blank */
452 unsigned int output_blank_flag;
453 unsigned int audio_notify_flag;
454 unsigned int audio_step;
455 bool hdcp22_type;
456 unsigned int repeater_tx;
457 struct hdcprp_topo *topo_info;
458 /* 0.1% clock shift, 1080p60hz->59.94hz */
459 unsigned int frac_rate_policy;
460 unsigned int rxsense_policy;
461 unsigned int cedst_policy;
462 struct ced_cnt ced_cnt;
463 struct scdc_locked_st chlocked_st;
464 unsigned int allm_mode; /* allm_mode: 1/on 0/off */
465 unsigned int ct_mode; /* 0/off 1/game, 2/graphcis, 3/photo, 4/cinema */
466 unsigned int sspll;
467 /* if HDMI plugin even once time, then set 1 */
468 /* if never hdmi plugin, then keep as 0 */
469 unsigned int already_used;
470 /* configure for I2S: 8ch in, 2ch out */
471 /* 0: default setting 1:ch0/1 2:ch2/3 3:ch4/5 4:ch6/7 */
472 unsigned int aud_output_ch;
473 unsigned int hdmi_ch;
474 unsigned int tx_aud_src; /* 0: SPDIF 1: I2S */
475 /* if set to 1, then HDMI will output no audio */
476 /* In KTV case, HDMI output Picture only, and Audio is driven by other
477 * sources.
478 */
479 unsigned char hdmi_audio_off_flag;
480 enum hdmi_hdr_transfer hdr_transfer_feature;
481 enum hdmi_hdr_color hdr_color_feature;
482 /* 0: sdr 1:standard HDR 2:non standard 3:HLG*/
483 unsigned int colormetry;
484 unsigned int hdmi_last_hdr_mode;
485 unsigned int hdmi_current_hdr_mode;
486 unsigned int dv_src_feature;
487 unsigned int sdr_hdr_feature;
488 unsigned int hdr10plus_feature;
489 enum eotf_type hdmi_current_eotf_type;
490 enum mode_type hdmi_current_tunnel_mode;
491 unsigned int flag_3dfp:1;
492 unsigned int flag_3dtb:1;
493 unsigned int flag_3dss:1;
494 unsigned int dongle_mode:1;
495 unsigned int cedst_en:1; /* configure in DTS */
496 unsigned int hdr_priority:1;
497 unsigned int bist_lock:1;
498 unsigned int drm_feature;/*Direct Rander Management*/
499 };
500
501 #define CMD_DDC_OFFSET (0x10 << 24)
502 #define CMD_STATUS_OFFSET (0x11 << 24)
503 #define CMD_PACKET_OFFSET (0x12 << 24)
504 #define CMD_MISC_OFFSET (0x13 << 24)
505 #define CMD_CONF_OFFSET (0x14 << 24)
506 #define CMD_STAT_OFFSET (0x15 << 24)
507
508 /***********************************************************************
509 * DDC CONTROL //cntlddc
510 **********************************************************************/
511 #define DDC_RESET_EDID (CMD_DDC_OFFSET + 0x00)
512 #define DDC_RESET_HDCP (CMD_DDC_OFFSET + 0x01)
513 #define DDC_HDCP_OP (CMD_DDC_OFFSET + 0x02)
514 #define HDCP14_ON 0x1
515 #define HDCP14_OFF 0x2
516 #define HDCP22_ON 0x3
517 #define HDCP22_OFF 0x4
518 #define DDC_IS_HDCP_ON (CMD_DDC_OFFSET + 0x04)
519 #define DDC_HDCP_GET_AKSV (CMD_DDC_OFFSET + 0x05)
520 #define DDC_HDCP_GET_BKSV (CMD_DDC_OFFSET + 0x06)
521 #define DDC_HDCP_GET_AUTH (CMD_DDC_OFFSET + 0x07)
522 #define DDC_PIN_MUX_OP (CMD_DDC_OFFSET + 0x08)
523 #define PIN_MUX 0x1
524 #define PIN_UNMUX 0x2
525 #define DDC_EDID_READ_DATA (CMD_DDC_OFFSET + 0x0a)
526 #define DDC_IS_EDID_DATA_READY (CMD_DDC_OFFSET + 0x0b)
527 #define DDC_EDID_GET_DATA (CMD_DDC_OFFSET + 0x0c)
528 #define DDC_EDID_CLEAR_RAM (CMD_DDC_OFFSET + 0x0d)
529 #define DDC_HDCP_MUX_INIT (CMD_DDC_OFFSET + 0x0e)
530 #define DDC_HDCP_14_LSTORE (CMD_DDC_OFFSET + 0x0f)
531 #define DDC_HDCP_22_LSTORE (CMD_DDC_OFFSET + 0x10)
532 #define DDC_GLITCH_FILTER_RESET (CMD_DDC_OFFSET + 0x11)
533 #define DDC_SCDC_DIV40_SCRAMB (CMD_DDC_OFFSET + 0x20)
534 #define DDC_HDCP14_GET_BCAPS_RP (CMD_DDC_OFFSET + 0x30)
535 #define DDC_HDCP14_GET_TOPO_INFO (CMD_DDC_OFFSET + 0x31)
536 #define DDC_HDCP_SET_TOPO_INFO (CMD_DDC_OFFSET + 0x32)
537 #define DDC_HDCP14_SAVE_OBS (CMD_DDC_OFFSET + 0x40)
538
539 /***********************************************************************
540 * CONFIG CONTROL //cntlconfig
541 **********************************************************************/
542 /* Video part */
543 #define CONF_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x02)
544 #define HDMI_MODE 0x1
545 #define DVI_MODE 0x2
546 #define CONF_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x00)
547 #define CLR_AVI_BT2020 0x0
548 #define SET_AVI_BT2020 0x1
549 /* set value as COLORSPACE_RGB444, YUV422, YUV444, YUV420 */
550 #define CONF_AVI_RGBYCC_INDIC (CMD_CONF_OFFSET + 0X2000 + 0x01)
551 #define CONF_AVI_Q01 (CMD_CONF_OFFSET + 0X2000 + 0x02)
552 #define RGB_RANGE_DEFAULT 0
553 #define RGB_RANGE_LIM 1
554 #define RGB_RANGE_FUL 2
555 #define RGB_RANGE_RSVD 3
556 #define CONF_AVI_YQ01 (CMD_CONF_OFFSET + 0X2000 + 0x03)
557 #define YCC_RANGE_LIM 0
558 #define YCC_RANGE_FUL 1
559 #define YCC_RANGE_RSVD 2
560 #define CONF_CT_MODE (CMD_CONF_OFFSET + 0X2000 + 0x04)
561 #define SET_CT_OFF 0
562 #define SET_CT_GAME 1
563 #define SET_CT_GRAPHICS 2
564 #define SET_CT_PHOTO 3
565 #define SET_CT_CINEMA 4
566 #define CONF_VIDEO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x04)
567 #define VIDEO_MUTE 0x1
568 #define VIDEO_UNMUTE 0x2
569 #define CONF_EMP_NUMBER (CMD_CONF_OFFSET + 0x3000 + 0x00)
570 #define CONF_EMP_PHY_ADDR (CMD_CONF_OFFSET + 0x3000 + 0x01)
571
572 /* Audio part */
573 #define CONF_CLR_AVI_PACKET (CMD_CONF_OFFSET + 0x04)
574 #define CONF_CLR_VSDB_PACKET (CMD_CONF_OFFSET + 0x05)
575 #define CONF_VIDEO_MAPPING (CMD_CONF_OFFSET + 0x06)
576 #define CONF_GET_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x07)
577
578 #define CONF_AUDIO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x00)
579 #define AUDIO_MUTE 0x1
580 #define AUDIO_UNMUTE 0x2
581 #define CONF_CLR_AUDINFO_PACKET (CMD_CONF_OFFSET + 0x1000 + 0x01)
582
583 /***********************************************************************
584 * MISC control, hpd, hpll //cntlmisc
585 **********************************************************************/
586 #define MISC_HPD_MUX_OP (CMD_MISC_OFFSET + 0x00)
587 #define MISC_HPD_GPI_ST (CMD_MISC_OFFSET + 0x02)
588 #define MISC_HPLL_OP (CMD_MISC_OFFSET + 0x03)
589 #define HPLL_ENABLE 0x1
590 #define HPLL_DISABLE 0x2
591 #define HPLL_SET 0x3
592 #define MISC_TMDS_PHY_OP (CMD_MISC_OFFSET + 0x04)
593 #define TMDS_PHY_ENABLE 0x1
594 #define TMDS_PHY_DISABLE 0x2
595 #define MISC_VIID_IS_USING (CMD_MISC_OFFSET + 0x05)
596 #define MISC_CONF_MODE420 (CMD_MISC_OFFSET + 0x06)
597 #define MISC_TMDS_CLK_DIV40 (CMD_MISC_OFFSET + 0x07)
598 #define MISC_COMP_HPLL (CMD_MISC_OFFSET + 0x08)
599 #define COMP_HPLL_SET_OPTIMISE_HPLL1 0x1
600 #define COMP_HPLL_SET_OPTIMISE_HPLL2 0x2
601 #define MISC_COMP_AUDIO (CMD_MISC_OFFSET + 0x09)
602 #define COMP_AUDIO_SET_N_6144x2 0x1
603 #define COMP_AUDIO_SET_N_6144x3 0x2
604 #define MISC_AVMUTE_OP (CMD_MISC_OFFSET + 0x0a)
605 #define MISC_FINE_TUNE_HPLL (CMD_MISC_OFFSET + 0x0b)
606 #define OFF_AVMUTE 0x0
607 #define CLR_AVMUTE 0x1
608 #define SET_AVMUTE 0x2
609 #define MISC_HPLL_FAKE (CMD_MISC_OFFSET + 0x0c)
610 #define MISC_ESM_RESET (CMD_MISC_OFFSET + 0x0d)
611 #define MISC_HDCP_CLKDIS (CMD_MISC_OFFSET + 0x0e)
612 #define MISC_TMDS_RXSENSE (CMD_MISC_OFFSET + 0x0f)
613 #define MISC_I2C_REACTIVE (CMD_MISC_OFFSET + 0x10) /* For gxl */
614 #define MISC_I2C_RESET (CMD_MISC_OFFSET + 0x11) /* For g12 */
615 #define MISC_READ_AVMUTE_OP (CMD_MISC_OFFSET + 0x12)
616 #define MISC_TMDS_CEDST (CMD_MISC_OFFSET + 0x13)
617 #define MISC_TRIGGER_HPD (CMD_MISC_OFFSET + 0X14)
618 #define MISC_SUSFLAG (CMD_MISC_OFFSET + 0X15)
619
620 /***********************************************************************
621 * Get State //getstate
622 **********************************************************************/
623 #define STAT_VIDEO_VIC (CMD_STAT_OFFSET + 0x00)
624 #define STAT_VIDEO_CLK (CMD_STAT_OFFSET + 0x01)
625 #define STAT_AUDIO_FORMAT (CMD_STAT_OFFSET + 0x10)
626 #define STAT_AUDIO_CHANNEL (CMD_STAT_OFFSET + 0x11)
627 #define STAT_AUDIO_CLK_STABLE (CMD_STAT_OFFSET + 0x12)
628 #define STAT_AUDIO_PACK (CMD_STAT_OFFSET + 0x13)
629 #define STAT_HDR_TYPE (CMD_STAT_OFFSET + 0x20)
630
631
632 /* HDMI LOG */
633 #define HDMI_LOG_HDCP (1 << 0)
634
635 #define HDMI_SOURCE_DESCRIPTION 0
636 #define HDMI_PACKET_VEND 1
637 #define HDMI_MPEG_SOURCE_INFO 2
638 #define HDMI_PACKET_AVI 3
639 #define HDMI_AUDIO_INFO 4
640 #define HDMI_AUDIO_CONTENT_PROTECTION 5
641 #define HDMI_PACKET_HBR 6
642 #define HDMI_PACKET_DRM 0x86
643
644 #define HDMI_PROCESS_DELAY msleep(10)
645 /* reduce a little time, previous setting is 4000/10 */
646 #define AUTH_PROCESS_TIME (1000/100)
647
648 /***********************************************************************
649 * hdmitx protocol level interface
650 **********************************************************************/
651 extern enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode);
652
653 extern int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device);
654 extern int check_dvi_hdmi_edid_valid(unsigned char *buf);
655
656 enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdmitx_device,
657 const char *disp_mode, char force_flag);
658
659 extern int hdmitx_edid_VIC_support(enum hdmi_vic vic);
660
661 extern int hdmitx_edid_dump(struct hdmitx_dev *hdmitx_device, char *buffer,
662 int buffer_len);
663 bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
664 struct hdmi_format_para *para);
665 const char *hdmitx_edid_vic_tab_map_string(enum hdmi_vic vic);
666 extern const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic);
667 extern void hdmitx_edid_clear(struct hdmitx_dev *hdmitx_device);
668
669 extern void hdmitx_edid_ram_buffer_clear(struct hdmitx_dev *hdmitx_device);
670
671 extern void hdmitx_edid_buf_compare_print(struct hdmitx_dev *hdmitx_device);
672
673 extern const char *hdmitx_edid_get_native_VIC(struct hdmitx_dev *hdmitx_device);
674
675 extern struct hdmitx_audpara hdmiaud_config_data;
676 extern struct hdmitx_audpara hsty_hdmiaud_config_data[8];
677 extern unsigned int hsty_hdmiaud_config_loc, hsty_hdmiaud_config_num;
678
679 /* VSIF: Vendor Specific InfoFrame
680 * It has multiple purposes:
681 * 1. HDMI1.4 4K, HDMI_VIC=1/2/3/4, 2160p30/25/24hz, smpte24hz, AVI.VIC=0
682 * In CTA-861-G, matched with AVI.VIC=95/94/93/98
683 * 2. 3D application, TB/SS/FP
684 * 3. DolbyVision, with Len=0x18
685 * 4. HDR10plus
686 * 5. HDMI20 3D OSD disparity / 3D dual-view / 3D independent view / ALLM
687 * Some functions are exclusive, but some may compound.
688 * Consider various state transitions carefully, such as play 3D under HDMI14
689 * 4K, exit 3D under 4K, play DV under 4K, enable ALLM under 3D dual-view
690 */
691 enum vsif_type {
692 /* Below 4 functions are exclusive */
693 VT_HDMI14_4K = 1,
694 VT_T3D_VIDEO,
695 VT_DOLBYVISION,
696 VT_HDR10PLUS,
697 /* Maybe compound 3D dualview + ALLM */
698 VT_T3D_OSD_DISPARITY = 0x10,
699 VT_T3D_DUALVIEW,
700 VT_T3D_INDEPENDVEW,
701 VT_ALLM,
702 /* default: if non-HDMI4K, no any vsif; if HDMI4k, = VT_HDMI14_4K */
703 VT_DEFAULT,
704 VT_MAX,
705 };
706 int hdmitx_construct_vsif(struct hdmitx_dev *hdev, enum vsif_type type, int on,
707 void *param);
708
709 /* if vic is 93 ~ 95, or 98 (HDMI14 4K), return 1 */
710 bool is_hdmi14_4k(enum hdmi_vic vic);
711
712 /* if 4k is Y420, return 1 */
713 bool is_hdmi4k_420(enum hdmi_vic vic);
714
715 /* set vic to AVI.VIC */
716 void hdmitx_set_avi_vic(enum hdmi_vic vic);
717
718 /*
719 * HDMI Repeater TX I/F
720 * RX downstream Information from rptx to rprx
721 */
722 /* send part raw edid from TX to RX */
723 extern void rx_repeat_hpd_state(unsigned int st);
724 /* prevent compile error in no HDMIRX case */
rx_repeat_hpd_state(unsigned int st)725 void __attribute__((weak))rx_repeat_hpd_state(unsigned int st)
726 {
727 }
728
729 extern void rx_edid_physical_addr(unsigned char a, unsigned char b,
730 unsigned char c, unsigned char d);
rx_edid_physical_addr(unsigned char a,unsigned char b,unsigned char c,unsigned char d)731 void __attribute__((weak))rx_edid_physical_addr(unsigned char a,
732 unsigned char b, unsigned char c, unsigned char d)
733 {
734 }
735
736 extern int rx_set_hdr_lumi(unsigned char *data, int len);
rx_set_hdr_lumi(unsigned char * data,int len)737 int __attribute__((weak))rx_set_hdr_lumi(unsigned char *data, int len)
738 {
739 return 0;
740 }
741
742 extern void rx_set_repeater_support(bool enable);
rx_set_repeater_support(bool enable)743 void __attribute__((weak))rx_set_repeater_support(bool enable)
744 {
745 }
746
747 extern void rx_set_receiver_edid(unsigned char *data, int len);
rx_set_receiver_edid(unsigned char * data,int len)748 void __attribute__((weak))rx_set_receiver_edid(unsigned char *data, int len)
749 {
750 }
751
752 extern void rx_set_receive_hdcp(unsigned char *data, int len, int depth,
753 bool max_cascade, bool max_devs);
rx_set_receive_hdcp(unsigned char * data,int len,int depth,bool max_cascade,bool max_devs)754 void __attribute__((weak))rx_set_receive_hdcp(unsigned char *data, int len,
755 int depth, bool max_cascade, bool max_devs)
756 {
757 }
758
759 extern int hdmitx_set_display(struct hdmitx_dev *hdmitx_device,
760 enum hdmi_vic VideoCode);
761
762 extern int hdmi_set_3d(struct hdmitx_dev *hdmitx_device, int type,
763 unsigned int param);
764
765 extern int hdmitx_set_audio(struct hdmitx_dev *hdmitx_device,
766 struct hdmitx_audpara *audio_param);
767
768
769 #ifdef CONFIG_AMLOGIC_HDMITX
770 extern struct hdmitx_dev *get_hdmitx_device(void);
771 extern int get_hpd_state(void);
772 extern void hdmitx_hdcp_status(int hdmi_authenticated);
773 #else
get_hdmitx_device(void)774 static inline struct hdmitx_dev *get_hdmitx_device(void)
775 {
776 return NULL;
777 }
get_hpd_state(void)778 static inline int get_hpd_state(void)
779 {
780 return 0;
781 }
hdmitx_event_notifier_regist(struct notifier_block * nb)782 static inline int hdmitx_event_notifier_regist(struct notifier_block *nb)
783 {
784 return -EINVAL;
785 }
786
hdmitx_event_notifier_unregist(struct notifier_block * nb)787 static inline int hdmitx_event_notifier_unregist(struct notifier_block *nb)
788 {
789 return -EINVAL;
790 }
791 #endif
792
793 extern void hdmi_set_audio_para(int para);
794 extern int get_cur_vout_index(void);
795 extern void phy_pll_off(void);
796 extern int get_hpd_state(void);
797 extern void hdmitx_hdcp_do_work(struct hdmitx_dev *hdev);
798
799 /***********************************************************************
800 * hdmitx hardware level interface
801 ***********************************************************************/
802 extern void HDMITX_Meson_Init(struct hdmitx_dev *hdmitx_device);
803 extern unsigned int get_hdcp22_base(void);
804 /*
805 * hdmitx_audio_mute_op() is used by external driver call
806 * flag: 0: audio off 1: audio_on
807 * 2: for EDID auto mode
808 */
809 extern void hdmitx_audio_mute_op(unsigned int flag);
810 extern void hdmitx_video_mute_op(unsigned int flag);
811
812 /*
813 * HDMITX HPD HW related operations
814 */
815 enum hpd_op {
816 HPD_INIT_DISABLE_PULLUP,
817 HPD_INIT_SET_FILTER,
818 HPD_IS_HPD_MUXED,
819 HPD_MUX_HPD,
820 HPD_UNMUX_HPD,
821 HPD_READ_HPD_GPIO,
822 };
823 extern int hdmitx_hpd_hw_op(enum hpd_op cmd);
824 /*
825 * HDMITX DDC HW related operations
826 */
827 enum ddc_op {
828 DDC_INIT_DISABLE_PULL_UP_DN,
829 DDC_MUX_DDC,
830 DDC_UNMUX_DDC,
831 };
832 extern int hdmitx_ddc_hw_op(enum ddc_op cmd);
833
834 #define HDMITX_HWCMD_MUX_HPD_IF_PIN_HIGH 0x3
835 #define HDMITX_HWCMD_TURNOFF_HDMIHW 0x4
836 #define HDMITX_HWCMD_MUX_HPD 0x5
837 #define HDMITX_HWCMD_PLL_MODE 0x6
838 #define HDMITX_HWCMD_TURN_ON_PRBS 0x7
839 #define HDMITX_FORCE_480P_CLK 0x8
840 #define HDMITX_GET_AUTHENTICATE_STATE 0xa
841 #define HDMITX_SW_INTERNAL_HPD_TRIG 0xb
842 #define HDMITX_HWCMD_OSD_ENABLE 0xf
843
844 #define HDMITX_HDCP_MONITOR 0x11
845 #define HDMITX_IP_INTR_MASN_RST 0x12
846 #define HDMITX_EARLY_SUSPEND_RESUME_CNTL 0x14
847 #define HDMITX_EARLY_SUSPEND 0x1
848 #define HDMITX_LATE_RESUME 0x2
849 /* Refer to HDMI_OTHER_CTRL0 in hdmi_tx_reg.h */
850 #define HDMITX_IP_SW_RST 0x15
851 #define TX_CREG_SW_RST (1<<5)
852 #define TX_SYS_SW_RST (1<<4)
853 #define CEC_CREG_SW_RST (1<<3)
854 #define CEC_SYS_SW_RST (1<<2)
855 #define HDMITX_AVMUTE_CNTL 0x19
856 #define AVMUTE_SET 0 /* set AVMUTE to 1 */
857 #define AVMUTE_CLEAR 1 /* set AVunMUTE to 1 */
858 #define AVMUTE_OFF 2 /* set both AVMUTE and AVunMUTE to 0 */
859 #define HDMITX_CBUS_RST 0x1A
860 #define HDMITX_INTR_MASKN_CNTL 0x1B
861 #define INTR_MASKN_ENABLE 0
862 #define INTR_MASKN_DISABLE 1
863 #define INTR_CLEAR 2
864
865 #define HDMI_HDCP_DELAYTIME_AFTER_DISPLAY 20 /* unit: ms */
866
867 #define HDMITX_HDCP_MONITOR_BUF_SIZE 1024
868 struct Hdcp_Sub {
869 char *hdcp_sub_name;
870 unsigned int hdcp_sub_addr_start;
871 unsigned int hdcp_sub_len;
872 };
873 extern void setup_attr(const char *buf);
874 extern void get_attr(char attr[16]);
875 extern void setup_drm_hdmi_hpd(unsigned char hpd_state);
876 extern void setup_drm_mode_setting(unsigned char drm_mode_setting);
877 extern unsigned int hd_read_reg(unsigned int addr);
878 extern void hd_write_reg(unsigned int addr, unsigned int val);
879 extern void hd_set_reg_bits(unsigned int addr, unsigned int value,
880 unsigned int offset, unsigned int len);
881 extern void hdmitx_wr_reg(unsigned int addr, unsigned int data);
882 extern void hdmitx_poll_reg(unsigned int addr, unsigned int val,
883 unsigned long timeout);
884 extern void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
885 unsigned int offset, unsigned int len);
886 extern unsigned int hdmitx_rd_reg(unsigned int addr);
887 extern unsigned int hdmitx_rd_check_reg(unsigned int addr,
888 unsigned int exp_data,
889 unsigned int mask);
890 extern void vsem_init_cfg(struct hdmitx_dev *hdev);
891
892 #endif
893