1 /* 2 * drivers/amlogic/amports/jpegenc.h 3 * 4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef __JPEG_ENC_H_ 19 #define __JPEG_ENC_H_ 20 21 #define JPEGENC_DEVINFO_M8 "AML-M8" 22 #define JPEGENC_DEVINFO_G9 "AML-G9" 23 #define JPEGENC_DEVINFO_GXBB "AML-GXBB" 24 #define JPEGENC_DEVINFO_GXTVBB "AML-GXTVBB" 25 #define JPEGENC_DEVINFO_GXL "AML-GXL" 26 27 /* M8: 2550/10 = 255M GX: 2000/10 = 200M */ 28 #define JPEGENC_HDEC_L0() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 29 (2 << 25) | (1 << 16) | (1 << 24) | \ 30 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 31 /* M8: 2550/8 = 319M GX: 2000/8 = 250M */ 32 #define JPEGENC_HDEC_L1() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 33 (0 << 25) | (1 << 16) | (1 << 24) | \ 34 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 35 /* M8: 2550/7 = 364M GX: 2000/7 = 285M */ 36 #define JPEGENC_HDEC_L2() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 37 (3 << 25) | (0 << 16) | (1 << 24) | \ 38 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 39 /* M8: 2550/6 = 425M GX: 2000/6 = 333M */ 40 #define JPEGENC_HDEC_L3() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 41 (1 << 25) | (1 << 16) | (1 << 24) | \ 42 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 43 /* M8: 2550/5 = 510M GX: 2000/5 = 400M */ 44 #define JPEGENC_HDEC_L4() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 45 (2 << 25) | (0 << 16) | (1 << 24) | \ 46 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 47 /* M8: 2550/4 = 638M GX: 2000/4 = 500M */ 48 #define JPEGENC_HDEC_L5() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 49 (0 << 25) | (0 << 16) | (1 << 24) | \ 50 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 51 /* M8: 2550/3 = 850M GX: 2000/3 = 667M */ 52 #define JPEGENC_HDEC_L6() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ 53 (1 << 25) | (0 << 16) | (1 << 24) | \ 54 (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) 55 56 #define jpegenc_clock_enable(level) \ 57 do { \ 58 if (level == 0) \ 59 JPEGENC_HDEC_L0(); \ 60 else if (level == 1) \ 61 JPEGENC_HDEC_L1(); \ 62 else if (level == 2) \ 63 JPEGENC_HDEC_L2(); \ 64 else if (level == 3) \ 65 JPEGENC_HDEC_L3(); \ 66 else if (level == 4) \ 67 JPEGENC_HDEC_L4(); \ 68 else if (level == 5) \ 69 JPEGENC_HDEC_L5(); \ 70 else if (level == 6) \ 71 JPEGENC_HDEC_L6(); \ 72 WRITE_VREG_BITS(DOS_GCLK_EN0, 0x7fff, 12, 15); \ 73 } while (0) 74 75 #define jpegenc_clock_disable() \ 76 do { \ 77 WRITE_VREG_BITS(DOS_GCLK_EN0, 0, 12, 15); \ 78 WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 0, 24, 1); \ 79 } while (0) 80 81 #define JPEGENC_IOC_MAGIC 'J' 82 83 #define JPEGENC_IOC_GET_DEVINFO _IOW(JPEGENC_IOC_MAGIC, 0xf0, u32) 84 85 #define JPEGENC_IOC_GET_BUFFINFO _IOW(JPEGENC_IOC_MAGIC, 0x00, u32) 86 #define JPEGENC_IOC_CONFIG_INIT _IOW(JPEGENC_IOC_MAGIC, 0x01, u32) 87 #define JPEGENC_IOC_NEW_CMD _IOW(JPEGENC_IOC_MAGIC, 0x02, u32) 88 #define JPEGENC_IOC_GET_STAGE _IOW(JPEGENC_IOC_MAGIC, 0x03, u32) 89 #define JPEGENC_IOC_GET_OUTPUT_SIZE _IOW(JPEGENC_IOC_MAGIC, 0x04, u32) 90 #define JPEGENC_IOC_SET_EXT_QUANT_TABLE _IOW(JPEGENC_IOC_MAGIC, 0x05, u32) 91 92 #define DCTSIZE2 64 93 94 #define JPEGENC_FLUSH_FLAG_INPUT 0x1 95 #define JPEGENC_FLUSH_FLAG_OUTPUT 0x2 96 97 /* Define Quantization table: Max two tables */ 98 #define QUANT_SEL_COMP0 0 99 #define QUANT_SEL_COMP1 1 100 #define QUANT_SEL_COMP2 1 101 102 /* Define Huffman table selection: Max two tables per DC/AC */ 103 #define DC_HUFF_SEL_COMP0 0 104 #define DC_HUFF_SEL_COMP1 1 105 #define DC_HUFF_SEL_COMP2 1 106 #define AC_HUFF_SEL_COMP0 0 107 #define AC_HUFF_SEL_COMP1 1 108 #define AC_HUFF_SEL_COMP2 1 109 110 /* DCT interrupt select:0=Disable intr; 111 1=Intr at end of each 8x8 block of DCT input; 112 2=Intr at end of each MCU of DCT input; 113 3=Intr at end of a scan of DCT input; 114 4=Intr at end of each 8x8 block of DCT output; 115 5=Intr at end of each MCU of DCT output; 116 6=Intr at end of a scan of DCT output; */ 117 #define JDCT_INTR_SEL 0 118 119 /* 0=Mark last coeff at the end of an 8x8 block, 120 1=Mark last coeff at the end of an MCU 121 2=Mark last coeff at the end of a scan */ 122 #define JDCT_LASTCOEFF_SEL 1 123 124 enum jpegenc_mem_type_e { 125 JPEGENC_LOCAL_BUFF = 0, 126 JPEGENC_CANVAS_BUFF, 127 JPEGENC_PHYSICAL_BUFF, 128 JPEGENC_MAX_BUFF_TYPE 129 }; 130 131 enum jpegenc_frame_fmt_e { 132 JPEGENC_FMT_YUV422_SINGLE = 0, 133 JPEGENC_FMT_YUV444_SINGLE, 134 JPEGENC_FMT_NV21, 135 JPEGENC_FMT_NV12, 136 JPEGENC_FMT_YUV420, 137 JPEGENC_FMT_YUV444_PLANE, 138 JPEGENC_FMT_RGB888, 139 JPEGENC_FMT_RGB888_PLANE, 140 JPEGENC_FMT_RGB565, 141 JPEGENC_FMT_RGBA8888, 142 JPEGENC_FMT_YUV422_12BIT, 143 JPEGENC_FMT_YUV444_10BIT, 144 JPEGENC_FMT_YUV422_10BIT, 145 JPEGENC_MAX_FRAME_FMT 146 }; 147 148 struct Jpegenc_Buff_s { 149 u32 buf_start; 150 u32 buf_size; 151 }; 152 153 struct Jpegenc_BuffInfo_s { 154 u32 lev_id; 155 u32 max_width; 156 u32 max_height; 157 u32 min_buffsize; 158 struct Jpegenc_Buff_s input; 159 struct Jpegenc_Buff_s assit; 160 struct Jpegenc_Buff_s bitstream; 161 }; 162 163 struct jpegenc_request_s { 164 u32 src; 165 u32 encoder_width; 166 u32 encoder_height; 167 u32 framesize; 168 u32 jpeg_quality; 169 u32 QuantTable_id; 170 u32 flush_flag; 171 enum jpegenc_mem_type_e type; 172 enum jpegenc_frame_fmt_e input_fmt; 173 enum jpegenc_frame_fmt_e output_fmt; 174 }; 175 176 struct jpegenc_meminfo_s { 177 u32 buf_start; 178 u32 buf_size; 179 u8 cur_buf_lev; 180 181 #ifdef CONFIG_CMA 182 ulong cma_pool_size; 183 #endif 184 struct Jpegenc_Buff_s reserve_mem; 185 struct Jpegenc_BuffInfo_s *bufspec; 186 }; 187 188 struct jpegenc_wq_s { 189 u32 hw_status; 190 u32 headbytes; 191 u32 output_size; 192 193 u32 buf_start; 194 u32 buf_size; 195 196 u32 InputBuffStart; 197 u32 InputBuffEnd; 198 199 u32 AssitStart; 200 u32 AssitEnd; 201 202 u32 BitstreamStart; 203 u32 BitstreamEnd; 204 void __iomem *AssitstreamStartVirtAddr; 205 206 u32 max_width; 207 u32 max_height; 208 209 struct jpegenc_request_s cmd; 210 atomic_t ready; 211 wait_queue_head_t complete; 212 #ifdef CONFIG_CMA 213 struct page *venc_pages; 214 #endif 215 }; 216 217 struct jpegenc_manager_s { 218 u32 encode_hw_status; 219 s32 irq_num; 220 221 bool irq_requested; 222 bool process_irq; 223 bool inited; 224 bool use_reserve; 225 u8 opened; 226 227 spinlock_t sem_lock; 228 struct platform_device *this_pdev; 229 struct jpegenc_meminfo_s mem; 230 struct jpegenc_wq_s wq; 231 struct tasklet_struct tasklet; 232 }; 233 234 /******************************************** 235 * AV Scratch Register Re-Define 236 ********************************************/ 237 #define JPEGENC_ENCODER_STATUS HCODEC_HENC_SCRATCH_0 238 #define JPEGENC_BITSTREAM_OFFSET HCODEC_HENC_SCRATCH_1 239 240 /********************************************* 241 * ENCODER_STATUS define 242 ********************************************/ 243 #define JPEGENC_ENCODER_IDLE 0 244 #define JPEGENC_ENCODER_START 1 245 /* #define JPEGENC_ENCODER_SOS_HEADER 2 */ 246 #define JPEGENC_ENCODER_MCU 3 247 #define JPEGENC_ENCODER_DONE 4 248 249 extern bool jpegenc_on(void); 250 #endif 251