1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef _LOG_DEF_STACK_H_ 19 #define _LOG_DEF_STACK_H_ 20 21 // event: 0 for time stamp; 1 reserved; eid2 - eid31 22 #define SLEV_timestamp 0 23 #define SLEV_reserved 1 24 #define SLEV_slot 2 25 #define SLEV_btrx 3 26 #define SLEV_set_clkn_fcnt 4 27 #define SLEV_rx_lmp 5 28 #define SLEV_rx_acl 6 29 #define SLEV_tx_tgl 7 30 #define SLEV_host_conn_req 8 31 #define SLEV_set_em 9 32 #define SLEV_rx_end 10 33 #define SLEV_tx_lmp 11 34 #define SLEV_tx_acl 12 35 #define SLEV_tx_lmp_full 13 36 #define SLEV_tx_acl_full 14 37 #define SLEV_tx_hci_full 15 38 #define SLEV_sniff_slot_start 16 39 #define SLEV_sniff_sub_slot_update 17 40 #define SLEV_sniff_sub_start 18 41 #define SLEV_sniff_transition 19 42 #define SLEV_name_req 20 43 #define SLEV_inq_timeout 21 44 #define SLEV_page_timeout 22 45 #define SLEV_pageresp_timeout 23 46 #define SLEV_newconnect_timeout 24 47 48 // 1-bit data: 0/1 for hardware signal: PA4/PB1; bid2 - bid31 49 #define SL01_TX_PA4 0 50 #define SL01_RXSYNC_PB1 1 51 #define SL01_ac_inq 2 52 #define SL01_ac_inq_scan 3 53 #define SL01_ac_page 4 54 #define SL01_ac_page_scan 5 55 #define SL01_ac_m_connect 6 56 #define SL01_ac_s_connect 7 57 58 #define SL01_task_system_tick 8 59 #define SL01_task_rx 9 60 #define SL01_tx_tgl_level 10 61 #define SL01_task_bt_ll_main 11 62 #define SL01_task_test 12 63 #define SL01_detach_timeout 13 64 // 8-bit data: cid0 - cid63 65 #define SL08_ac_state 0 66 #define SL08_state_pending_slot 1 67 #define SL08_rx_lmp_code 2 68 #define SL08_rx_poll_fcnt 3 69 #define SL08_rx_poll_offset 4 70 #define SL08_rx_poll_rxbit 5 71 #define SL08_lmp_esc4 6 72 #define SL08_acl_tx_type 7 73 74 #define SL08_hci_wptr 8 75 #define SL08_hci_rptr 9 76 #define SL08_valid_range 10 77 // 16-bit data: sid0 - sid63 78 #define SL16_CLKN 0 79 #define SL16_FCNT 1 80 #define SL16_MCLK 2 81 #define SL16_MCLKP 3 82 #define SL16_RXBIT 4 83 #define SL16_RxStat 5 84 #define SL16_LNKCNTL 6 85 #define SL16_acl_tx_size 7 86 #define SL16_rx_acl_cid 8 87 #define SL16_sniff_slot 9 88 #define SL16_sniff_win 10 89 #define SL16_sub_instant 11 90 #endif 91