1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 16 #ifndef __MCU_IP_H__ 17 #define __MCU_IP_H__ 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /***************************************************************************** 24 * System clock 25 ****************************************************************************/ 26 #define KHz 1000 27 #define MHz 1000000 28 29 #define CPUFREQ (60 * MHz) 30 31 /***************************************************************************** 32 * Device Specific Peripheral Registers structures 33 ****************************************************************************/ 34 35 #define __I volatile const /* 'read only' permissions */ 36 #define __O volatile /* 'write only' permissions */ 37 #define __IO volatile /* 'read / write' permissions */ 38 39 #define _IO_(addr) (addr) 40 41 #define PLIC_BASE _IO_(0xE4000000) 42 #define PLMT_BASE _IO_(0xE6000000) 43 #define PLIC_SW_BASE _IO_(0xE6400000) 44 #define PLDM_BASE _IO_(0xE6800000) 45 #define SMU_BASE _IO_(0xF0100000) 46 47 /***************************************************************************** 48 * PLMT 49 ****************************************************************************/ 50 typedef struct { 51 __IO unsigned long long MTIME; /* 0x00 Machine Time */ 52 __IO unsigned long long MTIMECMP; /* 0x08 Machine Time Compare */ 53 } PLMT_RegDef; 54 55 typedef struct { 56 __I unsigned int SYSTEMVER; /* 0x00 SYSTEM ID and Revision Register */ 57 unsigned int RESERVED0[3]; /* 0x04 ~ 0x0C Reserved */ 58 __IO unsigned int WRSR; /* 0x10 Wakeup and Reset Status Register */ 59 __IO unsigned int SMUCR; /* 0x14 SMU Command Register */ 60 unsigned int RESERVED1[1]; /* 0x18 Reserved */ 61 __IO unsigned int WRMASK; /* 0x1C Wake up Mask Register */ 62 __IO unsigned int CER; /* 0x20 Clock Enable Register */ 63 __IO unsigned int CRR; /* 0x24 Clock Ratio Register */ 64 unsigned int RESERVED2[6]; /* 0x28 ~ 0x3C Reserved Register */ 65 __IO unsigned int SCRATCH; /* 0x40 Scratch Register */ 66 unsigned int RESERVED3[3]; /* 0x44 ~ 0x4C Reserved */ 67 __IO unsigned int RESET_VECTOR; /* 0x50 CPU Reset Vector Register */ 68 } SMU_RegDef; 69 /***************************************************************************** 70 * Peripheral device declaration 71 ****************************************************************************/ 72 73 #define MCUIP_PLMT ((PLMT_RegDef *) PLMT_BASE) 74 #define MCUIP_SMU ((SMU_RegDef *) SMU_BASE) 75 #ifdef __cplusplus 76 } 77 #endif 78 79 #endif /* __MCU_IP_H__ */ 80