1 /* 2 * Copyright (C) 2015-2017 Alibaba Group Holding Limited. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef MPU_H 17 #define MPU_H 18 19 #ifdef STAR_MPU_ENABLE 20 typedef struct { 21 unsigned int type; /* !< Offset: 0x000 (R/) MPU Type Register */ 22 unsigned int ctrl; /* !< Offset: 0x004 (R/W) MPU Control Register */ 23 unsigned int rnr; /* !< Offset: 0x008 (R/W) MPU Region RNRber Register */ 24 unsigned int rbar; /* !< Offset: 0x00C (R/W) MPU Region Base Address Register */ 25 unsigned int rlar; /* !< Offset: 0x010 (R/W) MPU Region Limit Address and Size Register */ 26 unsigned int rbar_a; /* !< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 27 unsigned int rlar_a; /* !< Offset: 0x018 (R/W) MPU Region Base Address Register */ 28 unsigned int reserve1; /* !< Offset: 0x01C */ 29 unsigned int reserve2; /* !< Offset: 0x020 */ 30 unsigned int reserve3; /* !< Offset: 0x024 */ 31 unsigned int reserve4; /* !< Offset: 0x028 */ 32 unsigned int reserve5; /* !< Offset: 0x02C */ 33 unsigned int mair0; /* !< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 34 unsigned int mair1; /* !< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 35 } MPU_t; 36 37 /* System Handler Control and State register */ 38 #define SHCSR_M ((unsigned int*)0xE000ED24UL) 39 40 /* MPU registers */ 41 42 #define MPU_BASE (0xE000ED90UL) 43 #define MPU ((MPU_t*)(MPU_BASE)) 44 45 #define MPU_TYPE_IREGION_OFFSET (16U) 46 47 #define MPU_TYPE_IREGION_MASK (0xFFUL << MPU_TYPE_IREGION_OFFSET) 48 49 #define MPU_TYPE_DREGION_OFFSET (8U) 50 51 #define MPU_TYPE_DREGION_MASK (0xFFUL << MPU_TYPE_DREGION_OFFSET) 52 53 #define MPU_TYPE_SEPARATE_OFFSET (0U) 54 55 #define MPU_TYPE_SEPARATE_MASK (1UL) 56 57 #define MPU_CTRL_PRIVDEFENA_OFFSET (2U) 58 59 #define MPU_CTRL_PRIVDEFENA_MASK (1UL << MPU_CTRL_PRIVDEFENA_OFFSET) 60 61 #define MPU_CTRL_HFNMIENA_OFFSET (1U) 62 63 #define MPU_CTRL_HFNMIENA_MASK (1UL << MPU_CTRL_HFNMIENA_OFFSET) 64 65 #define MPU_CTRL_ENABLE_OFFSET (0U) 66 67 #define MPU_CTRL_ENABLE_MASK (1UL) 68 69 #define MPU_RNR_REGION_OFFSET (0U) 70 71 #define MPU_RNR_REGION_MASK (0xFFUL) 72 73 #define MPU_RBAR_ADDR_OFFSET (5U) 74 75 #define MPU_RBAR_ADDR_MASK (0x7FFFFFFUL << MPU_RBAR_ADDR_OFFSET) 76 77 #define MPU_RBAR_VALID_OFFSET (4U) 78 79 #define MPU_RBAR_VALID_MASK (1UL << MPU_RBAR_VALID_OFFSET) 80 81 #define MPU_RBAR_REGION_OFFSET (0U) 82 83 #define MPU_RBAR_REGION_MASK (0xFUL) 84 85 #define MPU_RASR_ATTRS_OFFSET (16U) 86 87 #define MPU_RASR_ATTRS_MASK (0xFFFFUL << MPU_RASR_ATTRS_OFFSET) 88 89 #define MPU_RASR_XN_OFFSET (28U) 90 91 #define MPU_RASR_XN_MASK (1UL << MPU_RASR_XN_OFFSET) 92 93 #define MPU_RASR_AP_OFFSET (24U) 94 95 #define MPU_RASR_AP_MASK (0x7UL << MPU_RASR_AP_OFFSET) 96 97 #define MPU_RASR_TEX_OFFSET (19U) 98 99 #define MPU_RASR_TEX_MASK (0x7UL << MPU_RASR_TEX_OFFSET) 100 101 #define MPU_RASR_S_OFFSET (18U) 102 103 #define MPU_RASR_S_MASK (1UL << MPU_RASR_S_OFFSET) 104 105 #define MPU_RASR_C_OFFSET (17U) 106 107 #define MPU_RASR_C_MASK (1UL << MPU_RASR_C_OFFSET) 108 109 #define MPU_RASR_B_OFFSET (16U) 110 111 #define MPU_RASR_B_MASK (1UL << MPU_RASR_B_OFFSET) 112 113 #define MPU_RASR_SRD_OFFSET (8U) 114 115 #define MPU_RASR_SRD_MASK (0xFFUL << MPU_RASR_SRD_OFFSET) 116 117 #define MPU_RASR_SIZE_OFFSET (1U) 118 119 #define MPU_RASR_SIZE_MASK (0x1FUL << MPU_RASR_SIZE_OFFSET) 120 121 #define MPU_RASR_ENABLE_OFFSET (0U) 122 123 #define MPU_RASR_ENABLE_MASK (1UL) 124 125 #define ATTR_INDEX_OFFSET 1 126 127 #define AP_OFFSET 1 128 #define ACCESS_PERMISSIONS_RW (0x01) 129 130 #define REGION_ENABLE (0x1) 131 #define REGION_DISABLE (0x0) 132 133 /* MPU regions size */ 134 135 #define MPU_REGION_SIZE_32B (0x04U) 136 #define MPU_REGION_SIZE_64B (0x05U) 137 #define MPU_REGION_SIZE_128B (0x06U) 138 #define MPU_REGION_SIZE_256B (0x07U) 139 #define MPU_REGION_SIZE_512B (0x08U) 140 #define MPU_REGION_SIZE_1KB (0x09U) 141 #define MPU_REGION_SIZE_2KB (0x0AU) 142 #define MPU_REGION_SIZE_4KB (0x0BU) 143 #define MPU_REGION_SIZE_8KB (0x0CU) 144 #define MPU_REGION_SIZE_16KB (0x0DU) 145 #define MPU_REGION_SIZE_32KB (0x0EU) 146 #define MPU_REGION_SIZE_64KB (0x0FU) 147 #define MPU_REGION_SIZE_128KB (0x10U) 148 #define MPU_REGION_SIZE_256KB (0x11U) 149 #define MPU_REGION_SIZE_512KB (0x12U) 150 #define MPU_REGION_SIZE_1MB (0x13U) 151 #define MPU_REGION_SIZE_2MB (0x14U) 152 #define MPU_REGION_SIZE_4MB (0x15U) 153 #define MPU_REGION_SIZE_8MB (0x16U) 154 #define MPU_REGION_SIZE_16MB (0x17U) 155 #define MPU_REGION_SIZE_32MB (0x18U) 156 #define MPU_REGION_SIZE_64MB (0x19U) 157 #define MPU_REGION_SIZE_128MB (0x1AU) 158 #define MPU_REGION_SIZE_256MB (0x1BU) 159 #define MPU_REGION_SIZE_512MB (0x1CU) 160 #define MPU_REGION_SIZE_1GB (0x1DU) 161 #define MPU_REGION_SIZE_2GB (0x1EU) 162 #define MPU_REGION_SIZE_4GB (0x1FU) 163 164 #define MPU_AP_NA_NA (0x00U) 165 #define MPU_AP_RW_NA (0x01U) 166 #define MPU_AP_RW_RO (0x02U) 167 #define MPU_AP_RW_RW (0x03U) 168 #define MPU_AP_RESV (0x04U) 169 #define MPU_AP_RO_NA (0x05U) 170 #define MPU_AP_RO_RO (0x06U) 171 172 typedef struct { 173 unsigned long base_addr; 174 unsigned char range_no; 175 unsigned long size; 176 unsigned char ext_type; 177 unsigned char access_permission; 178 unsigned char disable_exec; 179 unsigned char subregion_disable; 180 unsigned char shareable; 181 unsigned char cacheable; 182 unsigned char bufferable; 183 unsigned char enable; 184 } MPU_Region_Init_t; 185 186 /** 187 * set mpu region for memory unauthorized access check 188 * 189 * @param[in] addr_start monitor start addr 190 * @param[in] addr_size monitor size 191 * @param[in] mode prohibit access(0) or read only(>0) 192 */ 193 void debug_memory_access_err_check(unsigned long addr_start, unsigned long addr_size, 194 unsigned int mode, unsigned int cacheable, unsigned int rnr); 195 void mpu_init(void); 196 197 #else // STAR_MPU_ENABLE 198 typedef struct { 199 // MPU type register 200 unsigned int type; 201 // MPU control register 202 unsigned int ctrl; 203 // MPU range number register 204 unsigned int rnr; 205 // MPU region base address register 206 unsigned int rbar; 207 // MPU region attribute and size register 208 unsigned int rasr; 209 // MPU alias registers 210 unsigned int rbar_a1; 211 unsigned int rasr_a1; 212 unsigned int rbar_a2; 213 unsigned int rasr_a2; 214 unsigned int rbar_a3; 215 unsigned int rasr_a3; 216 } MPU_t; 217 218 /* System Handler Control and State register */ 219 #define SHCSR_M ((unsigned int*)0xE000ED24UL) 220 221 /* MPU registers */ 222 223 #define MPU_BASE (0xE000ED90UL) 224 #define MPU ((MPU_t*)(MPU_BASE)) 225 226 #define MPU_TYPE_IREGION_OFFSET (16U) 227 228 #define MPU_TYPE_IREGION_MASK (0xFFUL << MPU_TYPE_IREGION_OFFSET) 229 230 #define MPU_TYPE_DREGION_OFFSET (8U) 231 232 #define MPU_TYPE_DREGION_MASK (0xFFUL << MPU_TYPE_DREGION_OFFSET) 233 234 #define MPU_TYPE_SEPARATE_OFFSET (0U) 235 236 #define MPU_TYPE_SEPARATE_MASK (1UL) 237 238 #define MPU_CTRL_PRIVDEFENA_OFFSET (2U) 239 240 #define MPU_CTRL_PRIVDEFENA_MASK (1UL << MPU_CTRL_PRIVDEFENA_OFFSET) 241 242 #define MPU_CTRL_HFNMIENA_OFFSET (1U) 243 244 #define MPU_CTRL_HFNMIENA_MASK (1UL << MPU_CTRL_HFNMIENA_OFFSET) 245 246 #define MPU_CTRL_ENABLE_OFFSET (0U) 247 248 #define MPU_CTRL_ENABLE_MASK (1UL) 249 250 #define MPU_RNR_REGION_OFFSET (0U) 251 252 #define MPU_RNR_REGION_MASK (0xFFUL) 253 254 #define MPU_RBAR_ADDR_OFFSET (5U) 255 256 #define MPU_RBAR_ADDR_MASK (0x7FFFFFFUL << MPU_RBAR_ADDR_OFFSET) 257 258 #define MPU_RBAR_VALID_OFFSET (4U) 259 260 #define MPU_RBAR_VALID_MASK (1UL << MPU_RBAR_VALID_OFFSET) 261 262 #define MPU_RBAR_REGION_OFFSET (0U) 263 264 #define MPU_RBAR_REGION_MASK (0xFUL) 265 266 #define MPU_RASR_ATTRS_OFFSET (16U) 267 268 #define MPU_RASR_ATTRS_MASK (0xFFFFUL << MPU_RASR_ATTRS_OFFSET) 269 270 #define MPU_RASR_XN_OFFSET (28U) 271 272 #define MPU_RASR_XN_MASK (1UL << MPU_RASR_XN_OFFSET) 273 274 #define MPU_RASR_AP_OFFSET (24U) 275 276 #define MPU_RASR_AP_MASK (0x7UL << MPU_RASR_AP_OFFSET) 277 278 #define MPU_RASR_TEX_OFFSET (19U) 279 280 #define MPU_RASR_TEX_MASK (0x7UL << MPU_RASR_TEX_OFFSET) 281 282 #define MPU_RASR_S_OFFSET (18U) 283 284 #define MPU_RASR_S_MASK (1UL << MPU_RASR_S_OFFSET) 285 286 #define MPU_RASR_C_OFFSET (17U) 287 288 #define MPU_RASR_C_MASK (1UL << MPU_RASR_C_OFFSET) 289 290 #define MPU_RASR_B_OFFSET (16U) 291 292 #define MPU_RASR_B_MASK (1UL << MPU_RASR_B_OFFSET) 293 294 #define MPU_RASR_SRD_OFFSET (8U) 295 296 #define MPU_RASR_SRD_MASK (0xFFUL << MPU_RASR_SRD_OFFSET) 297 298 #define MPU_RASR_SIZE_OFFSET (1U) 299 300 #define MPU_RASR_SIZE_MASK (0x1FUL << MPU_RASR_SIZE_OFFSET) 301 302 #define MPU_RASR_ENABLE_OFFSET (0U) 303 304 #define MPU_RASR_ENABLE_MASK (1UL) 305 306 /* MPU regions size */ 307 308 #define MPU_REGION_SIZE_32B (0x04U) 309 #define MPU_REGION_SIZE_64B (0x05U) 310 #define MPU_REGION_SIZE_128B (0x06U) 311 #define MPU_REGION_SIZE_256B (0x07U) 312 #define MPU_REGION_SIZE_512B (0x08U) 313 #define MPU_REGION_SIZE_1KB (0x09U) 314 #define MPU_REGION_SIZE_2KB (0x0AU) 315 #define MPU_REGION_SIZE_4KB (0x0BU) 316 #define MPU_REGION_SIZE_8KB (0x0CU) 317 #define MPU_REGION_SIZE_16KB (0x0DU) 318 #define MPU_REGION_SIZE_32KB (0x0EU) 319 #define MPU_REGION_SIZE_64KB (0x0FU) 320 #define MPU_REGION_SIZE_128KB (0x10U) 321 #define MPU_REGION_SIZE_256KB (0x11U) 322 #define MPU_REGION_SIZE_512KB (0x12U) 323 #define MPU_REGION_SIZE_1MB (0x13U) 324 #define MPU_REGION_SIZE_2MB (0x14U) 325 #define MPU_REGION_SIZE_4MB (0x15U) 326 #define MPU_REGION_SIZE_8MB (0x16U) 327 #define MPU_REGION_SIZE_16MB (0x17U) 328 #define MPU_REGION_SIZE_32MB (0x18U) 329 #define MPU_REGION_SIZE_64MB (0x19U) 330 #define MPU_REGION_SIZE_128MB (0x1AU) 331 #define MPU_REGION_SIZE_256MB (0x1BU) 332 #define MPU_REGION_SIZE_512MB (0x1CU) 333 #define MPU_REGION_SIZE_1GB (0x1DU) 334 #define MPU_REGION_SIZE_2GB (0x1EU) 335 #define MPU_REGION_SIZE_4GB (0x1FU) 336 337 #define MPU_AP_NA_NA (0x00U) 338 #define MPU_AP_RW_NA (0x01U) 339 #define MPU_AP_RW_RO (0x02U) 340 #define MPU_AP_RW_RW (0x03U) 341 #define MPU_AP_RESV (0x04U) 342 #define MPU_AP_RO_NA (0x05U) 343 #define MPU_AP_RO_RO (0x06U) 344 345 typedef struct { 346 unsigned long base_addr; 347 unsigned char range_no; 348 unsigned char size; 349 unsigned char ext_type; 350 unsigned char access_permission; 351 unsigned char disable_exec; 352 unsigned char subregion_disable; 353 unsigned char shareable; 354 unsigned char cacheable; 355 unsigned char bufferable; 356 unsigned char enable; 357 } MPU_Region_Init_t; 358 359 #if (DEBUG_CONFIG_PANIC > 0) 360 /** 361 * set mpu region for memory unauthorized access check 362 * 363 * @param[in] addr_start monitor start addr 364 * @param[in] addr_size monitor size 365 * @param[in] mode prohibit access(0) or read only(>0) 366 */ 367 void debug_memory_access_err_check(unsigned long addr_start, unsigned long addr_size, unsigned int mode); 368 #endif 369 370 #endif // STAR_MPU_ENABLE 371 372 #endif // MPU_H 373 374