1 /*
2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 /**
16 * @file reg_bt_rf.h
17 * @brief Definitions of the BT_RF HW block registers and register access functions.
18 *
19 * @defgroup REG_BT_RF REG_BT_RF
20 * @ingroup REG
21 * @{
22 *
23 * @brief Definitions of the BT_RF HW block registers and register access functions.
24 */
25 #ifndef _REG_BT_RF_H_
26 #define _REG_BT_RF_H_
27
28 #include "compiler.h"
29 #include "arch.h"
30 #include "reg_access_wrapper.h"
31
32 /** @brief Number of registers in the REG_BT_RF peripheral.
33 */
34 #define REG_BT_RF_COUNT 28
35
36 /** @brief Decoding mask of the REG_BT_RF peripheral registers from the CPU point of view.
37 */
38 #define REG_BT_RF_DECODING_MASK 0x0000007F
39
40 /**
41 * @name BT_DPLL_REG2 register definitions
42 * <table>
43 * <caption id="BT_DPLL_REG2_BF">BT_DPLL_REG2 bitfields</caption>
44 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value
45 * <tr><td>20 <td>bt_dpll_fref_sel_rx <td>R <td>R/W <td>0
46 * </table>
47 *
48 * @{
49 */
50
51 /// Address of the BT_DPLL_REG2 register
52 #define BT_RF_BT_DPLL_REG2_ADDR 0x40622030
53 /// Offset of the BT_DPLL_REG2 register from the base address
54 #define BT_RF_BT_DPLL_REG2_OFFSET 0x00000030
55 /// Index of the BT_DPLL_REG2 register
56 #define BT_RF_BT_DPLL_REG2_INDEX 0x0000000C
57 /// Reset value of the BT_DPLL_REG2 register
58 #define BT_RF_BT_DPLL_REG2_RESET 0x00000000
59
60 /**
61 * @brief Returns the current value of the BT_DPLL_REG2 register.
62 * The BT_DPLL_REG2 register will be read and its value returned.
63 * @return The current value of the BT_DPLL_REG2 register.
64 */
bt_rf_bt_dpll_reg2_get(void)65 __INLINE uint32_t bt_rf_bt_dpll_reg2_get(void)
66 {
67 return PLATFORM_REG_READ(BT_RF_BT_DPLL_REG2_ADDR);
68 }
69
70 /**
71 * @brief Sets the BT_DPLL_REG2 register to a value.
72 * The BT_DPLL_REG2 register will be written.
73 * @param value - The value to write.
74 */
bt_rf_bt_dpll_reg2_set(uint32_t value)75 __INLINE void bt_rf_bt_dpll_reg2_set(uint32_t value)
76 {
77 PLATFORM_REG_WRITE(BT_RF_BT_DPLL_REG2_ADDR, value);
78 }
79
80 // field definitions
81 /// BT_DPLL_FREF_SEL_RX field bit
82 #define BT_RF_BT_DPLL_FREF_SEL_RX_BIT ((uint32_t)0x00100000)
83 /// BT_DPLL_FREF_SEL_RX field position
84 #define BT_RF_BT_DPLL_FREF_SEL_RX_POS 20
85
86 /// BT_DPLL_FREF_SEL_RX field reset value
87 #define BT_RF_BT_DPLL_FREF_SEL_RX_RST 0x0
88
89 /**
90 * @brief Returns the current value of the bt_dpll_fref_sel_rx field in the BT_DPLL_REG2 register.
91 *
92 * The BT_DPLL_REG2 register will be read and the bt_dpll_fref_sel_rx field's value will be returned.
93 *
94 * @return The current value of the bt_dpll_fref_sel_rx field in the BT_DPLL_REG2 register.
95 */
bt_rf_bt_dpll_fref_sel_rx_getf(void)96 __INLINE uint8_t bt_rf_bt_dpll_fref_sel_rx_getf(void)
97 {
98 uint32_t localVal = PLATFORM_REG_READ(BT_RF_BT_DPLL_REG2_ADDR);
99 return (localVal >> 20);
100 }
101
102 /**
103 * @brief Sets the bt_dpll_fref_sel_rx field of the BT_DPLL_REG2 register.
104 *
105 * The BT_DPLL_REG2 register will be read, modified to contain the new field value, and written.
106 *
107 * @param[in] btdpllfrefselrx - The value to set the field to.
108 */
bt_rf_bt_dpll_fref_sel_rx_setf(uint8_t btdpllfrefselrx)109 __INLINE void bt_rf_bt_dpll_fref_sel_rx_setf(uint8_t btdpllfrefselrx)
110 {
111 PLATFORM_REG_WRITE(BT_RF_BT_DPLL_REG2_ADDR, (uint32_t)btdpllfrefselrx << 20);
112 }
113
114 /// @}
115
116 /**
117 * @name MAN_CTRL register definitions
118 * <table>
119 * <caption id="MAN_CTRL_BF">MAN_CTRL bitfields</caption>
120 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value
121 * <tr><td>16 <td> rfon <td>R <td>R/W <td>0
122 * </table>
123 *
124 * @{
125 */
126
127 /// Address of the MAN_CTRL register
128 #define BT_RF_MAN_CTRL_ADDR 0x4062204C
129 /// Offset of the MAN_CTRL register from the base address
130 #define BT_RF_MAN_CTRL_OFFSET 0x0000004C
131 /// Index of the MAN_CTRL register
132 #define BT_RF_MAN_CTRL_INDEX 0x00000013
133 /// Reset value of the MAN_CTRL register
134 #define BT_RF_MAN_CTRL_RESET 0x00000000
135
136 /**
137 * @brief Returns the current value of the MAN_CTRL register.
138 * The MAN_CTRL register will be read and its value returned.
139 * @return The current value of the MAN_CTRL register.
140 */
bt_rf_man_ctrl_get(void)141 __INLINE uint32_t bt_rf_man_ctrl_get(void)
142 {
143 return PLATFORM_REG_READ(BT_RF_MAN_CTRL_ADDR);
144 }
145
146 /**
147 * @brief Sets the MAN_CTRL register to a value.
148 * The MAN_CTRL register will be written.
149 * @param value - The value to write.
150 */
bt_rf_man_ctrl_set(uint32_t value)151 __INLINE void bt_rf_man_ctrl_set(uint32_t value)
152 {
153 PLATFORM_REG_WRITE(BT_RF_MAN_CTRL_ADDR, value);
154 }
155
156 // field definitions
157 /// RFON field bit
158 #define BT_RF_RFON_BIT ((uint32_t)0x00010000)
159 /// RFON field position
160 #define BT_RF_RFON_POS 16
161
162 /// RFON field reset value
163 #define BT_RF_RFON_RST 0x0
164
165 /**
166 * @brief Returns the current value of the rfon field in the MAN_CTRL register.
167 *
168 * The MAN_CTRL register will be read and the rfon field's value will be returned.
169 *
170 * @return The current value of the rfon field in the MAN_CTRL register.
171 */
bt_rf_rfon_getf(void)172 __INLINE uint8_t bt_rf_rfon_getf(void)
173 {
174 uint32_t localVal = PLATFORM_REG_READ(BT_RF_MAN_CTRL_ADDR);
175 return (localVal >> 16);
176 }
177
178 /**
179 * @brief Sets the rfon field of the MAN_CTRL register.
180 *
181 * The MAN_CTRL register will be read, modified to contain the new field value, and written.
182 *
183 * @param[in] rfon - The value to set the field to.
184 */
bt_rf_rfon_setf(uint8_t rfon)185 __INLINE void bt_rf_rfon_setf(uint8_t rfon)
186 {
187 PLATFORM_REG_WRITE(BT_RF_MAN_CTRL_ADDR, (uint32_t)rfon << 16);
188 }
189
190 /// @}
191
192 /**
193 * @name RXGAIN_MEM_CTRL register definitions
194 * <table>
195 * <caption id="RXGAIN_MEM_CTRL_BF">RXGAIN_MEM_CTRL bitfields</caption>
196 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value
197 * <tr><td>11 <td>rxgain_mem_rw_done <td>R <td>R/W <td>0
198 * <tr><td>10 <td> clk_rxgain_sel <td>R <td>R/W <td>0
199 * <tr><td>09 <td> clk_rxgain_en <td>R <td>R/W <td>0
200 * <tr><td>08 <td> rxgain_mem_cfg <td>R <td>R/W <td>0
201 * <tr><td>07 <td>rxgain_mem_ren_pulse <td>R <td>R/W <td>0
202 * <tr><td>06 <td>rxgain_mem_wen_pulse <td>R <td>R/W <td>0
203 * <tr><td>05:00 <td>rxgain_mem_addr_cfg <td>R <td>R/W <td>0x0
204 * </table>
205 *
206 * @{
207 */
208
209 /// Address of the RXGAIN_MEM_CTRL register
210 #define BT_RF_RXGAIN_MEM_CTRL_ADDR 0x40622058
211 /// Offset of the RXGAIN_MEM_CTRL register from the base address
212 #define BT_RF_RXGAIN_MEM_CTRL_OFFSET 0x00000058
213 /// Index of the RXGAIN_MEM_CTRL register
214 #define BT_RF_RXGAIN_MEM_CTRL_INDEX 0x00000016
215 /// Reset value of the RXGAIN_MEM_CTRL register
216 #define BT_RF_RXGAIN_MEM_CTRL_RESET 0x00000000
217
218 /**
219 * @brief Returns the current value of the RXGAIN_MEM_CTRL register.
220 * The RXGAIN_MEM_CTRL register will be read and its value returned.
221 * @return The current value of the RXGAIN_MEM_CTRL register.
222 */
bt_rf_rxgain_mem_ctrl_get(void)223 __INLINE uint32_t bt_rf_rxgain_mem_ctrl_get(void)
224 {
225 return PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
226 }
227
228 /**
229 * @brief Sets the RXGAIN_MEM_CTRL register to a value.
230 * The RXGAIN_MEM_CTRL register will be written.
231 * @param value - The value to write.
232 */
bt_rf_rxgain_mem_ctrl_set(uint32_t value)233 __INLINE void bt_rf_rxgain_mem_ctrl_set(uint32_t value)
234 {
235 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, value);
236 }
237
238 // field definitions
239 /// RXGAIN_MEM_RW_DONE field bit
240 #define BT_RF_RXGAIN_MEM_RW_DONE_BIT ((uint32_t)0x00000800)
241 /// RXGAIN_MEM_RW_DONE field position
242 #define BT_RF_RXGAIN_MEM_RW_DONE_POS 11
243 /// CLK_RXGAIN_SEL field bit
244 #define BT_RF_CLK_RXGAIN_SEL_BIT ((uint32_t)0x00000400)
245 /// CLK_RXGAIN_SEL field position
246 #define BT_RF_CLK_RXGAIN_SEL_POS 10
247 /// CLK_RXGAIN_EN field bit
248 #define BT_RF_CLK_RXGAIN_EN_BIT ((uint32_t)0x00000200)
249 /// CLK_RXGAIN_EN field position
250 #define BT_RF_CLK_RXGAIN_EN_POS 9
251 /// RXGAIN_MEM_CFG field bit
252 #define BT_RF_RXGAIN_MEM_CFG_BIT ((uint32_t)0x00000100)
253 /// RXGAIN_MEM_CFG field position
254 #define BT_RF_RXGAIN_MEM_CFG_POS 8
255 /// RXGAIN_MEM_REN_PULSE field bit
256 #define BT_RF_RXGAIN_MEM_REN_PULSE_BIT ((uint32_t)0x00000080)
257 /// RXGAIN_MEM_REN_PULSE field position
258 #define BT_RF_RXGAIN_MEM_REN_PULSE_POS 7
259 /// RXGAIN_MEM_WEN_PULSE field bit
260 #define BT_RF_RXGAIN_MEM_WEN_PULSE_BIT ((uint32_t)0x00000040)
261 /// RXGAIN_MEM_WEN_PULSE field position
262 #define BT_RF_RXGAIN_MEM_WEN_PULSE_POS 6
263 /// RXGAIN_MEM_ADDR_CFG field mask
264 #define BT_RF_RXGAIN_MEM_ADDR_CFG_MASK ((uint32_t)0x0000003F)
265 /// RXGAIN_MEM_ADDR_CFG field LSB position
266 #define BT_RF_RXGAIN_MEM_ADDR_CFG_LSB 0
267 /// RXGAIN_MEM_ADDR_CFG field width
268 #define BT_RF_RXGAIN_MEM_ADDR_CFG_WIDTH ((uint32_t)0x00000006)
269
270 /// RXGAIN_MEM_RW_DONE field reset value
271 #define BT_RF_RXGAIN_MEM_RW_DONE_RST 0x0
272 /// CLK_RXGAIN_SEL field reset value
273 #define BT_RF_CLK_RXGAIN_SEL_RST 0x0
274 /// CLK_RXGAIN_EN field reset value
275 #define BT_RF_CLK_RXGAIN_EN_RST 0x0
276 /// RXGAIN_MEM_CFG field reset value
277 #define BT_RF_RXGAIN_MEM_CFG_RST 0x0
278 /// RXGAIN_MEM_REN_PULSE field reset value
279 #define BT_RF_RXGAIN_MEM_REN_PULSE_RST 0x0
280 /// RXGAIN_MEM_WEN_PULSE field reset value
281 #define BT_RF_RXGAIN_MEM_WEN_PULSE_RST 0x0
282 /// RXGAIN_MEM_ADDR_CFG field reset value
283 #define BT_RF_RXGAIN_MEM_ADDR_CFG_RST 0x0
284
285 /**
286 * @brief Constructs a value for the RXGAIN_MEM_CTRL register given values for its fields
287 * and writes the value to the register.
288 *
289 * @param[in] rxgainmemrwdone - The value to use for the rxgain_mem_rw_done field.
290 * @param[in] clkrxgainsel - The value to use for the clk_rxgain_sel field.
291 * @param[in] clkrxgainen - The value to use for the clk_rxgain_en field.
292 * @param[in] rxgainmemcfg - The value to use for the rxgain_mem_cfg field.
293 * @param[in] rxgainmemrenpulse - The value to use for the rxgain_mem_ren_pulse field.
294 * @param[in] rxgainmemwenpulse - The value to use for the rxgain_mem_wen_pulse field.
295 * @param[in] rxgainmemaddrcfg - The value to use for the rxgain_mem_addr_cfg field.
296 */
bt_rf_rxgain_mem_ctrl_pack(uint8_t rxgainmemrwdone,uint8_t clkrxgainsel,uint8_t clkrxgainen,uint8_t rxgainmemcfg,uint8_t rxgainmemrenpulse,uint8_t rxgainmemwenpulse,uint8_t rxgainmemaddrcfg)297 __INLINE void bt_rf_rxgain_mem_ctrl_pack(uint8_t rxgainmemrwdone, uint8_t clkrxgainsel, uint8_t clkrxgainen, uint8_t rxgainmemcfg, uint8_t rxgainmemrenpulse, uint8_t rxgainmemwenpulse, uint8_t rxgainmemaddrcfg)
298 {
299 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, ((uint32_t)rxgainmemrwdone << 11) | ((uint32_t)clkrxgainsel << 10) | ((uint32_t)clkrxgainen << 9) | ((uint32_t)rxgainmemcfg << 8) | ((uint32_t)rxgainmemrenpulse << 7) | ((uint32_t)rxgainmemwenpulse << 6) | ((uint32_t)rxgainmemaddrcfg << 0));
300 }
301
302 /**
303 * @brief Unpacks RXGAIN_MEM_CTRL's fields from current value of the RXGAIN_MEM_CTRL register.
304 *
305 * Reads the RXGAIN_MEM_CTRL register and populates all the _field variables with the corresponding
306 * values from the register.
307 *
308 * @param[out] rxgainmemrwdone - Will be populated with the current value of this field from the register.
309 * @param[out] clkrxgainsel - Will be populated with the current value of this field from the register.
310 * @param[out] clkrxgainen - Will be populated with the current value of this field from the register.
311 * @param[out] rxgainmemcfg - Will be populated with the current value of this field from the register.
312 * @param[out] rxgainmemrenpulse - Will be populated with the current value of this field from the register.
313 * @param[out] rxgainmemwenpulse - Will be populated with the current value of this field from the register.
314 * @param[out] rxgainmemaddrcfg - Will be populated with the current value of this field from the register.
315 */
bt_rf_rxgain_mem_ctrl_unpack(uint8_t * rxgainmemrwdone,uint8_t * clkrxgainsel,uint8_t * clkrxgainen,uint8_t * rxgainmemcfg,uint8_t * rxgainmemrenpulse,uint8_t * rxgainmemwenpulse,uint8_t * rxgainmemaddrcfg)316 __INLINE void bt_rf_rxgain_mem_ctrl_unpack(uint8_t* rxgainmemrwdone, uint8_t* clkrxgainsel, uint8_t* clkrxgainen, uint8_t* rxgainmemcfg, uint8_t* rxgainmemrenpulse, uint8_t* rxgainmemwenpulse, uint8_t* rxgainmemaddrcfg)
317 {
318 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
319
320 *rxgainmemrwdone = (localVal & ((uint32_t)0x00000800)) >> 11;
321 *clkrxgainsel = (localVal & ((uint32_t)0x00000400)) >> 10;
322 *clkrxgainen = (localVal & ((uint32_t)0x00000200)) >> 9;
323 *rxgainmemcfg = (localVal & ((uint32_t)0x00000100)) >> 8;
324 *rxgainmemrenpulse = (localVal & ((uint32_t)0x00000080)) >> 7;
325 *rxgainmemwenpulse = (localVal & ((uint32_t)0x00000040)) >> 6;
326 *rxgainmemaddrcfg = (localVal & ((uint32_t)0x0000003F)) >> 0;
327 }
328
329 /**
330 * @brief Returns the current value of the rxgain_mem_rw_done field in the RXGAIN_MEM_CTRL register.
331 *
332 * The RXGAIN_MEM_CTRL register will be read and the rxgain_mem_rw_done field's value will be returned.
333 *
334 * @return The current value of the rxgain_mem_rw_done field in the RXGAIN_MEM_CTRL register.
335 */
bt_rf_rxgain_mem_rw_done_getf(void)336 __INLINE uint8_t bt_rf_rxgain_mem_rw_done_getf(void)
337 {
338 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
339 return ((localVal & ((uint32_t)0x00000800)) >> 11);
340 }
341
342 /**
343 * @brief Sets the rxgain_mem_rw_done field of the RXGAIN_MEM_CTRL register.
344 *
345 * The RXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
346 *
347 * @param[in] rxgainmemrwdone - The value to set the field to.
348 */
bt_rf_rxgain_mem_rw_done_setf(uint8_t rxgainmemrwdone)349 __INLINE void bt_rf_rxgain_mem_rw_done_setf(uint8_t rxgainmemrwdone)
350 {
351 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000800)) | ((uint32_t)rxgainmemrwdone << 11));
352 }
353
354 /**
355 * @brief Returns the current value of the clk_rxgain_sel field in the RXGAIN_MEM_CTRL register.
356 *
357 * The RXGAIN_MEM_CTRL register will be read and the clk_rxgain_sel field's value will be returned.
358 *
359 * @return The current value of the clk_rxgain_sel field in the RXGAIN_MEM_CTRL register.
360 */
bt_rf_clk_rxgain_sel_getf(void)361 __INLINE uint8_t bt_rf_clk_rxgain_sel_getf(void)
362 {
363 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
364 return ((localVal & ((uint32_t)0x00000400)) >> 10);
365 }
366
367 /**
368 * @brief Sets the clk_rxgain_sel field of the RXGAIN_MEM_CTRL register.
369 *
370 * The RXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
371 *
372 * @param[in] clkrxgainsel - The value to set the field to.
373 */
bt_rf_clk_rxgain_sel_setf(uint8_t clkrxgainsel)374 __INLINE void bt_rf_clk_rxgain_sel_setf(uint8_t clkrxgainsel)
375 {
376 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000400)) | ((uint32_t)clkrxgainsel << 10));
377 }
378
379 /**
380 * @brief Returns the current value of the clk_rxgain_en field in the RXGAIN_MEM_CTRL register.
381 *
382 * The RXGAIN_MEM_CTRL register will be read and the clk_rxgain_en field's value will be returned.
383 *
384 * @return The current value of the clk_rxgain_en field in the RXGAIN_MEM_CTRL register.
385 */
bt_rf_clk_rxgain_en_getf(void)386 __INLINE uint8_t bt_rf_clk_rxgain_en_getf(void)
387 {
388 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
389 return ((localVal & ((uint32_t)0x00000200)) >> 9);
390 }
391
392 /**
393 * @brief Sets the clk_rxgain_en field of the RXGAIN_MEM_CTRL register.
394 *
395 * The RXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
396 *
397 * @param[in] clkrxgainen - The value to set the field to.
398 */
bt_rf_clk_rxgain_en_setf(uint8_t clkrxgainen)399 __INLINE void bt_rf_clk_rxgain_en_setf(uint8_t clkrxgainen)
400 {
401 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000200)) | ((uint32_t)clkrxgainen << 9));
402 }
403
404 /**
405 * @brief Returns the current value of the rxgain_mem_cfg field in the RXGAIN_MEM_CTRL register.
406 *
407 * The RXGAIN_MEM_CTRL register will be read and the rxgain_mem_cfg field's value will be returned.
408 *
409 * @return The current value of the rxgain_mem_cfg field in the RXGAIN_MEM_CTRL register.
410 */
bt_rf_rxgain_mem_cfg_getf(void)411 __INLINE uint8_t bt_rf_rxgain_mem_cfg_getf(void)
412 {
413 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
414 return ((localVal & ((uint32_t)0x00000100)) >> 8);
415 }
416
417 /**
418 * @brief Sets the rxgain_mem_cfg field of the RXGAIN_MEM_CTRL register.
419 *
420 * The RXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
421 *
422 * @param[in] rxgainmemcfg - The value to set the field to.
423 */
bt_rf_rxgain_mem_cfg_setf(uint8_t rxgainmemcfg)424 __INLINE void bt_rf_rxgain_mem_cfg_setf(uint8_t rxgainmemcfg)
425 {
426 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)rxgainmemcfg << 8));
427 }
428
429 /**
430 * @brief Returns the current value of the rxgain_mem_ren_pulse field in the RXGAIN_MEM_CTRL register.
431 *
432 * The RXGAIN_MEM_CTRL register will be read and the rxgain_mem_ren_pulse field's value will be returned.
433 *
434 * @return The current value of the rxgain_mem_ren_pulse field in the RXGAIN_MEM_CTRL register.
435 */
bt_rf_rxgain_mem_ren_pulse_getf(void)436 __INLINE uint8_t bt_rf_rxgain_mem_ren_pulse_getf(void)
437 {
438 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
439 return ((localVal & ((uint32_t)0x00000080)) >> 7);
440 }
441
442 /**
443 * @brief Sets the rxgain_mem_ren_pulse field of the RXGAIN_MEM_CTRL register.
444 *
445 * The RXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
446 *
447 * @param[in] rxgainmemrenpulse - The value to set the field to.
448 */
bt_rf_rxgain_mem_ren_pulse_setf(uint8_t rxgainmemrenpulse)449 __INLINE void bt_rf_rxgain_mem_ren_pulse_setf(uint8_t rxgainmemrenpulse)
450 {
451 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000080)) | ((uint32_t)rxgainmemrenpulse << 7));
452 }
453
454 /**
455 * @brief Returns the current value of the rxgain_mem_wen_pulse field in the RXGAIN_MEM_CTRL register.
456 *
457 * The RXGAIN_MEM_CTRL register will be read and the rxgain_mem_wen_pulse field's value will be returned.
458 *
459 * @return The current value of the rxgain_mem_wen_pulse field in the RXGAIN_MEM_CTRL register.
460 */
bt_rf_rxgain_mem_wen_pulse_getf(void)461 __INLINE uint8_t bt_rf_rxgain_mem_wen_pulse_getf(void)
462 {
463 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
464 return ((localVal & ((uint32_t)0x00000040)) >> 6);
465 }
466
467 /**
468 * @brief Sets the rxgain_mem_wen_pulse field of the RXGAIN_MEM_CTRL register.
469 *
470 * The RXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
471 *
472 * @param[in] rxgainmemwenpulse - The value to set the field to.
473 */
bt_rf_rxgain_mem_wen_pulse_setf(uint8_t rxgainmemwenpulse)474 __INLINE void bt_rf_rxgain_mem_wen_pulse_setf(uint8_t rxgainmemwenpulse)
475 {
476 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)rxgainmemwenpulse << 6));
477 }
478
479 /**
480 * @brief Returns the current value of the rxgain_mem_addr_cfg field in the RXGAIN_MEM_CTRL register.
481 *
482 * The RXGAIN_MEM_CTRL register will be read and the rxgain_mem_addr_cfg field's value will be returned.
483 *
484 * @return The current value of the rxgain_mem_addr_cfg field in the RXGAIN_MEM_CTRL register.
485 */
bt_rf_rxgain_mem_addr_cfg_getf(void)486 __INLINE uint8_t bt_rf_rxgain_mem_addr_cfg_getf(void)
487 {
488 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR);
489 return ((localVal & ((uint32_t)0x0000003F)) >> 0);
490 }
491
492 /**
493 * @brief Sets the rxgain_mem_addr_cfg field of the RXGAIN_MEM_CTRL register.
494 *
495 * The RXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
496 *
497 * @param[in] rxgainmemaddrcfg - The value to set the field to.
498 */
bt_rf_rxgain_mem_addr_cfg_setf(uint8_t rxgainmemaddrcfg)499 __INLINE void bt_rf_rxgain_mem_addr_cfg_setf(uint8_t rxgainmemaddrcfg)
500 {
501 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x0000003F)) | ((uint32_t)rxgainmemaddrcfg << 0));
502 }
503
504 /// @}
505
506 /**
507 * @name RXGAIN_MEM_WD register definitions
508 * <table>
509 * <caption id="RXGAIN_MEM_WD_BF">RXGAIN_MEM_WD bitfields</caption>
510 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value
511 * <tr><td>31:00 <td> rxgain_mem_wdata <td>R <td>R/W <td>0x0
512 * </table>
513 *
514 * @{
515 */
516
517 /// Address of the RXGAIN_MEM_WD register
518 #define BT_RF_RXGAIN_MEM_WD_ADDR 0x4062205C
519 /// Offset of the RXGAIN_MEM_WD register from the base address
520 #define BT_RF_RXGAIN_MEM_WD_OFFSET 0x0000005C
521 /// Index of the RXGAIN_MEM_WD register
522 #define BT_RF_RXGAIN_MEM_WD_INDEX 0x00000017
523 /// Reset value of the RXGAIN_MEM_WD register
524 #define BT_RF_RXGAIN_MEM_WD_RESET 0x00000000
525
526 /**
527 * @brief Returns the current value of the RXGAIN_MEM_WD register.
528 * The RXGAIN_MEM_WD register will be read and its value returned.
529 * @return The current value of the RXGAIN_MEM_WD register.
530 */
bt_rf_rxgain_mem_wd_get(void)531 __INLINE uint32_t bt_rf_rxgain_mem_wd_get(void)
532 {
533 return PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_WD_ADDR);
534 }
535
536 /**
537 * @brief Sets the RXGAIN_MEM_WD register to a value.
538 * The RXGAIN_MEM_WD register will be written.
539 * @param value - The value to write.
540 */
bt_rf_rxgain_mem_wd_set(uint32_t value)541 __INLINE void bt_rf_rxgain_mem_wd_set(uint32_t value)
542 {
543 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_WD_ADDR, value);
544 }
545
546 // field definitions
547 /// RXGAIN_MEM_WDATA field mask
548 #define BT_RF_RXGAIN_MEM_WDATA_MASK ((uint32_t)0xFFFFFFFF)
549 /// RXGAIN_MEM_WDATA field LSB position
550 #define BT_RF_RXGAIN_MEM_WDATA_LSB 0
551 /// RXGAIN_MEM_WDATA field width
552 #define BT_RF_RXGAIN_MEM_WDATA_WIDTH ((uint32_t)0x00000020)
553
554 /// RXGAIN_MEM_WDATA field reset value
555 #define BT_RF_RXGAIN_MEM_WDATA_RST 0x0
556
557 /**
558 * @brief Returns the current value of the rxgain_mem_wdata field in the RXGAIN_MEM_WD register.
559 *
560 * The RXGAIN_MEM_WD register will be read and the rxgain_mem_wdata field's value will be returned.
561 *
562 * @return The current value of the rxgain_mem_wdata field in the RXGAIN_MEM_WD register.
563 */
bt_rf_rxgain_mem_wdata_getf(void)564 __INLINE uint32_t bt_rf_rxgain_mem_wdata_getf(void)
565 {
566 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_WD_ADDR);
567 return (localVal >> 0);
568 }
569
570 /**
571 * @brief Sets the rxgain_mem_wdata field of the RXGAIN_MEM_WD register.
572 *
573 * The RXGAIN_MEM_WD register will be read, modified to contain the new field value, and written.
574 *
575 * @param[in] rxgainmemwdata - The value to set the field to.
576 */
bt_rf_rxgain_mem_wdata_setf(uint32_t rxgainmemwdata)577 __INLINE void bt_rf_rxgain_mem_wdata_setf(uint32_t rxgainmemwdata)
578 {
579 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_WD_ADDR, (uint32_t)rxgainmemwdata << 0);
580 }
581
582 /// @}
583
584 /**
585 * @name RXGAIN_MEM_RD register definitions
586 * <table>
587 * <caption id="RXGAIN_MEM_RD_BF">RXGAIN_MEM_RD bitfields</caption>
588 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value
589 * <tr><td>31:00 <td> rxgain_mem_rdata <td>R <td>R/W <td>0x0
590 * </table>
591 *
592 * @{
593 */
594
595 /// Address of the RXGAIN_MEM_RD register
596 #define BT_RF_RXGAIN_MEM_RD_ADDR 0x40622060
597 /// Offset of the RXGAIN_MEM_RD register from the base address
598 #define BT_RF_RXGAIN_MEM_RD_OFFSET 0x00000060
599 /// Index of the RXGAIN_MEM_RD register
600 #define BT_RF_RXGAIN_MEM_RD_INDEX 0x00000018
601 /// Reset value of the RXGAIN_MEM_RD register
602 #define BT_RF_RXGAIN_MEM_RD_RESET 0x00000000
603
604 /**
605 * @brief Returns the current value of the RXGAIN_MEM_RD register.
606 * The RXGAIN_MEM_RD register will be read and its value returned.
607 * @return The current value of the RXGAIN_MEM_RD register.
608 */
bt_rf_rxgain_mem_rd_get(void)609 __INLINE uint32_t bt_rf_rxgain_mem_rd_get(void)
610 {
611 return PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_RD_ADDR);
612 }
613
614 /**
615 * @brief Sets the RXGAIN_MEM_RD register to a value.
616 * The RXGAIN_MEM_RD register will be written.
617 * @param value - The value to write.
618 */
bt_rf_rxgain_mem_rd_set(uint32_t value)619 __INLINE void bt_rf_rxgain_mem_rd_set(uint32_t value)
620 {
621 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_RD_ADDR, value);
622 }
623
624 // field definitions
625 /// RXGAIN_MEM_RDATA field mask
626 #define BT_RF_RXGAIN_MEM_RDATA_MASK ((uint32_t)0xFFFFFFFF)
627 /// RXGAIN_MEM_RDATA field LSB position
628 #define BT_RF_RXGAIN_MEM_RDATA_LSB 0
629 /// RXGAIN_MEM_RDATA field width
630 #define BT_RF_RXGAIN_MEM_RDATA_WIDTH ((uint32_t)0x00000020)
631
632 /// RXGAIN_MEM_RDATA field reset value
633 #define BT_RF_RXGAIN_MEM_RDATA_RST 0x0
634
635 /**
636 * @brief Returns the current value of the rxgain_mem_rdata field in the RXGAIN_MEM_RD register.
637 *
638 * The RXGAIN_MEM_RD register will be read and the rxgain_mem_rdata field's value will be returned.
639 *
640 * @return The current value of the rxgain_mem_rdata field in the RXGAIN_MEM_RD register.
641 */
bt_rf_rxgain_mem_rdata_getf(void)642 __INLINE uint32_t bt_rf_rxgain_mem_rdata_getf(void)
643 {
644 uint32_t localVal = PLATFORM_REG_READ(BT_RF_RXGAIN_MEM_RD_ADDR);
645 return (localVal >> 0);
646 }
647
648 /**
649 * @brief Sets the rxgain_mem_rdata field of the RXGAIN_MEM_RD register.
650 *
651 * The RXGAIN_MEM_RD register will be read, modified to contain the new field value, and written.
652 *
653 * @param[in] rxgainmemrdata - The value to set the field to.
654 */
bt_rf_rxgain_mem_rdata_setf(uint32_t rxgainmemrdata)655 __INLINE void bt_rf_rxgain_mem_rdata_setf(uint32_t rxgainmemrdata)
656 {
657 PLATFORM_REG_WRITE(BT_RF_RXGAIN_MEM_RD_ADDR, (uint32_t)rxgainmemrdata << 0);
658 }
659
660 /// @}
661
662 /**
663 * @name TXGAIN_MEM_CTRL register definitions
664 * <table>
665 * <caption id="TXGAIN_MEM_CTRL_BF">TXGAIN_MEM_CTRL bitfields</caption>
666 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value
667 * <tr><td>10 <td>txgain_mem_rw_done <td>R <td>R/W <td>0
668 * <tr><td>09 <td> clk_txgain_sel <td>R <td>R/W <td>0
669 * <tr><td>08 <td> clk_txgain_en <td>R <td>R/W <td>0
670 * <tr><td>07 <td> txgain_mem_cfg <td>R <td>R/W <td>0
671 * <tr><td>06 <td>txgain_mem_ren_pulse <td>R <td>R/W <td>0
672 * <tr><td>05 <td>txgain_mem_wen_pulse <td>R <td>R/W <td>0
673 * <tr><td>04:00 <td>txgain_mem_addr_cfg <td>R <td>R/W <td>0x0
674 * </table>
675 *
676 * @{
677 */
678
679 /// Address of the TXGAIN_MEM_CTRL register
680 #define BT_RF_TXGAIN_MEM_CTRL_ADDR 0x40622064
681 /// Offset of the TXGAIN_MEM_CTRL register from the base address
682 #define BT_RF_TXGAIN_MEM_CTRL_OFFSET 0x00000064
683 /// Index of the TXGAIN_MEM_CTRL register
684 #define BT_RF_TXGAIN_MEM_CTRL_INDEX 0x00000019
685 /// Reset value of the TXGAIN_MEM_CTRL register
686 #define BT_RF_TXGAIN_MEM_CTRL_RESET 0x00000000
687
688 /**
689 * @brief Returns the current value of the TXGAIN_MEM_CTRL register.
690 * The TXGAIN_MEM_CTRL register will be read and its value returned.
691 * @return The current value of the TXGAIN_MEM_CTRL register.
692 */
bt_rf_txgain_mem_ctrl_get(void)693 __INLINE uint32_t bt_rf_txgain_mem_ctrl_get(void)
694 {
695 return PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
696 }
697
698 /**
699 * @brief Sets the TXGAIN_MEM_CTRL register to a value.
700 * The TXGAIN_MEM_CTRL register will be written.
701 * @param value - The value to write.
702 */
bt_rf_txgain_mem_ctrl_set(uint32_t value)703 __INLINE void bt_rf_txgain_mem_ctrl_set(uint32_t value)
704 {
705 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, value);
706 }
707
708 // field definitions
709 /// TXGAIN_MEM_RW_DONE field bit
710 #define BT_RF_TXGAIN_MEM_RW_DONE_BIT ((uint32_t)0x00000400)
711 /// TXGAIN_MEM_RW_DONE field position
712 #define BT_RF_TXGAIN_MEM_RW_DONE_POS 10
713 /// CLK_TXGAIN_SEL field bit
714 #define BT_RF_CLK_TXGAIN_SEL_BIT ((uint32_t)0x00000200)
715 /// CLK_TXGAIN_SEL field position
716 #define BT_RF_CLK_TXGAIN_SEL_POS 9
717 /// CLK_TXGAIN_EN field bit
718 #define BT_RF_CLK_TXGAIN_EN_BIT ((uint32_t)0x00000100)
719 /// CLK_TXGAIN_EN field position
720 #define BT_RF_CLK_TXGAIN_EN_POS 8
721 /// TXGAIN_MEM_CFG field bit
722 #define BT_RF_TXGAIN_MEM_CFG_BIT ((uint32_t)0x00000080)
723 /// TXGAIN_MEM_CFG field position
724 #define BT_RF_TXGAIN_MEM_CFG_POS 7
725 /// TXGAIN_MEM_REN_PULSE field bit
726 #define BT_RF_TXGAIN_MEM_REN_PULSE_BIT ((uint32_t)0x00000040)
727 /// TXGAIN_MEM_REN_PULSE field position
728 #define BT_RF_TXGAIN_MEM_REN_PULSE_POS 6
729 /// TXGAIN_MEM_WEN_PULSE field bit
730 #define BT_RF_TXGAIN_MEM_WEN_PULSE_BIT ((uint32_t)0x00000020)
731 /// TXGAIN_MEM_WEN_PULSE field position
732 #define BT_RF_TXGAIN_MEM_WEN_PULSE_POS 5
733 /// TXGAIN_MEM_ADDR_CFG field mask
734 #define BT_RF_TXGAIN_MEM_ADDR_CFG_MASK ((uint32_t)0x0000001F)
735 /// TXGAIN_MEM_ADDR_CFG field LSB position
736 #define BT_RF_TXGAIN_MEM_ADDR_CFG_LSB 0
737 /// TXGAIN_MEM_ADDR_CFG field width
738 #define BT_RF_TXGAIN_MEM_ADDR_CFG_WIDTH ((uint32_t)0x00000005)
739
740 /// TXGAIN_MEM_RW_DONE field reset value
741 #define BT_RF_TXGAIN_MEM_RW_DONE_RST 0x0
742 /// CLK_TXGAIN_SEL field reset value
743 #define BT_RF_CLK_TXGAIN_SEL_RST 0x0
744 /// CLK_TXGAIN_EN field reset value
745 #define BT_RF_CLK_TXGAIN_EN_RST 0x0
746 /// TXGAIN_MEM_CFG field reset value
747 #define BT_RF_TXGAIN_MEM_CFG_RST 0x0
748 /// TXGAIN_MEM_REN_PULSE field reset value
749 #define BT_RF_TXGAIN_MEM_REN_PULSE_RST 0x0
750 /// TXGAIN_MEM_WEN_PULSE field reset value
751 #define BT_RF_TXGAIN_MEM_WEN_PULSE_RST 0x0
752 /// TXGAIN_MEM_ADDR_CFG field reset value
753 #define BT_RF_TXGAIN_MEM_ADDR_CFG_RST 0x0
754
755 /**
756 * @brief Constructs a value for the TXGAIN_MEM_CTRL register given values for its fields
757 * and writes the value to the register.
758 *
759 * @param[in] txgainmemrwdone - The value to use for the txgain_mem_rw_done field.
760 * @param[in] clktxgainsel - The value to use for the clk_txgain_sel field.
761 * @param[in] clktxgainen - The value to use for the clk_txgain_en field.
762 * @param[in] txgainmemcfg - The value to use for the txgain_mem_cfg field.
763 * @param[in] txgainmemrenpulse - The value to use for the txgain_mem_ren_pulse field.
764 * @param[in] txgainmemwenpulse - The value to use for the txgain_mem_wen_pulse field.
765 * @param[in] txgainmemaddrcfg - The value to use for the txgain_mem_addr_cfg field.
766 */
bt_rf_txgain_mem_ctrl_pack(uint8_t txgainmemrwdone,uint8_t clktxgainsel,uint8_t clktxgainen,uint8_t txgainmemcfg,uint8_t txgainmemrenpulse,uint8_t txgainmemwenpulse,uint8_t txgainmemaddrcfg)767 __INLINE void bt_rf_txgain_mem_ctrl_pack(uint8_t txgainmemrwdone, uint8_t clktxgainsel, uint8_t clktxgainen, uint8_t txgainmemcfg, uint8_t txgainmemrenpulse, uint8_t txgainmemwenpulse, uint8_t txgainmemaddrcfg)
768 {
769 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, ((uint32_t)txgainmemrwdone << 10) | ((uint32_t)clktxgainsel << 9) | ((uint32_t)clktxgainen << 8) | ((uint32_t)txgainmemcfg << 7) | ((uint32_t)txgainmemrenpulse << 6) | ((uint32_t)txgainmemwenpulse << 5) | ((uint32_t)txgainmemaddrcfg << 0));
770 }
771
772 /**
773 * @brief Unpacks TXGAIN_MEM_CTRL's fields from current value of the TXGAIN_MEM_CTRL register.
774 *
775 * Reads the TXGAIN_MEM_CTRL register and populates all the _field variables with the corresponding
776 * values from the register.
777 *
778 * @param[out] txgainmemrwdone - Will be populated with the current value of this field from the register.
779 * @param[out] clktxgainsel - Will be populated with the current value of this field from the register.
780 * @param[out] clktxgainen - Will be populated with the current value of this field from the register.
781 * @param[out] txgainmemcfg - Will be populated with the current value of this field from the register.
782 * @param[out] txgainmemrenpulse - Will be populated with the current value of this field from the register.
783 * @param[out] txgainmemwenpulse - Will be populated with the current value of this field from the register.
784 * @param[out] txgainmemaddrcfg - Will be populated with the current value of this field from the register.
785 */
bt_rf_txgain_mem_ctrl_unpack(uint8_t * txgainmemrwdone,uint8_t * clktxgainsel,uint8_t * clktxgainen,uint8_t * txgainmemcfg,uint8_t * txgainmemrenpulse,uint8_t * txgainmemwenpulse,uint8_t * txgainmemaddrcfg)786 __INLINE void bt_rf_txgain_mem_ctrl_unpack(uint8_t* txgainmemrwdone, uint8_t* clktxgainsel, uint8_t* clktxgainen, uint8_t* txgainmemcfg, uint8_t* txgainmemrenpulse, uint8_t* txgainmemwenpulse, uint8_t* txgainmemaddrcfg)
787 {
788 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
789
790 *txgainmemrwdone = (localVal & ((uint32_t)0x00000400)) >> 10;
791 *clktxgainsel = (localVal & ((uint32_t)0x00000200)) >> 9;
792 *clktxgainen = (localVal & ((uint32_t)0x00000100)) >> 8;
793 *txgainmemcfg = (localVal & ((uint32_t)0x00000080)) >> 7;
794 *txgainmemrenpulse = (localVal & ((uint32_t)0x00000040)) >> 6;
795 *txgainmemwenpulse = (localVal & ((uint32_t)0x00000020)) >> 5;
796 *txgainmemaddrcfg = (localVal & ((uint32_t)0x0000001F)) >> 0;
797 }
798
799 /**
800 * @brief Returns the current value of the txgain_mem_rw_done field in the TXGAIN_MEM_CTRL register.
801 *
802 * The TXGAIN_MEM_CTRL register will be read and the txgain_mem_rw_done field's value will be returned.
803 *
804 * @return The current value of the txgain_mem_rw_done field in the TXGAIN_MEM_CTRL register.
805 */
bt_rf_txgain_mem_rw_done_getf(void)806 __INLINE uint8_t bt_rf_txgain_mem_rw_done_getf(void)
807 {
808 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
809 return ((localVal & ((uint32_t)0x00000400)) >> 10);
810 }
811
812 /**
813 * @brief Sets the txgain_mem_rw_done field of the TXGAIN_MEM_CTRL register.
814 *
815 * The TXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
816 *
817 * @param[in] txgainmemrwdone - The value to set the field to.
818 */
bt_rf_txgain_mem_rw_done_setf(uint8_t txgainmemrwdone)819 __INLINE void bt_rf_txgain_mem_rw_done_setf(uint8_t txgainmemrwdone)
820 {
821 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000400)) | ((uint32_t)txgainmemrwdone << 10));
822 }
823
824 /**
825 * @brief Returns the current value of the clk_txgain_sel field in the TXGAIN_MEM_CTRL register.
826 *
827 * The TXGAIN_MEM_CTRL register will be read and the clk_txgain_sel field's value will be returned.
828 *
829 * @return The current value of the clk_txgain_sel field in the TXGAIN_MEM_CTRL register.
830 */
bt_rf_clk_txgain_sel_getf(void)831 __INLINE uint8_t bt_rf_clk_txgain_sel_getf(void)
832 {
833 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
834 return ((localVal & ((uint32_t)0x00000200)) >> 9);
835 }
836
837 /**
838 * @brief Sets the clk_txgain_sel field of the TXGAIN_MEM_CTRL register.
839 *
840 * The TXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
841 *
842 * @param[in] clktxgainsel - The value to set the field to.
843 */
bt_rf_clk_txgain_sel_setf(uint8_t clktxgainsel)844 __INLINE void bt_rf_clk_txgain_sel_setf(uint8_t clktxgainsel)
845 {
846 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000200)) | ((uint32_t)clktxgainsel << 9));
847 }
848
849 /**
850 * @brief Returns the current value of the clk_txgain_en field in the TXGAIN_MEM_CTRL register.
851 *
852 * The TXGAIN_MEM_CTRL register will be read and the clk_txgain_en field's value will be returned.
853 *
854 * @return The current value of the clk_txgain_en field in the TXGAIN_MEM_CTRL register.
855 */
bt_rf_clk_txgain_en_getf(void)856 __INLINE uint8_t bt_rf_clk_txgain_en_getf(void)
857 {
858 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
859 return ((localVal & ((uint32_t)0x00000100)) >> 8);
860 }
861
862 /**
863 * @brief Sets the clk_txgain_en field of the TXGAIN_MEM_CTRL register.
864 *
865 * The TXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
866 *
867 * @param[in] clktxgainen - The value to set the field to.
868 */
bt_rf_clk_txgain_en_setf(uint8_t clktxgainen)869 __INLINE void bt_rf_clk_txgain_en_setf(uint8_t clktxgainen)
870 {
871 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000100)) | ((uint32_t)clktxgainen << 8));
872 }
873
874 /**
875 * @brief Returns the current value of the txgain_mem_cfg field in the TXGAIN_MEM_CTRL register.
876 *
877 * The TXGAIN_MEM_CTRL register will be read and the txgain_mem_cfg field's value will be returned.
878 *
879 * @return The current value of the txgain_mem_cfg field in the TXGAIN_MEM_CTRL register.
880 */
bt_rf_txgain_mem_cfg_getf(void)881 __INLINE uint8_t bt_rf_txgain_mem_cfg_getf(void)
882 {
883 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
884 return ((localVal & ((uint32_t)0x00000080)) >> 7);
885 }
886
887 /**
888 * @brief Sets the txgain_mem_cfg field of the TXGAIN_MEM_CTRL register.
889 *
890 * The TXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
891 *
892 * @param[in] txgainmemcfg - The value to set the field to.
893 */
bt_rf_txgain_mem_cfg_setf(uint8_t txgainmemcfg)894 __INLINE void bt_rf_txgain_mem_cfg_setf(uint8_t txgainmemcfg)
895 {
896 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000080)) | ((uint32_t)txgainmemcfg << 7));
897 }
898
899 /**
900 * @brief Returns the current value of the txgain_mem_ren_pulse field in the TXGAIN_MEM_CTRL register.
901 *
902 * The TXGAIN_MEM_CTRL register will be read and the txgain_mem_ren_pulse field's value will be returned.
903 *
904 * @return The current value of the txgain_mem_ren_pulse field in the TXGAIN_MEM_CTRL register.
905 */
bt_rf_txgain_mem_ren_pulse_getf(void)906 __INLINE uint8_t bt_rf_txgain_mem_ren_pulse_getf(void)
907 {
908 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
909 return ((localVal & ((uint32_t)0x00000040)) >> 6);
910 }
911
912 /**
913 * @brief Sets the txgain_mem_ren_pulse field of the TXGAIN_MEM_CTRL register.
914 *
915 * The TXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
916 *
917 * @param[in] txgainmemrenpulse - The value to set the field to.
918 */
bt_rf_txgain_mem_ren_pulse_setf(uint8_t txgainmemrenpulse)919 __INLINE void bt_rf_txgain_mem_ren_pulse_setf(uint8_t txgainmemrenpulse)
920 {
921 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000040)) | ((uint32_t)txgainmemrenpulse << 6));
922 }
923
924 /**
925 * @brief Returns the current value of the txgain_mem_wen_pulse field in the TXGAIN_MEM_CTRL register.
926 *
927 * The TXGAIN_MEM_CTRL register will be read and the txgain_mem_wen_pulse field's value will be returned.
928 *
929 * @return The current value of the txgain_mem_wen_pulse field in the TXGAIN_MEM_CTRL register.
930 */
bt_rf_txgain_mem_wen_pulse_getf(void)931 __INLINE uint8_t bt_rf_txgain_mem_wen_pulse_getf(void)
932 {
933 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
934 return ((localVal & ((uint32_t)0x00000020)) >> 5);
935 }
936
937 /**
938 * @brief Sets the txgain_mem_wen_pulse field of the TXGAIN_MEM_CTRL register.
939 *
940 * The TXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
941 *
942 * @param[in] txgainmemwenpulse - The value to set the field to.
943 */
bt_rf_txgain_mem_wen_pulse_setf(uint8_t txgainmemwenpulse)944 __INLINE void bt_rf_txgain_mem_wen_pulse_setf(uint8_t txgainmemwenpulse)
945 {
946 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x00000020)) | ((uint32_t)txgainmemwenpulse << 5));
947 }
948
949 /**
950 * @brief Returns the current value of the txgain_mem_addr_cfg field in the TXGAIN_MEM_CTRL register.
951 *
952 * The TXGAIN_MEM_CTRL register will be read and the txgain_mem_addr_cfg field's value will be returned.
953 *
954 * @return The current value of the txgain_mem_addr_cfg field in the TXGAIN_MEM_CTRL register.
955 */
bt_rf_txgain_mem_addr_cfg_getf(void)956 __INLINE uint8_t bt_rf_txgain_mem_addr_cfg_getf(void)
957 {
958 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR);
959 return ((localVal & ((uint32_t)0x0000001F)) >> 0);
960 }
961
962 /**
963 * @brief Sets the txgain_mem_addr_cfg field of the TXGAIN_MEM_CTRL register.
964 *
965 * The TXGAIN_MEM_CTRL register will be read, modified to contain the new field value, and written.
966 *
967 * @param[in] txgainmemaddrcfg - The value to set the field to.
968 */
bt_rf_txgain_mem_addr_cfg_setf(uint8_t txgainmemaddrcfg)969 __INLINE void bt_rf_txgain_mem_addr_cfg_setf(uint8_t txgainmemaddrcfg)
970 {
971 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_CTRL_ADDR, (PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_CTRL_ADDR) & ~((uint32_t)0x0000001F)) | ((uint32_t)txgainmemaddrcfg << 0));
972 }
973
974 /// @}
975
976 /**
977 * @name TXGAIN_MEM_WD register definitions
978 * <table>
979 * <caption id="TXGAIN_MEM_WD_BF">TXGAIN_MEM_WD bitfields</caption>
980 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value
981 * <tr><td>31:00 <td> txgain_mem_wdata <td>R <td>R/W <td>0x0
982 * </table>
983 *
984 * @{
985 */
986
987 /// Address of the TXGAIN_MEM_WD register
988 #define BT_RF_TXGAIN_MEM_WD_ADDR 0x40622068
989 /// Offset of the TXGAIN_MEM_WD register from the base address
990 #define BT_RF_TXGAIN_MEM_WD_OFFSET 0x00000068
991 /// Index of the TXGAIN_MEM_WD register
992 #define BT_RF_TXGAIN_MEM_WD_INDEX 0x0000001A
993 /// Reset value of the TXGAIN_MEM_WD register
994 #define BT_RF_TXGAIN_MEM_WD_RESET 0x00000000
995
996 /**
997 * @brief Returns the current value of the TXGAIN_MEM_WD register.
998 * The TXGAIN_MEM_WD register will be read and its value returned.
999 * @return The current value of the TXGAIN_MEM_WD register.
1000 */
bt_rf_txgain_mem_wd_get(void)1001 __INLINE uint32_t bt_rf_txgain_mem_wd_get(void)
1002 {
1003 return PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_WD_ADDR);
1004 }
1005
1006 /**
1007 * @brief Sets the TXGAIN_MEM_WD register to a value.
1008 * The TXGAIN_MEM_WD register will be written.
1009 * @param value - The value to write.
1010 */
bt_rf_txgain_mem_wd_set(uint32_t value)1011 __INLINE void bt_rf_txgain_mem_wd_set(uint32_t value)
1012 {
1013 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_WD_ADDR, value);
1014 }
1015
1016 // field definitions
1017 /// TXGAIN_MEM_WDATA field mask
1018 #define BT_RF_TXGAIN_MEM_WDATA_MASK ((uint32_t)0xFFFFFFFF)
1019 /// TXGAIN_MEM_WDATA field LSB position
1020 #define BT_RF_TXGAIN_MEM_WDATA_LSB 0
1021 /// TXGAIN_MEM_WDATA field width
1022 #define BT_RF_TXGAIN_MEM_WDATA_WIDTH ((uint32_t)0x00000020)
1023
1024 /// TXGAIN_MEM_WDATA field reset value
1025 #define BT_RF_TXGAIN_MEM_WDATA_RST 0x0
1026
1027 /**
1028 * @brief Returns the current value of the txgain_mem_wdata field in the TXGAIN_MEM_WD register.
1029 *
1030 * The TXGAIN_MEM_WD register will be read and the txgain_mem_wdata field's value will be returned.
1031 *
1032 * @return The current value of the txgain_mem_wdata field in the TXGAIN_MEM_WD register.
1033 */
bt_rf_txgain_mem_wdata_getf(void)1034 __INLINE uint32_t bt_rf_txgain_mem_wdata_getf(void)
1035 {
1036 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_WD_ADDR);
1037 return (localVal >> 0);
1038 }
1039
1040 /**
1041 * @brief Sets the txgain_mem_wdata field of the TXGAIN_MEM_WD register.
1042 *
1043 * The TXGAIN_MEM_WD register will be read, modified to contain the new field value, and written.
1044 *
1045 * @param[in] txgainmemwdata - The value to set the field to.
1046 */
bt_rf_txgain_mem_wdata_setf(uint32_t txgainmemwdata)1047 __INLINE void bt_rf_txgain_mem_wdata_setf(uint32_t txgainmemwdata)
1048 {
1049 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_WD_ADDR, (uint32_t)txgainmemwdata << 0);
1050 }
1051
1052 /// @}
1053
1054 /**
1055 * @name TXGAIN_MEM_RD register definitions
1056 * <table>
1057 * <caption id="TXGAIN_MEM_RD_BF">TXGAIN_MEM_RD bitfields</caption>
1058 * <tr><th>Bits <th>Field Name <th>HW Access <th>SW Access <th>Reset Value
1059 * <tr><td>31:00 <td> txgain_mem_rdata <td>R <td>R/W <td>0x0
1060 * </table>
1061 *
1062 * @{
1063 */
1064
1065 /// Address of the TXGAIN_MEM_RD register
1066 #define BT_RF_TXGAIN_MEM_RD_ADDR 0x4062206C
1067 /// Offset of the TXGAIN_MEM_RD register from the base address
1068 #define BT_RF_TXGAIN_MEM_RD_OFFSET 0x0000006C
1069 /// Index of the TXGAIN_MEM_RD register
1070 #define BT_RF_TXGAIN_MEM_RD_INDEX 0x0000001B
1071 /// Reset value of the TXGAIN_MEM_RD register
1072 #define BT_RF_TXGAIN_MEM_RD_RESET 0x00000000
1073
1074 /**
1075 * @brief Returns the current value of the TXGAIN_MEM_RD register.
1076 * The TXGAIN_MEM_RD register will be read and its value returned.
1077 * @return The current value of the TXGAIN_MEM_RD register.
1078 */
bt_rf_txgain_mem_rd_get(void)1079 __INLINE uint32_t bt_rf_txgain_mem_rd_get(void)
1080 {
1081 return PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_RD_ADDR);
1082 }
1083
1084 /**
1085 * @brief Sets the TXGAIN_MEM_RD register to a value.
1086 * The TXGAIN_MEM_RD register will be written.
1087 * @param value - The value to write.
1088 */
bt_rf_txgain_mem_rd_set(uint32_t value)1089 __INLINE void bt_rf_txgain_mem_rd_set(uint32_t value)
1090 {
1091 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_RD_ADDR, value);
1092 }
1093
1094 // field definitions
1095 /// TXGAIN_MEM_RDATA field mask
1096 #define BT_RF_TXGAIN_MEM_RDATA_MASK ((uint32_t)0xFFFFFFFF)
1097 /// TXGAIN_MEM_RDATA field LSB position
1098 #define BT_RF_TXGAIN_MEM_RDATA_LSB 0
1099 /// TXGAIN_MEM_RDATA field width
1100 #define BT_RF_TXGAIN_MEM_RDATA_WIDTH ((uint32_t)0x00000020)
1101
1102 /// TXGAIN_MEM_RDATA field reset value
1103 #define BT_RF_TXGAIN_MEM_RDATA_RST 0x0
1104
1105 /**
1106 * @brief Returns the current value of the txgain_mem_rdata field in the TXGAIN_MEM_RD register.
1107 *
1108 * The TXGAIN_MEM_RD register will be read and the txgain_mem_rdata field's value will be returned.
1109 *
1110 * @return The current value of the txgain_mem_rdata field in the TXGAIN_MEM_RD register.
1111 */
bt_rf_txgain_mem_rdata_getf(void)1112 __INLINE uint32_t bt_rf_txgain_mem_rdata_getf(void)
1113 {
1114 uint32_t localVal = PLATFORM_REG_READ(BT_RF_TXGAIN_MEM_RD_ADDR);
1115 return (localVal >> 0);
1116 }
1117
1118 /**
1119 * @brief Sets the txgain_mem_rdata field of the TXGAIN_MEM_RD register.
1120 *
1121 * The TXGAIN_MEM_RD register will be read, modified to contain the new field value, and written.
1122 *
1123 * @param[in] txgainmemrdata - The value to set the field to.
1124 */
bt_rf_txgain_mem_rdata_setf(uint32_t txgainmemrdata)1125 __INLINE void bt_rf_txgain_mem_rdata_setf(uint32_t txgainmemrdata)
1126 {
1127 PLATFORM_REG_WRITE(BT_RF_TXGAIN_MEM_RD_ADDR, (uint32_t)txgainmemrdata << 0);
1128 }
1129
1130 /// @}
1131
1132
1133 #endif // _REG_BT_RF_H_
1134
1135 /// @}
1136
1137