1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_DSI_H__ 16 #define __REG_DSI_H__ 17 18 #include "plat_types.h" 19 20 struct DSI_REG_T { 21 __IO uint32_t REG_000; 22 __IO uint32_t REG_004; 23 __IO uint32_t REG_008; 24 __IO uint32_t REG_00C; 25 __IO uint32_t REG_010; 26 __IO uint32_t REG_014; 27 __IO uint32_t REG_018; 28 __IO uint32_t REG_01C; 29 __IO uint32_t REG_020; 30 __IO uint32_t REG_024; 31 __IO uint32_t REG_028; 32 __IO uint32_t REG_02C; 33 __IO uint32_t REG_030; 34 __IO uint32_t REG_034; 35 __IO uint32_t REG_038; 36 __IO uint32_t REG_03C; 37 __IO uint32_t REG_040; 38 __IO uint32_t REG_044; 39 __IO uint32_t REG_048; 40 __IO uint32_t REG_RES[5]; 41 __IO uint32_t REG_060; 42 __IO uint32_t REG_064; 43 __IO uint32_t REG_068; 44 __IO uint32_t REG_06C; 45 __IO uint32_t REG_070; 46 __IO uint32_t REG_074; 47 }; 48 49 // reg_00 50 #define DSI_R_LANE_NUM(n) (((n) & 0x3) << 0) 51 #define DSI_R_LANE_NUM_MASK (0x3 << 0) 52 #define DSI_R_LANE_NUM_SHIFT (0) 53 #define DSI_R_LPCD_EN (1 << 2) 54 #define DSI_R_LPCD_DLY(n) (((n) & 0x3) << 3) 55 #define DSI_R_LPCD_DLY_MASK (0x3 << 3) 56 #define DSI_R_LPCD_DLY_SHIFT (3) 57 #define DSI_R_HSA_LP (1 << 5) 58 #define DSI_R_HSE_EN (1 << 6) 59 #define DSI_R_HBP_LP (1 << 7) 60 #define DSI_R_HFP_LP (1 << 8) 61 #define DSI_R_EOTP_EN (1 << 9) 62 #define DSI_R_CLANE_LP_EN (1 << 10) 63 #define DSI_R_VIDEO_MODE (1 << 11) 64 #define DSI_R_T_BTA(n) (((n) & 0xF) << 12) 65 #define DSI_R_T_BTA_MASK (0xF << 12) 66 #define DSI_R_T_BTA_SHIFT (12) 67 #define DSI_R_T_LPX(n) (((n) & 0xF) << 16) 68 #define DSI_R_T_LPX_MASK (0xF << 16) 69 #define DSI_R_T_LPX_SHIFT (16) 70 #define DSI_R_CLK_T_LPX(n) (((n) & 0xF) << 20) 71 #define DSI_R_CLK_T_LPX_MASK (0xF << 20) 72 #define DSI_R_CLK_T_LPX_SHIFT (20) 73 #define DSI_R_CLK_PRE(n) (((n) & 0x3) << 24) 74 #define DSI_R_CLK_PRE_MASK (0x3 << 24) 75 #define DSI_R_CLK_PRE_SHIFT (24) 76 #define DSI_R_CLK_POST(n) (((n) & 0x3F) << 26) 77 #define DSI_R_CLK_POST_MASK (0x3F << 26) 78 #define DSI_R_CLK_POST_SHIFT (26) 79 80 // reg_04 81 #define DSI_R_HS_EXIT_TIME(n) (((n) & 0x3F) << 0) 82 #define DSI_R_HS_EXIT_TIME_MASK (0x3F << 0) 83 #define DSI_R_HS_EXIT_TIME_SHIFT (0) 84 #define DSI_R_HS_PRPR_TIME(n) (((n) & 0xF) << 6) 85 #define DSI_R_HS_PRPR_TIME_MASK (0xF << 6) 86 #define DSI_R_HS_PRPR_TIME_SHIFT (6) 87 #define DSI_R_HS_ZERO_TIME(n) (((n) & 0x3F) << 10) 88 #define DSI_R_HS_ZERO_TIME_MASK (0x3F << 10) 89 #define DSI_R_HS_ZERO_TIME_SHIFT (10) 90 #define DSI_R_HS_TRAIL_TIME(n) (((n) & 0x3F) << 16) 91 #define DSI_R_HS_TRAIL_TIME_MASK (0x3F << 16) 92 #define DSI_R_HS_TRAIL_TIME_SHIFT (16) 93 #define DSI_R_T_WAKEUP(n) (((n) & 0x3FF) << 22) 94 #define DSI_R_T_WAKEUP_MASK (0x3FF << 22) 95 #define DSI_R_T_WAKEUP_SHIFT (22) 96 97 // reg_08 98 #define DSI_R_CLK_EXIT_TIME(n) (((n) & 0x3F) << 0) 99 #define DSI_R_CLK_EXIT_TIME_MASK (0x3F << 0) 100 #define DSI_R_CLK_EXIT_TIME_SHIFT (0) 101 #define DSI_R_CLK_PRPR_TIME(n) (((n) & 0xF) << 6) 102 #define DSI_R_CLK_PRPR_TIME_MASK (0xF << 6) 103 #define DSI_R_CLK_PRPR_TIME_SHIFT (6) 104 #define DSI_R_CLK_ZERO_TIME(n) (((n) & 0x3F) << 10) 105 #define DSI_R_CLK_ZERO_TIME_MASK (0x3F << 10) 106 #define DSI_R_CLK_ZERO_TIME_SHIFT (10) 107 #define DSI_R_CLK_TRAIL_TIME(n) (((n) & 0x3F) << 16) 108 #define DSI_R_CLK_TRAIL_TIME_MASK (0x3F << 16) 109 #define DSI_R_CLK_TRAIL_TIME_SHIFT (16) 110 #define DSI_R_CLK_T_WAKEUP(n) (((n) & 0x3FF) << 22) 111 #define DSI_R_CLK_T_WAKEUP_MASK (0x3FF << 22) 112 #define DSI_R_CLK_T_WAKEUP_SHIFT (22) 113 114 // reg_0c 115 #define DSI_R_DTYPE(n) (((n) & 0x3F) << 0) 116 #define DSI_R_DTYPE_MASK (0x3F << 0) 117 #define DSI_R_DTYPE_SHIFT (0) 118 #define DSI_R_VC_CH_ID(n) (((n) & 0x3) << 6) 119 #define DSI_R_VC_CH_ID_MASK (0x3 << 6) 120 #define DSI_R_VC_CH_ID_SHIFT (6) 121 #define DSI_R_VIDEO_PACKET_LENTH(n) (((n) & 0xFFFF) << 8) 122 #define DSI_R_VIDEO_PACKET_LENTH_MASK (0xFFFF << 8) 123 #define DSI_R_VIDEO_PACKET_LENTH_SHIFT (8) 124 #define DSI_R_INPUT_TYPE(n) (((n) & 0x3) << 24) 125 #define DSI_R_INPUT_TYPE_MASK (0x3 << 24) 126 #define DSI_R_INPUT_TYPE_SHIFT (24) 127 #define DSI_R_DLANE_AD_TIME(n) (((n) & 0x3F) << 26) 128 #define DSI_R_DLANE_AD_TIME_MASK (0x3F << 26) 129 #define DSI_R_DLANE_AD_TIME_SHIFT (26) 130 131 // reg_10 132 #define DSI_LPRX_DATA(n) (((n) & 0xFF) << 0) 133 #define DSI_LPRX_DATA_MASK (0xFF << 0) 134 #define DSI_LPRX_DATA_SHIFT (0) 135 #define DSI_LPRX_SIZE(n) (((n) & 0x1F) << 8) 136 #define DSI_LPRX_SIZE_MASK (0x1F << 8) 137 #define DSI_LPRX_SIZE_SHIFT (8) 138 #define DSI_HS_CMD_RD_EN (1 << 14) 139 #define DSI_LPRX_RD_EN (1 << 15) 140 #define DSI_CMD_DONE_FLAG (1 << 16) 141 #define DSI_BTA_DONE_FLAG (1 << 17) 142 #define DSI_BTA_FAIL_FLAG (1 << 18) 143 #define DSI_LP_RX_DONE_FLAG (1 << 19) 144 #define DSI_RX_ERR_FLAG (1 << 20) 145 #define DSI_LPCD_FLAG (1 << 21) 146 #define DSI_RX_TIMEOUT_FLAG (1 << 22) 147 #define DSI_TE_INTR (1 << 23) 148 #define DSI_INTR_MASK(n) (((n) & 0xFF) << 24) 149 #define DSI_INTR_MASK_MASK (0xFF << 24) 150 #define DSI_INTR_MASK_SHIFT (24) 151 #define DSI_FLAG_MASK(n) (((n) & 0xFF) << 16) 152 #define DSI_FLAG_MASK_MASK (0xFF << 16) 153 #define DSI_FLAG_MASK_SHIFT (16) 154 155 // reg_14 156 #define DSI_CMD_TYPE(n) (((n) & 0x7) << 0) 157 #define DSI_CMD_TYPE_MASK (0x7 << 0) 158 #define DSI_CMD_TYPE_SHIFT (0) 159 #define DSI_FLUSH_CMD_PRE (1 << 3) 160 #define DSI_LP_CMD_VALID (1 << 4) 161 #define DSI_HS_CMD_VALID (1 << 5) 162 #define DSI_BTA_VALID (1 << 6) 163 #define DSI_ESC_CMD(n) (((n) & 0xFF) << 8) 164 #define DSI_ESC_CMD_MASK (0xFF << 8) 165 #define DSI_ESC_CMD_SHIFT (8) 166 #define DSI_R_SOFT_CMD_LENGTH(n) (((n) & 0xFFF) << 16) 167 #define DSI_R_SOFT_CMD_LENGTH_MASK (0xFFF << 16) 168 #define DSI_R_SOFT_CMD_LENGTH_SHIFT (16) 169 170 // reg_30 171 #define DSI_OV_FLAG (1 << 0) 172 #define DSI_UN_FLAG (1 << 1) 173 #define DSI_CTRL_STX(n) (((n) & 0x1F) << 8) 174 #define DSI_CTRL_STX_MASK (0x1F << 8) 175 #define DSI_CTRL_STX_SHIFT (8) 176 #define DSI_CTRL_ST(n) (((n) & 0xF) << 13) 177 #define DSI_CTRL_ST_MASK (0xF << 13) 178 #define DSI_CTRL_ST_SHIFT (13) 179 #define DSI_HS_CTRL_ST(n) (((n) & 0xF) << 17) 180 #define DSI_HS_CTRL_ST_MASK (0xF << 17) 181 #define DSI_HS_CTRL_ST_SHIFT (17) 182 183 // reg_40 184 #define DSI_R_HTOTAL(n) (((n) & 0xFFF) << 0) 185 #define DSI_R_HTOTAL_MASK (0xFFF << 0) 186 #define DSI_R_HTOTAL_SHIFT (0) 187 #define DSI_R_HSTART(n) (((n) & 0xFF) << 12) 188 #define DSI_R_HSTART_MASK (0xFF << 12) 189 #define DSI_R_HSTART_SHIFT (12) 190 #define DSI_R_HWIDTH(n) (((n) & 0xFFF) << 20) 191 #define DSI_R_HWIDTH_MASK (0xFFF << 20) 192 #define DSI_R_HWIDTH_SHIFT (20) 193 194 // reg_44 195 #define DSI_R_VTOTAL(n) (((n) & 0xFFF) << 0) 196 #define DSI_R_VTOTAL_MASK (0xFFF << 0) 197 #define DSI_R_VTOTAL_SHIFT (0) 198 #define DSI_R_VSTART(n) (((n) & 0xFF) << 12) 199 #define DSI_R_VSTART_MASK (0xFF << 12) 200 #define DSI_R_VSTART_SHIFT (12) 201 #define DSI_R_VHEIGHT(n) (((n) & 0xFFF) << 20) 202 #define DSI_R_VHEIGHT_MASK (0xFFF << 20) 203 #define DSI_R_VHEIGHT_SHIFT (20) 204 205 // reg_48 206 #define DSI_R_CL_DATA_SEL (1 << 0) 207 #define DSI_R_TE_EDGE_SEL (1 << 1) 208 #define DSI_R_VIDEO_SEL (1 << 2) 209 #define DSI_R_VIDEO_BIST_EN (1 << 3) 210 #define DSI_R_VIDEO_BIST_PATTERN(n) (((n) & 0x7) << 4) 211 #define DSI_R_VIDEO_BIST_PATTERN_MASK (0x7 << 4) 212 #define DSI_R_VIDEO_BIST_PATTERN_SHIFT (4) 213 #define DSI_R_COLOR_BAR_WIDTH(n) (((n) & 0xFFF) << 8) 214 #define DSI_R_COLOR_BAR_WIDTH_MASK (0xFFF << 8) 215 #define DSI_R_COLOR_BAR_WIDTH_SHIFT (8) 216 #define DSI_R_HSYNC_DLY_NUM(n) (((n) & 0xFFF) << 20) 217 #define DSI_R_HSYNC_DLY_NUM_MASK (0xFFF << 20) 218 #define DSI_R_HSYNC_DLY_NUM_SHIFT (20) 219 220 //2003 reg_60 221 #define DSI_REG_CK_LB_HS(n) (((n) & 0xFF) << 0) 222 #define DSI_REG_CK_LB_HS_MASK (0xFF << 0) 223 #define DSI_REG_CK_LB_HS_SHIFT (0) 224 #define DSI_REG_CK_LB_ZERO(n) (((n) & 0xFF) << 8) 225 #define DSI_REG_CK_LB_ZERO_MASK (0xFF << 8) 226 #define DSI_REG_CK_LB_ZERO_SHIFT (8) 227 #define DSI_REG_CK_LB_PRPR(n) (((n) & 0xFF) << 16) 228 #define DSI_REG_CK_LB_PRPR_MASK (0xFF << 16) 229 #define DSI_REG_CK_LB_PRPR_SHIFT (16) 230 #define DSI_REG_CK_LB_RQST(n) (((n) & 0xFF) << 24) 231 #define DSI_REG_CK_LB_RQST_MASK (0xFF << 24) 232 #define DSI_REG_CK_LB_RQST_SHIFT (24) 233 234 //1600 REG060 235 #define REG_EN_LPRX0_DSI (1 << 0) 236 #define REG_CLK_SWRC_DSI_SHIFT 1 237 #define REG_CLK_SWRC_DSI_MASK (0x7 << REG_CLK_SWRC_DSI_SHIFT) 238 #define REG_CLK_SWRC_DSI(n) BITFIELD_VAL(REG_CLK_SWRC_DSI, n) 239 #define REG_CLKGEN_PU_DSI (1 << 4) 240 #define REG_RX_SWAP_PN_DSI (1 << 5) 241 #define REG_SWAP_CKX1_DSI (1 << 6) 242 #define REG_SWAP_CKX8_DSI (1 << 7) 243 #define REG_PRECHARGE_LDO_DSI (1 << 8) 244 #define REG_PU_CH_DSI (1 << 9) 245 #define REG_PU_LDO_DSI (1 << 10) 246 #define REG_DSI_PHY_RSTN (1 << 11) 247 #define REG_MASK_LP_LDO (1 << 12) 248 #define REG_MASK_LP_RSTN (1 << 13) 249 #define REG_CKX8_EN (1 << 14) 250 251 //1600 REG064 252 #define REG_LDO0P4_RES_SHIFT 0 253 #define REG_LDO0P4_RES_MASK (0xF << REG_LDO0P4_RES_SHIFT) 254 #define REG_LDO0P4_RES(n) BITFIELD_VAL(REG_LDO0P4_RES, n) 255 #define REG_LDO0P8_RES_SHIFT 4 256 #define REG_LDO0P8_RES_MASK (0x7 << REG_LDO0P8_RES_SHIFT) 257 #define REG_LDO0P8_RES(n) BITFIELD_VAL(REG_LDO0P8_RES, n) 258 #define REG_LDO1P2_RES_SHIFT 8 259 #define REG_LDO1P2_RES_MASK (0x7 << REG_LDO1P2_RES_SHIFT) 260 #define REG_LDO1P2_RES(n) BITFIELD_VAL(REG_LDO1P2_RES, n) 261 #define REG_VB_LPCD_H_SHIFT 12 262 #define REG_VB_LPCD_H_MASK (0x7 << REG_VB_LPCD_H_SHIFT) 263 #define REG_VB_LPCD_H(n) BITFIELD_VAL(REG_VB_LPCD_H, n) 264 #define REG_VB_LPCD_L_SHIFT 15 265 #define REG_VB_LPCD_L_MASK (0x7 << REG_VB_LPCD_L_SHIFT) 266 #define REG_VB_LPCD_L(n) BITFIELD_VAL(REG_VB_LPCD_L, n) 267 #define REG_VB_LPRX_H_SHIFT 18 268 #define REG_VB_LPRX_H_MASK (0x7 << REG_VB_LPRX_H_SHIFT) 269 #define REG_VB_LPRX_H(n) BITFIELD_VAL(REG_VB_LPRX_H, n) 270 #define REG_VB_LPRX_L_SHIFT 21 271 #define REG_VB_LPRX_L_MASK (0x7 << REG_VB_LPRX_L_SHIFT) 272 #define REG_VB_LPRX_L(n) BITFIELD_VAL(REG_VB_LPRX_L, n) 273 274 // reg_64 275 #define DSI_REG_DATA_LB_ZERO(n) (((n) & 0xFF) << 0) 276 #define DSI_REG_DATA_LB_ZERO_MASK (0xFF << 0) 277 #define DSI_REG_DATA_LB_ZERO_SHIFT (0) 278 #define DSI_REG_DATA_LB_PRPR(n) (((n) & 0xFF) << 8) 279 #define DSI_REG_DATA_LB_PRPR_MASK (0xFF << 8) 280 #define DSI_REG_DATA_LB_PRPR_SHIFT (8) 281 #define DSI_REG_DATA_LB_RQST(n) (((n) & 0xFF) << 16) 282 #define DSI_REG_DATA_LB_RQST_MASK (0xFF << 16) 283 #define DSI_REG_DATA_LB_RQST_SHIFT (16) 284 #define DSI_REG_CK_LB_DATA_SEL (1 << 24) 285 #define DSI_REG_LOOPBACK_TEST (1 << 25) 286 287 //REG068 288 #define REG_CH0_EN_DSI (1 << 0) 289 #define REG_CH0_DLY_TUNE_DSI_SHIFT 1 290 #define REG_CH0_DLY_TUNE_DSI_MASK (0x7 << REG_CH0_DLY_TUNE_DSI_SHIFT) 291 #define REG_CH0_DLY_TUNE_DSI(n) BITFIELD_VAL(REG_CH0_DLY_TUNE_DSI, n) 292 #define REG_CH0_HSTX_DRV_DSI_SHIFT 4 293 #define REG_CH0_HSTX_DRV_DSI_MASK (0xF << REG_CH0_HSTX_DRV_DSI_SHIFT) 294 #define REG_CH0_HSTX_DRV_DSI(n) BITFIELD_VAL(REG_CH0_HSTX_DRV_DSI, n) 295 #define REG_CH0_LPTX_DRV_DSI_SHIFT 8 296 #define REG_CH0_LPTX_DRV_DSI_MASK (0x7 << REG_CH0_LPTX_DRV_DSI_SHIFT) 297 #define REG_CH0_LPTX_DRV_DSI(n) BITFIELD_VAL(REG_CH0_LPTX_DRV_DSI, n) 298 #define REG_CH0_PULL_DN_DSI (1 << 11) 299 #define REG_CH0_SWAP_PN_DSI (1 << 12) 300 #define RESERVED_DSI_11_9_SHIFT 13 301 #define RESERVED_DSI_11_9_MASK (0x7 << RESERVED_DSI_11_9_SHIFT) 302 #define RESERVED_DSI_11_9(n) BITFIELD_VAL(RESERVED_DSI_11_9, n) 303 304 //REG06C 305 #define REG_CH1_EN_DSI (1 << 0) 306 #define REG_CH1_DLY_TUNE_DSI_SHIFT 1 307 #define REG_CH1_DLY_TUNE_DSI_MASK (0x7 << REG_CH1_DLY_TUNE_DSI_SHIFT) 308 #define REG_CH1_DLY_TUNE_DSI(n) BITFIELD_VAL(REG_CH1_DLY_TUNE_DSI, n) 309 #define REG_CH1_HSTX_DRV_DSI_SHIFT 4 310 #define REG_CH1_HSTX_DRV_DSI_MASK (0xF << REG_CH1_HSTX_DRV_DSI_SHIFT) 311 #define REG_CH1_HSTX_DRV_DSI(n) BITFIELD_VAL(REG_CH1_HSTX_DRV_DSI, n) 312 #define REG_CH1_LPTX_DRV_DSI_SHIFT 8 313 #define REG_CH1_LPTX_DRV_DSI_MASK (0x7 << REG_CH1_LPTX_DRV_DSI_SHIFT) 314 #define REG_CH1_LPTX_DRV_DSI(n) BITFIELD_VAL(REG_CH1_LPTX_DRV_DSI, n) 315 #define REG_CH1_PULL_DN_DSI (1 << 11) 316 #define REG_CH1_SWAP_PN_DSI (1 << 12) 317 #define RESERVED_DSI_14_12_SHIFT 13 318 #define RESERVED_DSI_14_12_MASK (0x7 << RESERVED_DSI_14_12_SHIFT) 319 #define RESERVED_DSI_14_12(n) BITFIELD_VAL(RESERVED_DSI_14_12, n) 320 321 //REG070 322 #define REG_CHCK_EN_DSI (1 << 0) 323 #define REG_CHCK_DLY_TUNE_DSI_SHIFT 1 324 #define REG_CHCK_DLY_TUNE_DSI_MASK (0x7 << REG_CHCK_DLY_TUNE_DSI_SHIFT) 325 #define REG_CHCK_DLY_TUNE_DSI(n) BITFIELD_VAL(REG_CHCK_DLY_TUNE_DSI, n) 326 #define REG_CHCK_HSTX_DRV_DSI_SHIFT 4 327 #define REG_CHCK_HSTX_DRV_DSI_MASK (0xF << REG_CHCK_HSTX_DRV_DSI_SHIFT) 328 #define REG_CHCK_HSTX_DRV_DSI(n) BITFIELD_VAL(REG_CHCK_HSTX_DRV_DSI, n) 329 #define REG_CHCK_LPTX_DRV_DSI_SHIFT 8 330 #define REG_CHCK_LPTX_DRV_DSI_MASK (0x7 << REG_CHCK_LPTX_DRV_DSI_SHIFT) 331 #define REG_CHCK_LPTX_DRV_DSI(n) BITFIELD_VAL(REG_CHCK_LPTX_DRV_DSI, n) 332 #define REG_CHCK_PULL_DN_DSI (1 << 11) 333 #define REG_CHCK_SWAP_PN_DSI (1 << 12) 334 #define REG_PRECHARGE_LDO_CNT_SHIFT 13 335 #define REG_PRECHARGE_LDO_CNT_MASK (0x3ff << REG_PRECHARGE_LDO_CNT_SHIFT) 336 #define REG_PRECHARGE_LDO_CNT(n) BITFIELD_VAL(REG_PRECHARGE_LDO_CNT,n) 337 338 // reg_74 339 #define DSI_R_HSW(n) (((n) & 0x7F) << 0) 340 #define DSI_R_HSW_MASK (0x7F << 0) 341 #define DSI_R_HSW_SHIFT (0) 342 #define DSI_R_VSW(n) (((n) & 0x7F) << 7) 343 #define DSI_R_VSW_MASK (0x7F << 7) 344 #define DSI_R_VSW_SHIFT (7) 345 #define DSI_R_HS_TRAIL_TIME2(n) (((n) & 0x3F) << 16) 346 #define DSI_R_HS_TRAIL_TIME2_MASK (0x3F << 16) 347 #define DSI_R_HS_TRAIL_TIME2_SHIFT (16) 348 349 #endif 350 351