1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef NPE_REG_H 19 #define NPE_REG_H 20 #include "../sys.h" 21 #define NPE_BASE_ADDR 0x112000 22 #define reg_npe_addr(addr) ((addr)-CPU_DLM_BASE + DLM_BASE) 23 #define reg_npe_0x40 REG_ADDR32(NPE_BASE_ADDR + 0x40) 24 #define reg_npe_0x6c REG_ADDR32(NPE_BASE_ADDR + 0x6c) 25 #define reg_npe_0x84 REG_ADDR32(NPE_BASE_ADDR + 0x84) 26 #define reg_npe_0x74 REG_ADDR32(NPE_BASE_ADDR + 0x74) 27 #define reg_npe_0x80 REG_ADDR32(NPE_BASE_ADDR + 0x80) 28 #define reg_npe_0x84 REG_ADDR32(NPE_BASE_ADDR + 0x84) 29 30 #define reg_npe_irq_0 REG_ADDR8(STIMER_BASE_ADDR + 0x20) 31 enum { 32 FLD_IRQ_NPE_BUS0 = BIT(0), 33 FLD_IRQ_NPE_BUS1 = BIT(1), 34 FLD_IRQ_NPE_BUS2 = BIT(2), 35 FLD_IRQ_NPE_BUS3 = BIT(3), 36 FLD_IRQ_NPE_BUS4 = BIT(4), 37 FLD_IRQ_NPE_BUS7 = BIT(7), 38 }; 39 40 #define reg_npe_irq_1 REG_ADDR8(STIMER_BASE_ADDR + 0x21) 41 enum { 42 FLD_IRQ_NPE_BUS8 = BIT(0), 43 FLD_IRQ_NPE_BUS13 = BIT(5), 44 FLD_IRQ_NPE_BUS14 = BIT(6), 45 FLD_IRQ_NPE_BUS15 = BIT(7), 46 }; 47 48 #define reg_npe_irq_2 REG_ADDR8(STIMER_BASE_ADDR + 0x22) 49 enum { 50 FLD_IRQ_NPE_BUS17 = BIT(1), 51 FLD_IRQ_NPE_BUS21 = BIT(5), 52 FLD_IRQ_NPE_BUS22 = BIT(6), 53 FLD_IRQ_NPE_BUS23 = BIT(7), 54 }; 55 56 #define reg_npe_irq_3 REG_ADDR8(STIMER_BASE_ADDR + 0x23) 57 enum { 58 FLD_IRQ_NPE_BUS24 = BIT(0), 59 FLD_IRQ_NPE_BUS25 = BIT(1), 60 FLD_IRQ_NPE_BUS26 = BIT(2), 61 FLD_IRQ_NPE_BUS27 = BIT(3), 62 FLD_IRQ_NPE_BUS28 = BIT(4), 63 FLD_IRQ_NPE_BUS29 = BIT(5), 64 FLD_IRQ_NPE_BUS30 = BIT(6), 65 FLD_IRQ_NPE_BUS31 = BIT(7), 66 }; 67 #endif 68