1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_LCD_H__ 16 #define __REG_LCD_H__ 17 18 #include "plat_types.h" 19 20 struct LCDC_REG_T { 21 __IO uint32_t REG_000; 22 __IO uint32_t REG_004; 23 __IO uint32_t REG_008; 24 __IO uint32_t REG_00C; 25 __IO uint32_t REG_010; 26 __IO uint32_t REG_014; 27 __IO uint32_t REG_018; 28 __IO uint32_t REG_01C; 29 __IO uint32_t REG_020; 30 __IO uint32_t REG_024; 31 __IO uint32_t REG_028; 32 __IO uint32_t REG_02C; 33 __IO uint32_t REG_030; 34 __IO uint32_t REG_034; 35 __IO uint32_t REG_038; 36 __IO uint32_t REG_03C; 37 __IO uint32_t REG_040; 38 __IO uint32_t REG_044; 39 __IO uint32_t REG_048; 40 __IO uint32_t REG_04C; 41 __IO uint32_t REG_RESERVED0[12]; 42 __IO uint32_t REG_080; 43 __IO uint32_t REG_084; 44 __IO uint32_t REG_088; 45 __IO uint32_t REG_08C; 46 __IO uint32_t REG_RESERVED1[12]; 47 __IO uint32_t REG_0C0; 48 __IO uint32_t REG_0C4; 49 __IO uint32_t REG_0C8; 50 __IO uint32_t REG_0CC; 51 __IO uint32_t REG_0D0; 52 __IO uint32_t REG_0D4; 53 __IO uint32_t REG_0D8; 54 __IO uint32_t REG_0DC; 55 __IO uint32_t REG_0E0; 56 __IO uint32_t REG_0E4; 57 __IO uint32_t REG_0E8; 58 __IO uint32_t REG_0EC; 59 __IO uint32_t REG_0F0; 60 __IO uint32_t REG_0F4; 61 __IO uint32_t REG_0F8; 62 __IO uint32_t REG_0FC; 63 __IO uint32_t REG_100; 64 __IO uint32_t REG_104; 65 __IO uint32_t REG_108; 66 __IO uint32_t REG_10C; 67 __IO uint32_t REG_110; 68 __IO uint32_t REG_114; 69 __IO uint32_t REG_118; 70 __IO uint32_t REG_11C; 71 __IO uint32_t REG_120; 72 __IO uint32_t REG_124; 73 __IO uint32_t REG_128; 74 __IO uint32_t REG_12C; 75 __IO uint32_t REG_130; 76 __IO uint32_t REG_134; 77 __IO uint32_t REG_138; 78 __IO uint32_t REG_13C; 79 __IO uint32_t REG_RESERVED2[18]; 80 __IO uint32_t REG_188; 81 __IO uint32_t REG_18C; 82 __IO uint32_t REG_190; 83 __IO uint32_t REG_194; 84 __IO uint32_t REG_198; 85 __IO uint32_t REG_19C; 86 __IO uint32_t REG_1A0; 87 __IO uint32_t REG_1A4; 88 __IO uint32_t REG_1A8; 89 __IO uint32_t REG_1AC; 90 __IO uint32_t REG_1B0; 91 __IO uint32_t REG_1B4; 92 __IO uint32_t REG_1B8; 93 __IO uint32_t REG_1BC; 94 __IO uint32_t REG_1C0; 95 __IO uint32_t REG_1C4; 96 __IO uint32_t REG_1C8; 97 __IO uint32_t REG_1CC; 98 __IO uint32_t REG_1D0; 99 __IO uint32_t REG_1D4; 100 __IO uint32_t REG_1D8; 101 __IO uint32_t REG_1DC; 102 __IO uint32_t REG_1E0; 103 __IO uint32_t REG_1E4; 104 __IO uint32_t REG_1E8; 105 __IO uint32_t REG_1EC; 106 __IO uint32_t REG_1F0; 107 __IO uint32_t REG_1F4; 108 __IO uint32_t REG_1F8; 109 __IO uint32_t REG_1FC; 110 __IO uint32_t REG_200; 111 __IO uint32_t REG_204; 112 __IO uint32_t REG_208; 113 __IO uint32_t REG_20C; 114 __IO uint32_t REG_210; 115 __IO uint32_t REG_214; 116 __IO uint32_t REG_218; 117 __IO uint32_t REG_21C; 118 __IO uint32_t REG_220; 119 __IO uint32_t REG_224; 120 __IO uint32_t REG_228; 121 __IO uint32_t REG_22C; 122 __IO uint32_t REG_230; 123 __IO uint32_t REG_234; 124 __IO uint32_t REG_238; 125 __IO uint32_t REG_23C; 126 __IO uint32_t REG_240; 127 __IO uint32_t REG_244; 128 __IO uint32_t REG_248; 129 __IO uint32_t REG_24C; 130 __IO uint32_t REG_250; 131 __IO uint32_t REG_254; 132 __IO uint32_t REG_258; 133 __IO uint32_t REG_25C; 134 __IO uint32_t REG_260; 135 __IO uint32_t REG_264; 136 }; 137 138 // reg_00 139 #define LCD_CFG_TVD_SA_Y0(n) (((n) & 0xFFFFFFFF) << 0) 140 #define LCD_CFG_TVD_SA_Y0_MASK (0xFFFFFFFF << 0) 141 #define LCD_CFG_TVD_SA_Y0_SHIFT (0) 142 143 // reg_04 144 #define LCD_CFG_TVD_SA_U0(n) (((n) & 0xFFFFFFFF) << 0) 145 #define LCD_CFG_TVD_SA_U0_MASK (0xFFFFFFFF << 0) 146 #define LCD_CFG_TVD_SA_U0_SHIFT (0) 147 148 // reg_08 149 #define LCD_CFG_TVD_SA_V0(n) (((n) & 0xFFFFFFFF) << 0) 150 #define LCD_CFG_TVD_SA_V0_MASK (0xFFFFFFFF << 0) 151 #define LCD_CFG_TVD_SA_V0_SHIFT (0) 152 153 // reg_0c 154 #define LCD_CFG_TVD_SA_C0(n) (((n) & 0xFFFFFFFF) << 0) 155 #define LCD_CFG_TVD_SA_C0_MASK (0xFFFFFFFF << 0) 156 #define LCD_CFG_TVD_SA_C0_SHIFT (0) 157 158 // reg_10 159 #define LCD_CFG_TVD_SA_Y1(n) (((n) & 0xFFFFFFFF) << 0) 160 #define LCD_CFG_TVD_SA_Y1_MASK (0xFFFFFFFF << 0) 161 #define LCD_CFG_TVD_SA_Y1_SHIFT (0) 162 163 // reg_14 164 #define LCD_CFG_TVD_SA_U1(n) (((n) & 0xFFFFFFFF) << 0) 165 #define LCD_CFG_TVD_SA_U1_MASK (0xFFFFFFFF << 0) 166 #define LCD_CFG_TVD_SA_U1_SHIFT (0) 167 168 // reg_18 169 #define LCD_CFG_TVD_SA_V1(n) (((n) & 0xFFFFFFFF) << 0) 170 #define LCD_CFG_TVD_SA_V1_MASK (0xFFFFFFFF << 0) 171 #define LCD_CFG_TVD_SA_V1_SHIFT (0) 172 173 // reg_1c 174 #define LCD_CFG_TVD_SA_C1(n) (((n) & 0xFFFFFFFF) << 0) 175 #define LCD_CFG_TVD_SA_C1_MASK (0xFFFFFFFF << 0) 176 #define LCD_CFG_TVD_SA_C1_SHIFT (0) 177 178 // reg_20 179 #define LCD_CFG_TVD_PITCH_Y(n) (((n) & 0xFFFF) << 0) 180 #define LCD_CFG_TVD_PITCH_Y_MASK (0xFFFF << 0) 181 #define LCD_CFG_TVD_PITCH_Y_SHIFT (0) 182 #define LCD_CFG_TVD_PITCH_C(n) (((n) & 0xFFFF) << 16) 183 #define LCD_CFG_TVD_PITCH_C_MASK (0xFFFF << 16) 184 #define LCD_CFG_TVD_PITCH_C_SHIFT (16) 185 186 // reg_24 187 #define LCD_CFG_TVD_PITCH_U(n) (((n) & 0xFFFF) << 0) 188 #define LCD_CFG_TVD_PITCH_U_MASK (0xFFFF << 0) 189 #define LCD_CFG_TVD_PITCH_U_SHIFT (0) 190 #define LCD_CFG_TVD_PITCH_V(n) (((n) & 0xFFFF) << 16) 191 #define LCD_CFG_TVD_PITCH_V_MASK (0xFFFF << 16) 192 #define LCD_CFG_TVD_PITCH_V_SHIFT (16) 193 194 // reg_28 195 #define LCD_CFG_TVD_OVSA_HPXL(n) (((n) & 0xFFF) << 0) 196 #define LCD_CFG_TVD_OVSA_HPXL_MASK (0xFFF << 0) 197 #define LCD_CFG_TVD_OVSA_HPXL_SHIFT (0) 198 #define LCD_CFG_TVDFRM_Y (1 << 12) 199 #define LCD_CFG_TVDFRM_U (1 << 13) 200 #define LCD_CFG_TVDFRM_V (1 << 14) 201 #define LCD_CFG_TVDFRM_C (1 << 15) 202 #define LCD_CFG_TVD_OVSA_VLN(n) (((n) & 0xFFF) << 16) 203 #define LCD_CFG_TVD_OVSA_VLN_MASK (0xFFF << 16) 204 #define LCD_CFG_TVD_OVSA_VLN_SHIFT (16) 205 #define LCD_CFG_TVDFRM_FIX (1 << 31) 206 207 // reg_2c 208 #define LCD_CFG_TVD_H_PIXEL(n) (((n) & 0xFFF) << 0) 209 #define LCD_CFG_TVD_H_PIXEL_MASK (0xFFF << 0) 210 #define LCD_CFG_TVD_H_PIXEL_SHIFT (0) 211 #define LCD_CFG_TVD_V_LINE(n) (((n) & 0xFFF) << 16) 212 #define LCD_CFG_TVD_V_LINE_MASK (0xFFF << 16) 213 #define LCD_CFG_TVD_V_LINE_SHIFT (16) 214 215 // reg_30 216 #define LCD_CFG_TVDZM_H_PIXEL(n) (((n) & 0xFFF) << 0) 217 #define LCD_CFG_TVDZM_H_PIXEL_MASK (0xFFF << 0) 218 #define LCD_CFG_TVDZM_H_PIXEL_SHIFT (0) 219 #define LCD_CFG_TVDZM_V_LINE(n) (((n) & 0xFFF) << 16) 220 #define LCD_CFG_TVDZM_V_LINE_MASK (0xFFF << 16) 221 #define LCD_CFG_TVDZM_V_LINE_SHIFT (16) 222 223 // reg_34 224 #define LCD_CFG_TVG_SA0(n) (((n) & 0xFFFFFFFF) << 0) 225 #define LCD_CFG_TVG_SA0_MASK (0xFFFFFFFF << 0) 226 #define LCD_CFG_TVG_SA0_SHIFT (0) 227 228 // reg_38 229 #define LCD_CFG_TVG_SA1(n) (((n) & 0xFFFFFFFF) << 0) 230 #define LCD_CFG_TVG_SA1_MASK (0xFFFFFFFF << 0) 231 #define LCD_CFG_TVG_SA1_SHIFT (0) 232 233 // reg_3c 234 #define LCD_CFG_TVG_PITCH(n) (((n) & 0xFFFF) << 0) 235 #define LCD_CFG_TVG_PITCH_MASK (0xFFFF << 0) 236 #define LCD_CFG_TVG_PITCH_SHIFT (0) 237 #define LCD_CFG_TV_BKLIGHTDIV(n) (((n) & 0xFFF) << 16) 238 #define LCD_CFG_TV_BKLIGHTDIV_MASK (0xFFF << 16) 239 #define LCD_CFG_TV_BKLIGHTDIV_SHIFT (16) 240 #define LCD_CFG_TV_BKLIGHTDIV_CTRL(n) (((n) & 0xF) << 28) 241 #define LCD_CFG_TV_BKLIGHTDIV_CTRL_MASK (0xF << 28) 242 #define LCD_CFG_TV_BKLIGHTDIV_CTRL_SHIFT (28) 243 244 // reg_40 245 #define LCD_CFG_TVG_OVSA_HPXL(n) (((n) & 0xFFF) << 0) 246 #define LCD_CFG_TVG_OVSA_HPXL_MASK (0xFFF << 0) 247 #define LCD_CFG_TVG_OVSA_HPXL_SHIFT (0) 248 #define LCD_CFG_TVGFRM_Y (1 << 12) 249 #define LCD_CFG_TVG_OVSA_VLN(n) (((n) & 0xFFF) << 16) 250 #define LCD_CFG_TVG_OVSA_VLN_MASK (0xFFF << 16) 251 #define LCD_CFG_TVG_OVSA_VLN_SHIFT (16) 252 #define LCD_CFG_TVGFRM_FIX (1 << 31) 253 254 // reg_44 255 #define LCD_CFG_TVG_H_PIXEL(n) (((n) & 0xFFF) << 0) 256 #define LCD_CFG_TVG_H_PIXEL_MASK (0xFFF << 0) 257 #define LCD_CFG_TVG_H_PIXEL_SHIFT (0) 258 #define LCD_CFG_TVG_V_LINE(n) (((n) & 0xFFF) << 16) 259 #define LCD_CFG_TVG_V_LINE_MASK (0xFFF << 16) 260 #define LCD_CFG_TVG_V_LINE_SHIFT (16) 261 262 // reg_48 263 #define LCD_CFG_TVGZM_H_PIXEL(n) (((n) & 0xFFF) << 0) 264 #define LCD_CFG_TVGZM_H_PIXEL_MASK (0xFFF << 0) 265 #define LCD_CFG_TVGZM_H_PIXEL_SHIFT (0) 266 #define LCD_CFG_TVGZM_V_LINE(n) (((n) & 0xFFF) << 16) 267 #define LCD_CFG_TVGZM_V_LINE_MASK (0xFFF << 16) 268 #define LCD_CFG_TVGZM_V_LINE_SHIFT (16) 269 270 // reg_4c 271 #define LCD_CFG_TVC_OVSA_HPXL(n) (((n) & 0xFFF) << 0) 272 #define LCD_CFG_TVC_OVSA_HPXL_MASK (0xFFF << 0) 273 #define LCD_CFG_TVC_OVSA_HPXL_SHIFT (0) 274 #define LCD_CFG_TVC_OVSA_VLN(n) (((n) & 0xFFF) << 16) 275 #define LCD_CFG_TVC_OVSA_VLN_MASK (0xFFF << 16) 276 #define LCD_CFG_TVC_OVSA_VLN_SHIFT (16) 277 278 // reg_50 279 #define LCD_CFG_TVC_PHXL(n) (((n) & 0xFFF) << 0) 280 #define LCD_CFG_TVC_PHXL_MASK (0xFFF << 0) 281 #define LCD_CFG_TVC_PHXL_SHIFT (0) 282 #define LCD_CFG_TVC_VLN(n) (((n) & 0xFFF) << 16) 283 #define LCD_CFG_TVC_VLN_MASK (0xFFF << 16) 284 #define LCD_CFG_TVC_VLN_SHIFT (16) 285 286 // reg_54 287 #define LCD_CFG_TV_H_TOTAL(n) (((n) & 0xFFF) << 0) 288 #define LCD_CFG_TV_H_TOTAL_MASK (0xFFF << 0) 289 #define LCD_CFG_TV_H_TOTAL_SHIFT (0) 290 #define LCD_CFG_TV_V_TOTAL(n) (((n) & 0xFFF) << 16) 291 #define LCD_CFG_TV_V_TOTAL_MASK (0xFFF << 16) 292 #define LCD_CFG_TV_V_TOTAL_SHIFT (16) 293 294 // reg_58 295 #define LCD_CFG_TV_H_ACTIVE(n) (((n) & 0xFFF) << 0) 296 #define LCD_CFG_TV_H_ACTIVE_MASK (0xFFF << 0) 297 #define LCD_CFG_TV_H_ACTIVE_SHIFT (0) 298 #define LCD_CFG_TV_V_ACTIVE(n) (((n) & 0xFFF) << 16) 299 #define LCD_CFG_TV_V_ACTIVE_MASK (0xFFF << 16) 300 #define LCD_CFG_TV_V_ACTIVE_SHIFT (16) 301 302 // reg_5c 303 #define LCD_CFG_TV_H_FPORCH(n) (((n) & 0xFFF) << 0) 304 #define LCD_CFG_TV_H_FPORCH_MASK (0xFFF << 0) 305 #define LCD_CFG_TV_H_FPORCH_SHIFT (0) 306 #define LCD_CFG_TV_H_BPORCH(n) (((n) & 0xFFF) << 16) 307 #define LCD_CFG_TV_H_BPORCH_MASK (0xFFF << 16) 308 #define LCD_CFG_TV_H_BPORCH_SHIFT (16) 309 310 // reg_60 311 #define LCD_CFG_TV_V_FPORCH(n) (((n) & 0xFFF) << 0) 312 #define LCD_CFG_TV_V_FPORCH_MASK (0xFFF << 0) 313 #define LCD_CFG_TV_V_FPORCH_SHIFT (0) 314 #define LCD_CFG_TV_V_BPORCH(n) (((n) & 0xFFF) << 16) 315 #define LCD_CFG_TV_V_BPORCH_MASK (0xFFF << 16) 316 #define LCD_CFG_TV_V_BPORCH_SHIFT (16) 317 318 // reg_64 319 #define LCD_CFG_TV_BLANKCOLOR(n) (((n) & 0xFFFFFF) << 0) 320 #define LCD_CFG_TV_BLANKCOLOR_MASK (0xFFFFFF << 0) 321 #define LCD_CFG_TV_BLANKCOLOR_SHIFT (0) 322 323 // reg_68 324 #define LCD_CFG_TVC_COLOR1(n) (((n) & 0xFFFFFF) << 0) 325 #define LCD_CFG_TVC_COLOR1_MASK (0xFFFFFF << 0) 326 #define LCD_CFG_TVC_COLOR1_SHIFT (0) 327 328 // reg_6c 329 #define LCD_CFG_TVC_COLOR2(n) (((n) & 0xFFFFFF) << 0) 330 #define LCD_CFG_TVC_COLOR2_MASK (0xFFFFFF << 0) 331 #define LCD_CFG_TVC_COLOR2_SHIFT (0) 332 333 // reg_70 334 #define LCD_CFG_TV_ALPHA_Y(n) (((n) & 0xFF) << 0) 335 #define LCD_CFG_TV_ALPHA_Y_MASK (0xFF << 0) 336 #define LCD_CFG_TV_ALPHA_Y_SHIFT (0) 337 #define LCD_CFG_TV_CKEY_Y(n) (((n) & 0xFF) << 8) 338 #define LCD_CFG_TV_CKEY_Y_MASK (0xFF << 8) 339 #define LCD_CFG_TV_CKEY_Y_SHIFT (8) 340 #define LCD_CFG_TV_CKEY_Y1(n) (((n) & 0xFF) << 16) 341 #define LCD_CFG_TV_CKEY_Y1_MASK (0xFF << 16) 342 #define LCD_CFG_TV_CKEY_Y1_SHIFT (16) 343 #define LCD_CFG_TV_CKEY_Y2(n) (((n) & 0xFF) << 24) 344 #define LCD_CFG_TV_CKEY_Y2_MASK (0xFF << 24) 345 #define LCD_CFG_TV_CKEY_Y2_SHIFT (24) 346 347 // reg_74 348 #define LCD_CFG_TV_ALPHA_U(n) (((n) & 0xFF) << 0) 349 #define LCD_CFG_TV_ALPHA_U_MASK (0xFF << 0) 350 #define LCD_CFG_TV_ALPHA_U_SHIFT (0) 351 #define LCD_CFG_TV_CKEY_U(n) (((n) & 0xFF) << 8) 352 #define LCD_CFG_TV_CKEY_U_MASK (0xFF << 8) 353 #define LCD_CFG_TV_CKEY_U_SHIFT (8) 354 #define LCD_CFG_TV_CKEY_U1(n) (((n) & 0xFF) << 16) 355 #define LCD_CFG_TV_CKEY_U1_MASK (0xFF << 16) 356 #define LCD_CFG_TV_CKEY_U1_SHIFT (16) 357 #define LCD_CFG_TV_CKEY_U2(n) (((n) & 0xFF) << 24) 358 #define LCD_CFG_TV_CKEY_U2_MASK (0xFF << 24) 359 #define LCD_CFG_TV_CKEY_U2_SHIFT (24) 360 361 // reg_78 362 #define LCD_CFG_TV_ALPHA_V(n) (((n) & 0xFF) << 0) 363 #define LCD_CFG_TV_ALPHA_V_MASK (0xFF << 0) 364 #define LCD_CFG_TV_ALPHA_V_SHIFT (0) 365 #define LCD_CFG_TV_CKEY_V(n) (((n) & 0xFF) << 8) 366 #define LCD_CFG_TV_CKEY_V_MASK (0xFF << 8) 367 #define LCD_CFG_TV_CKEY_V_SHIFT (8) 368 #define LCD_CFG_TV_CKEY_V1(n) (((n) & 0xFF) << 16) 369 #define LCD_CFG_TV_CKEY_V1_MASK (0xFF << 16) 370 #define LCD_CFG_TV_CKEY_V1_SHIFT (16) 371 #define LCD_CFG_TV_CKEY_V2(n) (((n) & 0xFF) << 24) 372 #define LCD_CFG_TV_CKEY_V2_MASK (0xFF << 24) 373 #define LCD_CFG_TV_CKEY_V2_SHIFT (24) 374 375 // reg_7c 376 #define LCD_CFG_TV_V_SPXLCNT(n) (((n) & 0xFFF) << 0) 377 #define LCD_CFG_TV_V_SPXLCNT_MASK (0xFFF << 0) 378 #define LCD_CFG_TV_V_SPXLCNT_SHIFT (0) 379 #define LCD_CFG_TV_V_EPXLCNT(n) (((n) & 0xFFF) << 16) 380 #define LCD_CFG_TV_V_EPXLCNT_MASK (0xFFF << 16) 381 #define LCD_CFG_TV_V_EPXLCNT_SHIFT (16) 382 383 // reg_80 384 #define LCD_CFG_TVG_ENA (1 << 0) 385 #define LCD_CFG_YUV2RGB_TVG (1 << 1) 386 #define LCD_CFG_TVG_SWAPYU (1 << 2) 387 #define LCD_CFG_TVG_SWAPUV (1 << 3) 388 #define LCD_CFG_TVG_SWAPRB (1 << 4) 389 #define LCD_CFG_TVG_TSTMODE (1 << 5) 390 #define LCD_CFG_TVG_HSMOOTH (1 << 6) 391 #define LCD_CFG_TVG_FTOGGLE (1 << 7) 392 #define LCD_CFG_TVGFORMAT(n) (((n) & 0xF) << 8) 393 #define LCD_CFG_TVGFORMAT_MASK (0xF << 8) 394 #define LCD_CFG_TVGFORMAT_SHIFT (8) 395 #define LCD_CFG_TVC_1BITENA (1 << 25) 396 #define LCD_CFG_TVC_1BITMOD (1 << 26) 397 #define LCD_CFG_TV_PALETTE_ENA (1 << 28) 398 #define LCD_CFG_TV_CBSH_ENA (1 << 29) 399 #define LCD_CFG_TV_GAMMA_ENA (1 << 30) 400 #define LCD_CFG_TV_NOBLENDING (1 << 31) 401 402 // reg_84 403 #define LCD_CFG_TV_NI (1 << 0) 404 #define LCD_CFG_TV_RESETB (1 << 1) 405 #define LCD_CFG_TV_TVGOTOPN (1 << 2) 406 #define LCD_CFG_TV_PNGOTOTV (1 << 3) 407 #define LCD_CFG_IO_TVGOTOPN (1 << 4) 408 #define LCD_CFG_IO_PNGOTOTV (1 << 5) 409 #define LCD_CFG_TMSYNC_ENA (1 << 6) 410 #define LCD_CFG_TV_ALPHA(n) (((n) & 0xFF) << 8) 411 #define LCD_CFG_TV_ALPHA_MASK (0xFF << 8) 412 #define LCD_CFG_TV_ALPHA_SHIFT (8) 413 #define LCD_CFG_TV_ALPHAMODE(n) (((n) & 0x3) << 16) 414 #define LCD_CFG_TV_ALPHAMODE_MASK (0x3 << 16) 415 #define LCD_CFG_TV_ALPHAMODE_SHIFT (16) 416 #define LCD_CFG_TV_CKEY_DMA (1 << 18) 417 #define LCD_CFG_TV_CKEY_GRA (1 << 19) 418 #define LCD_CFG_TV_CKEY_TVD (1 << 20) 419 #define LCD_CFG_TV_CKEY_TVG (1 << 21) 420 #define LCD_CFG_TV_CARRY (1 << 23) 421 #define LCD_CFG_TV_CKEY_MODE(n) (((n) & 0x7) << 24) 422 #define LCD_CFG_TV_CKEY_MODE_MASK (0x7 << 24) 423 #define LCD_CFG_TV_CKEY_MODE_SHIFT (24) 424 #define LCD_CFG_TVSYN_INV (1 << 27) 425 426 // reg_88 427 #define LCD_CFG_TV_CONTRAST(n) (((n) & 0xFFFF) << 0) 428 #define LCD_CFG_TV_CONTRAST_MASK (0xFFFF << 0) 429 #define LCD_CFG_TV_CONTRAST_SHIFT (0) 430 #define LCD_CFG_TV_BRIGHTNESS(n) (((n) & 0xFFFF) << 16) 431 #define LCD_CFG_TV_BRIGHTNESS_MASK (0xFFFF << 16) 432 #define LCD_CFG_TV_BRIGHTNESS_SHIFT (16) 433 434 // reg_8c 435 #define LCD_CFG_TV_SATURATION(n) (((n) & 0xFFFF) << 0) 436 #define LCD_CFG_TV_SATURATION_MASK (0xFFFF << 0) 437 #define LCD_CFG_TV_SATURATION_SHIFT (0) 438 #define LCD_CFG_TV_C_MULT_S(n) (((n) & 0xFFFF) << 16) 439 #define LCD_CFG_TV_C_MULT_S_MASK (0xFFFF << 16) 440 #define LCD_CFG_TV_C_MULT_S_SHIFT (16) 441 442 // reg_90 443 #define LCD_CFG_TV_COS0(n) (((n) & 0xFFFF) << 0) 444 #define LCD_CFG_TV_COS0_MASK (0xFFFF << 0) 445 #define LCD_CFG_TV_COS0_SHIFT (0) 446 #define LCD_CFG_TV_SIN0(n) (((n) & 0xFFFF) << 16) 447 #define LCD_CFG_TV_SIN0_MASK (0xFFFF << 16) 448 #define LCD_CFG_TV_SIN0_SHIFT (16) 449 450 // reg_94 451 #define LCD_CFG_TVIF_ENA (1 << 0) 452 #define LCD_CFG_TV_INV_TCLK (1 << 1) 453 #define LCD_CFG_TV_INV_HSYNC (1 << 2) 454 #define LCD_CFG_TV_INV_VSYNC (1 << 3) 455 #define LCD_CFG_TV_INV_HENA (1 << 4) 456 #define LCD_CFG_TV_INV_COMPSYNC (1 << 5) 457 #define LCD_CFG_TV_INV_COMPBLANK (1 << 6) 458 #define LCD_CFG_TV_REVERSERGB (1 << 7) 459 #define LCD_CFG_TV_BIASOUT (1 << 8) 460 #define LCD_CFG_INV_TCLK2X (1 << 9) 461 #define LCD_CFG_TV_INV_FIELD (1 << 10) 462 #define LCD_CFG_TVG_PMBURST (1 << 11) 463 #define LCD_CFG_AFF_WATERMARK(n) (((n) & 0xFF) << 16) 464 #define LCD_CFG_AFF_WATERMARK_MASK (0xFF << 16) 465 #define LCD_CFG_AFF_WATERMARK_SHIFT (16) 466 #define LCD_CFG_HDMIMODE(n) (((n) & 0xF) << 24) 467 #define LCD_CFG_HDMIMODE_MASK (0xF << 24) 468 #define LCD_CFG_HDMIMODE_SHIFT (24) 469 #define LCD_CFG_TVIFMODE(n) (((n) & 0xF) << 28) 470 #define LCD_CFG_TVIFMODE_MASK (0xF << 28) 471 #define LCD_CFG_TVIFMODE_SHIFT (28) 472 473 // reg_98 474 475 // reg_9c 476 #define LCD_CFG_TCLK_DIV(n) (((n) & 0xFFFFFFFF) << 0) 477 #define LCD_CFG_TCLK_DIV_MASK (0xFFFFFFFF << 0) 478 #define LCD_CFG_TCLK_DIV_SHIFT (0) 479 480 // reg_c0 481 #define LCD_CFG_DMA_SA_Y0(n) (((n) & 0xFFFFFFFF) << 0) 482 #define LCD_CFG_DMA_SA_Y0_MASK (0xFFFFFFFF << 0) 483 #define LCD_CFG_DMA_SA_Y0_SHIFT (0) 484 485 // reg_c4 486 #define LCD_CFG_DMA_SA_U0(n) (((n) & 0xFFFFFFFF) << 0) 487 #define LCD_CFG_DMA_SA_U0_MASK (0xFFFFFFFF << 0) 488 #define LCD_CFG_DMA_SA_U0_SHIFT (0) 489 490 // reg_c8 491 #define LCD_CFG_DMA_SA_V0(n) (((n) & 0xFFFFFFFF) << 0) 492 #define LCD_CFG_DMA_SA_V0_MASK (0xFFFFFFFF << 0) 493 #define LCD_CFG_DMA_SA_V0_SHIFT (0) 494 495 // reg_cc 496 #define LCD_CFG_DMA_SA_C0(n) (((n) & 0xFFFFFFFF) << 0) 497 #define LCD_CFG_DMA_SA_C0_MASK (0xFFFFFFFF << 0) 498 #define LCD_CFG_DMA_SA_C0_SHIFT (0) 499 500 // reg_d0 501 #define LCD_CFG_DMA_SA_Y1(n) (((n) & 0xFFFFFFFF) << 0) 502 #define LCD_CFG_DMA_SA_Y1_MASK (0xFFFFFFFF << 0) 503 #define LCD_CFG_DMA_SA_Y1_SHIFT (0) 504 505 // reg_d4 506 #define LCD_CFG_DMA_SA_U1(n) (((n) & 0xFFFFFFFF) << 0) 507 #define LCD_CFG_DMA_SA_U1_MASK (0xFFFFFFFF << 0) 508 #define LCD_CFG_DMA_SA_U1_SHIFT (0) 509 510 // reg_d8 511 #define LCD_CFG_DMA_SA_V1(n) (((n) & 0xFFFFFFFF) << 0) 512 #define LCD_CFG_DMA_SA_V1_MASK (0xFFFFFFFF << 0) 513 #define LCD_CFG_DMA_SA_V1_SHIFT (0) 514 515 // reg_dc 516 #define LCD_CFG_DMA_SA_C1(n) (((n) & 0xFFFFFFFF) << 0) 517 #define LCD_CFG_DMA_SA_C1_MASK (0xFFFFFFFF << 0) 518 #define LCD_CFG_DMA_SA_C1_SHIFT (0) 519 520 // reg_e0 521 #define LCD_CFG_DMA_PITCH_Y(n) (((n) & 0xFFFF) << 0) 522 #define LCD_CFG_DMA_PITCH_Y_MASK (0xFFFF << 0) 523 #define LCD_CFG_DMA_PITCH_Y_SHIFT (0) 524 #define LCD_CFG_DMA_PITCH_C(n) (((n) & 0xFFFF) << 16) 525 #define LCD_CFG_DMA_PITCH_C_MASK (0xFFFF << 16) 526 #define LCD_CFG_DMA_PITCH_C_SHIFT (16) 527 528 // reg_e4 529 #define LCD_CFG_DMA_PITCH_U(n) (((n) & 0xFFFF) << 0) 530 #define LCD_CFG_DMA_PITCH_U_MASK (0xFFFF << 0) 531 #define LCD_CFG_DMA_PITCH_U_SHIFT (0) 532 #define LCD_CFG_DMA_PITCH_V(n) (((n) & 0xFFFF) << 16) 533 #define LCD_CFG_DMA_PITCH_V_MASK (0xFFFF << 16) 534 #define LCD_CFG_DMA_PITCH_V_SHIFT (16) 535 536 // reg_e8 537 #define LCD_CFG_DMA_OVSA_HPXL(n) (((n) & 0xFFF) << 0) 538 #define LCD_CFG_DMA_OVSA_HPXL_MASK (0xFFF << 0) 539 #define LCD_CFG_DMA_OVSA_HPXL_SHIFT (0) 540 #define LCD_CFG_DMAFRM_Y (1 << 12) 541 #define LCD_CFG_DMAFRM_U (1 << 13) 542 #define LCD_CFG_DMAFRM_V (1 << 14) 543 #define LCD_CFG_DMAFRM_C (1 << 15) 544 #define LCD_CFG_DMA_OVSA_VLN(n) (((n) & 0xFFF) << 16) 545 #define LCD_CFG_DMA_OVSA_VLN_MASK (0xFFF << 16) 546 #define LCD_CFG_DMA_OVSA_VLN_SHIFT (16) 547 #define LCD_CFG_DMAFRM_FIX (1 << 31) 548 549 // reg_ec 550 #define LCD_CFG_DMA_H_PIXEL(n) (((n) & 0xFFF) << 0) 551 #define LCD_CFG_DMA_H_PIXEL_MASK (0xFFF << 0) 552 #define LCD_CFG_DMA_H_PIXEL_SHIFT (0) 553 #define LCD_CFG_DMA_V_LINE(n) (((n) & 0xFFF) << 16) 554 #define LCD_CFG_DMA_V_LINE_MASK (0xFFF << 16) 555 #define LCD_CFG_DMA_V_LINE_SHIFT (16) 556 557 // reg_f0 558 #define LCD_CFG_DMAZM_H_PIXEL(n) (((n) & 0xFFF) << 0) 559 #define LCD_CFG_DMAZM_H_PIXEL_MASK (0xFFF << 0) 560 #define LCD_CFG_DMAZM_H_PIXEL_SHIFT (0) 561 #define LCD_CFG_DMAZM_V_LINE(n) (((n) & 0xFFF) << 16) 562 #define LCD_CFG_DMAZM_V_LINE_MASK (0xFFF << 16) 563 #define LCD_CFG_DMAZM_V_LINE_SHIFT (16) 564 565 // reg_f4 566 #define LCD_CFG_GRA_SA0(n) (((n) & 0xFFFFFFFF) << 0) 567 #define LCD_CFG_GRA_SA0_MASK (0xFFFFFFFF << 0) 568 #define LCD_CFG_GRA_SA0_SHIFT (0) 569 570 // reg_f8 571 #define LCD_CFG_GRA_SA1(n) (((n) & 0xFFFFFFFF) << 0) 572 #define LCD_CFG_GRA_SA1_MASK (0xFFFFFFFF << 0) 573 #define LCD_CFG_GRA_SA1_SHIFT (0) 574 575 // reg_fc 576 #define LCD_CFG_GRA_PITCH(n) (((n) & 0xFFFF) << 0) 577 #define LCD_CFG_GRA_PITCH_MASK (0xFFFF << 0) 578 #define LCD_CFG_GRA_PITCH_SHIFT (0) 579 #define LCD_CFG_PN_BKLIGHTDIV(n) (((n) & 0xFFFF) << 16) 580 #define LCD_CFG_PN_BKLIGHTDIV_MASK (0xFFFF << 16) 581 #define LCD_CFG_PN_BKLIGHTDIV_SHIFT (16) 582 583 // reg_100 584 #define LCD_CFG_GRA_OVSA_HPXL(n) (((n) & 0xFFF) << 0) 585 #define LCD_CFG_GRA_OVSA_HPXL_MASK (0xFFF << 0) 586 #define LCD_CFG_GRA_OVSA_HPXL_SHIFT (0) 587 #define LCD_CFG_GRAFRM_Y (1 << 12) 588 #define LCD_CFG_GRA_OVSA_VLN(n) (((n) & 0xFFF) << 16) 589 #define LCD_CFG_GRA_OVSA_VLN_MASK (0xFFF << 16) 590 #define LCD_CFG_GRA_OVSA_VLN_SHIFT (16) 591 #define LCD_CFG_GRAFRM_FIX (1 << 31) 592 593 // reg_104 594 #define LCD_CFG_GRA_H_PIXEL(n) (((n) & 0xFFF) << 0) 595 #define LCD_CFG_GRA_H_PIXEL_MASK (0xFFF << 0) 596 #define LCD_CFG_GRA_H_PIXEL_SHIFT (0) 597 #define LCD_CFG_GRA_V_LINE(n) (((n) & 0xFFF) << 16) 598 #define LCD_CFG_GRA_V_LINE_MASK (0xFFF << 16) 599 #define LCD_CFG_GRA_V_LINE_SHIFT (16) 600 601 // reg_108 602 #define LCD_CFG_GRAZM_H_PIXEL(n) (((n) & 0xFFF) << 0) 603 #define LCD_CFG_GRAZM_H_PIXEL_MASK (0xFFF << 0) 604 #define LCD_CFG_GRAZM_H_PIXEL_SHIFT (0) 605 #define LCD_CFG_GRAZM_V_LINE(n) (((n) & 0xFFF) << 16) 606 #define LCD_CFG_GRAZM_V_LINE_MASK (0xFFF << 16) 607 #define LCD_CFG_GRAZM_V_LINE_SHIFT (16) 608 609 // reg_10c 610 #define LCD_CFG_HWC_OVSA_HPXL(n) (((n) & 0xFFF) << 0) 611 #define LCD_CFG_HWC_OVSA_HPXL_MASK (0xFFF << 0) 612 #define LCD_CFG_HWC_OVSA_HPXL_SHIFT (0) 613 #define LCD_CFG_HWC_OVSA_VLN(n) (((n) & 0xFFF) << 16) 614 #define LCD_CFG_HWC_OVSA_VLN_MASK (0xFFF << 16) 615 #define LCD_CFG_HWC_OVSA_VLN_SHIFT (16) 616 617 // reg_110 618 #define LCD_CFG_HWC_HPXL(n) (((n) & 0xFFF) << 0) 619 #define LCD_CFG_HWC_HPXL_MASK (0xFFF << 0) 620 #define LCD_CFG_HWC_HPXL_SHIFT (0) 621 #define LCD_CFG_HWC_VLN(n) (((n) & 0xFFF) << 16) 622 #define LCD_CFG_HWC_VLN_MASK (0xFFF << 16) 623 #define LCD_CFG_HWC_VLN_SHIFT (16) 624 625 // reg_114 626 #define LCD_CFG_PN_H_TOTAL(n) (((n) & 0xFFF) << 0) 627 #define LCD_CFG_PN_H_TOTAL_MASK (0xFFF << 0) 628 #define LCD_CFG_PN_H_TOTAL_SHIFT (0) 629 #define LCD_CFG_PN_V_TOTAL(n) (((n) & 0xFFF) << 16) 630 #define LCD_CFG_PN_V_TOTAL_MASK (0xFFF << 16) 631 #define LCD_CFG_PN_V_TOTAL_SHIFT (16) 632 633 // reg_118 634 #define LCD_CFG_PN_H_ACTIVE(n) (((n) & 0xFFF) << 0) 635 #define LCD_CFG_PN_H_ACTIVE_MASK (0xFFF << 0) 636 #define LCD_CFG_PN_H_ACTIVE_SHIFT (0) 637 #define LCD_CFG_PN_V_ACTIVE(n) (((n) & 0xFFF) << 16) 638 #define LCD_CFG_PN_V_ACTIVE_MASK (0xFFF << 16) 639 #define LCD_CFG_PN_V_ACTIVE_SHIFT (16) 640 641 // reg_11c 642 #define LCD_CFG_PN_H_FPORCH(n) (((n) & 0xFFF) << 0) 643 #define LCD_CFG_PN_H_FPORCH_MASK (0xFFF << 0) 644 #define LCD_CFG_PN_H_FPORCH_SHIFT (0) 645 #define LCD_CFG_PN_H_BPORCH(n) (((n) & 0xFFF) << 16) 646 #define LCD_CFG_PN_H_BPORCH_MASK (0xFFF << 16) 647 #define LCD_CFG_PN_H_BPORCH_SHIFT (16) 648 649 // reg_120 650 #define LCD_CFG_PN_V_FPORCH(n) (((n) & 0xFFF) << 0) 651 #define LCD_CFG_PN_V_FPORCH_MASK (0xFFF << 0) 652 #define LCD_CFG_PN_V_FPORCH_SHIFT (0) 653 #define LCD_CFG_PN_V_BPORCH(n) (((n) & 0xFFF) << 16) 654 #define LCD_CFG_PN_V_BPORCH_MASK (0xFFF << 16) 655 #define LCD_CFG_PN_V_BPORCH_SHIFT (16) 656 657 // reg_124 658 #define LCD_CFG_PN_BLANKCOLOR(n) (((n) & 0xFFFFFF) << 0) 659 #define LCD_CFG_PN_BLANKCOLOR_MASK (0xFFFFFF << 0) 660 #define LCD_CFG_PN_BLANKCOLOR_SHIFT (0) 661 662 // reg_128 663 #define LCD_CFG_HWC_COLOR1(n) (((n) & 0xFFFFFF) << 0) 664 #define LCD_CFG_HWC_COLOR1_MASK (0xFFFFFF << 0) 665 #define LCD_CFG_HWC_COLOR1_SHIFT (0) 666 667 // reg_12c 668 #define LCD_CFG_HWC_COLOR2(n) (((n) & 0xFFFFFF) << 0) 669 #define LCD_CFG_HWC_COLOR2_MASK (0xFFFFFF << 0) 670 #define LCD_CFG_HWC_COLOR2_SHIFT (0) 671 672 // reg_130 673 #define LCD_CFG_PN_ALPHA_Y(n) (((n) & 0xFF) << 0) 674 #define LCD_CFG_PN_ALPHA_Y_MASK (0xFF << 0) 675 #define LCD_CFG_PN_ALPHA_Y_SHIFT (0) 676 #define LCD_CFG_PN_CKEY_Y(n) (((n) & 0xFF) << 8) 677 #define LCD_CFG_PN_CKEY_Y_MASK (0xFF << 8) 678 #define LCD_CFG_PN_CKEY_Y_SHIFT (8) 679 #define LCD_CFG_PN_CKEY_Y1(n) (((n) & 0xFF) << 16) 680 #define LCD_CFG_PN_CKEY_Y1_MASK (0xFF << 16) 681 #define LCD_CFG_PN_CKEY_Y1_SHIFT (16) 682 #define LCD_CFG_PN_CKEY_Y2(n) (((n) & 0xFF) << 24) 683 #define LCD_CFG_PN_CKEY_Y2_MASK (0xFF << 24) 684 #define LCD_CFG_PN_CKEY_Y2_SHIFT (24) 685 686 // reg_134 687 #define LCD_CFG_PN_ALPHA_U(n) (((n) & 0xFF) << 0) 688 #define LCD_CFG_PN_ALPHA_U_MASK (0xFF << 0) 689 #define LCD_CFG_PN_ALPHA_U_SHIFT (0) 690 #define LCD_CFG_PN_CKEY_U(n) (((n) & 0xFF) << 8) 691 #define LCD_CFG_PN_CKEY_U_MASK (0xFF << 8) 692 #define LCD_CFG_PN_CKEY_U_SHIFT (8) 693 #define LCD_CFG_PN_CKEY_U1(n) (((n) & 0xFF) << 16) 694 #define LCD_CFG_PN_CKEY_U1_MASK (0xFF << 16) 695 #define LCD_CFG_PN_CKEY_U1_SHIFT (16) 696 #define LCD_CFG_PN_CKEY_U2(n) (((n) & 0xFF) << 24) 697 #define LCD_CFG_PN_CKEY_U2_MASK (0xFF << 24) 698 #define LCD_CFG_PN_CKEY_U2_SHIFT (24) 699 700 // reg_138 701 #define LCD_CFG_PN_ALPHA_V(n) (((n) & 0xFF) << 0) 702 #define LCD_CFG_PN_ALPHA_V_MASK (0xFF << 0) 703 #define LCD_CFG_PN_ALPHA_V_SHIFT (0) 704 #define LCD_CFG_PN_CKEY_V(n) (((n) & 0xFF) << 8) 705 #define LCD_CFG_PN_CKEY_V_MASK (0xFF << 8) 706 #define LCD_CFG_PN_CKEY_V_SHIFT (8) 707 #define LCD_CFG_PN_CKEY_V1(n) (((n) & 0xFF) << 16) 708 #define LCD_CFG_PN_CKEY_V1_MASK (0xFF << 16) 709 #define LCD_CFG_PN_CKEY_V1_SHIFT (16) 710 #define LCD_CFG_PN_CKEY_V2(n) (((n) & 0xFF) << 24) 711 #define LCD_CFG_PN_CKEY_V2_MASK (0xFF << 24) 712 #define LCD_CFG_PN_CKEY_V2_SHIFT (24) 713 714 // reg_13c 715 #define LCD_CFG_PN_V_SPXLCNT(n) (((n) & 0xFFF) << 0) 716 #define LCD_CFG_PN_V_SPXLCNT_MASK (0xFFF << 0) 717 #define LCD_CFG_PN_V_SPXLCNT_SHIFT (0) 718 #define LCD_CFG_PN_V_EPXLCNT(n) (((n) & 0xFFF) << 16) 719 #define LCD_CFG_PN_V_EPXLCNT_MASK (0xFFF << 16) 720 #define LCD_CFG_PN_V_EPXLCNT_SHIFT (16) 721 #define LCD_CFG_DBG_RD_INDEX(n) (((n) & 0xF) << 28) 722 #define LCD_CFG_DBG_RD_INDEX_MASK (0xF << 28) 723 #define LCD_CFG_DBG_RD_INDEX_SHIFT (28) 724 725 // reg_140 726 #define LCD_SPI_RXDATA(n) (((n) & 0xFFFFFFFF) << 0) 727 #define LCD_SPI_RXDATA_MASK (0xFFFFFFFF << 0) 728 #define LCD_SPI_RXDATA_SHIFT (0) 729 730 // reg_144 731 #define LCD_ISA_RXDATA(n) (((n) & 0xFFFFFFFF) << 0) 732 #define LCD_ISA_RXDATA_MASK (0xFFFFFFFF << 0) 733 #define LCD_ISA_RXDATA_SHIFT (0) 734 735 // reg_148 736 #define LCD_PN_IOPAD_I(n) (((n) & 0xFFFFFFF) << 0) 737 #define LCD_PN_IOPAD_I_MASK (0xFFFFFFF << 0) 738 #define LCD_PN_IOPAD_I_SHIFT (0) 739 740 // reg_14c 741 #define LCD_CFG_DMAVLD_HLEN_Y(n) (((n) & 0xFFFF) << 0) 742 #define LCD_CFG_DMAVLD_HLEN_Y_MASK (0xFFFF << 0) 743 #define LCD_CFG_DMAVLD_HLEN_Y_SHIFT (0) 744 #define LCD_TVD_SA_CFLAG (1 << 22) 745 #define LCD_DMA_SA_CFLAG (1 << 23) 746 #define LCD_TVG_SA_YFLAG (1 << 24) 747 #define LCD_TVD_SA_VFLAG (1 << 25) 748 #define LCD_TVD_SA_UFLAG (1 << 26) 749 #define LCD_TVD_SA_YFLAG (1 << 27) 750 #define LCD_GRA_SA_YFLAG (1 << 28) 751 #define LCD_DMA_SA_VFLAG (1 << 29) 752 #define LCD_DMA_SA_UFLAG (1 << 30) 753 #define LCD_DMA_SA_YFLAG (1 << 31) 754 755 // reg_150 756 #define LCD_CFG_DMAVLD_HLEN_U(n) (((n) & 0x3FF) << 0) 757 #define LCD_CFG_DMAVLD_HLEN_U_MASK (0x3FF << 0) 758 #define LCD_CFG_DMAVLD_HLEN_U_SHIFT (0) 759 #define LCD_CFG_DMAVLD_HLEN_V(n) (((n) & 0x3FF) << 10) 760 #define LCD_CFG_DMAVLD_HLEN_V_MASK (0x3FF << 10) 761 #define LCD_CFG_DMAVLD_HLEN_V_SHIFT (10) 762 763 // reg_154 764 #define LCD_CFG_GRAVLD_HLEN(n) (((n) & 0xFFFF) << 0) 765 #define LCD_CFG_GRAVLD_HLEN_MASK (0xFFFF << 0) 766 #define LCD_CFG_GRAVLD_HLEN_SHIFT (0) 767 #define LCD_CFG_TVGVLD_HLEN(n) (((n) & 0xFFFF) << 16) 768 #define LCD_CFG_TVGVLD_HLEN_MASK (0xFFFF << 16) 769 #define LCD_CFG_TVGVLD_HLEN_SHIFT (16) 770 771 // reg_158 772 #define LCD_CFG_HWC_RDDAT(n) (((n) & 0xFFFFFFFF) << 0) 773 #define LCD_CFG_HWC_RDDAT_MASK (0xFFFFFFFF << 0) 774 #define LCD_CFG_HWC_RDDAT_SHIFT (0) 775 776 // reg_15c 777 #define LCD_CFG_PN_GAMMA_RDDAT(n) (((n) & 0xFF) << 0) 778 #define LCD_CFG_PN_GAMMA_RDDAT_MASK (0xFF << 0) 779 #define LCD_CFG_PN_GAMMA_RDDAT_SHIFT (0) 780 781 // reg_160 782 #define LCD_CFG_PN_PALETTE_RDDAT(n) (((n) & 0xFFFFFF) << 0) 783 #define LCD_CFG_PN_PALETTE_RDDAT_MASK (0xFFFFFF << 0) 784 #define LCD_CFG_PN_PALETTE_RDDAT_SHIFT (0) 785 786 // reg_164 787 #define LCD_SLV_DATACNT(n) (((n) & 0xFF) << 4) 788 #define LCD_SLV_DATACNT_MASK (0xFF << 4) 789 #define LCD_SLV_DATACNT_SHIFT (4) 790 #define LCD_SLV_SPACECNT(n) (((n) & 0xFF) << 12) 791 #define LCD_SLV_SPACECNT_MASK (0xFF << 12) 792 #define LCD_SLV_SPACECNT_SHIFT (12) 793 794 // reg_168 795 #define LCD_CFG_TVDVLD_HLEN_Y(n) (((n) & 0xFFFF) << 0) 796 #define LCD_CFG_TVDVLD_HLEN_Y_MASK (0xFFFF << 0) 797 #define LCD_CFG_TVDVLD_HLEN_Y_SHIFT (0) 798 799 // reg_16c 800 #define LCD_CFG_DMAVLD_HLEN_U(n) (((n) & 0x3FF) << 0) 801 #define LCD_CFG_DMAVLD_HLEN_U_MASK (0x3FF << 0) 802 #define LCD_CFG_DMAVLD_HLEN_U_SHIFT (0) 803 #define LCD_CFG_DMAVLD_HLEN_V(n) (((n) & 0x3FF) << 10) 804 #define LCD_CFG_DMAVLD_HLEN_V_MASK (0x3FF << 10) 805 #define LCD_CFG_DMAVLD_HLEN_V_SHIFT (10) 806 807 // reg_170 808 #define LCD_CFG_TVC_RDDAT(n) (((n) & 0xFFFFFFFF) << 0) 809 #define LCD_CFG_TVC_RDDAT_MASK (0xFFFFFFFF << 0) 810 #define LCD_CFG_TVC_RDDAT_SHIFT (0) 811 812 // reg_174 813 #define LCD_CFG_TV_GAMMA_RDDAT(n) (((n) & 0xFF) << 0) 814 #define LCD_CFG_TV_GAMMA_RDDAT_MASK (0xFF << 0) 815 #define LCD_CFG_TV_GAMMA_RDDAT_SHIFT (0) 816 817 // reg_178 818 #define LCD_CFG_TV_PALETTE_RDDAT(n) (((n) & 0xFFFFFF) << 0) 819 #define LCD_CFG_TV_PALETTE_RDDAT_MASK (0xFFFFFF << 0) 820 #define LCD_CFG_TV_PALETTE_RDDAT_SHIFT (0) 821 822 // reg_17c 823 #define LCD_DMA_FRAME_CNT(n) (((n) & 0x3) << 0) 824 #define LCD_DMA_FRAME_CNT_MASK (0x3 << 0) 825 #define LCD_DMA_FRAME_CNT_SHIFT (0) 826 #define LCD_GRA_FRAME_CNT(n) (((n) & 0x3) << 2) 827 #define LCD_GRA_FRAME_CNT_MASK (0x3 << 2) 828 #define LCD_GRA_FRAME_CNT_SHIFT (2) 829 #define LCD_TVD_FRAME_CNT(n) (((n) & 0x3) << 4) 830 #define LCD_TVD_FRAME_CNT_MASK (0x3 << 4) 831 #define LCD_TVD_FRAME_CNT_SHIFT (4) 832 #define LCD_TVG_FRAME_CNT(n) (((n) & 0x3) << 6) 833 #define LCD_TVG_FRAME_CNT_MASK (0x3 << 6) 834 #define LCD_TVG_FRAME_CNT_SHIFT (6) 835 #define LCD_PN_CCIC_FRAME_CNT(n) (((n) & 0x3) << 8) 836 #define LCD_PN_CCIC_FRAME_CNT_MASK (0x3 << 8) 837 #define LCD_PN_CCIC_FRAME_CNT_SHIFT (8) 838 #define LCD_PN_IRE_FRAME_CNT(n) (((n) & 0x3) << 10) 839 #define LCD_PN_IRE_FRAME_CNT_MASK (0x3 << 10) 840 #define LCD_PN_IRE_FRAME_CNT_SHIFT (10) 841 #define LCD_TV_CCIC_FRAME_CNT(n) (((n) & 0x3) << 12) 842 #define LCD_TV_CCIC_FRAME_CNT_MASK (0x3 << 12) 843 #define LCD_TV_CCIC_FRAME_CNT_SHIFT (12) 844 #define LCD_TV_IRE_FRAME_CNT(n) (((n) & 0x3) << 14) 845 #define LCD_TV_IRE_FRAME_CNT_MASK (0x3 << 14) 846 #define LCD_TV_IRE_FRAME_CNT_SHIFT (14) 847 #define LCD_SP_FRAME_CNT(n) (((n) & 0x3) << 18) 848 #define LCD_SP_FRAME_CNT_MASK (0x3 << 18) 849 #define LCD_SP_FRAME_CNT_SHIFT (18) 850 #define LCD_PN_FRAME_CNT(n) (((n) & 0x3) << 20) 851 #define LCD_PN_FRAME_CNT_MASK (0x3 << 20) 852 #define LCD_PN_FRAME_CNT_SHIFT (20) 853 #define LCD_TV_FRAME_CNT(n) (((n) & 0x3) << 22) 854 #define LCD_TV_FRAME_CNT_MASK (0x3 << 22) 855 #define LCD_TV_FRAME_CNT_SHIFT (22) 856 857 // reg_180 858 #define LCD_CFG_SPI_START (1 << 0) 859 #define LCD_CFG_SPI_3W4WB (1 << 1) 860 #define LCD_CFG_SPI_SEL (1 << 2) 861 #define LCD_CFG_SPI_ENA (1 << 3) 862 #define LCD_CFG_TXBITSTO0 (1 << 4) 863 #define LCD_CFG_RXBITSTO0 (1 << 5) 864 #define LCD_CFG_SPI_KEEPXFER (1 << 6) 865 #define LCD_CFG_CLKINV (1 << 7) 866 #define LCD_CFG_TXBITS(n) (((n) & 0xFF) << 8) 867 #define LCD_CFG_TXBITS_MASK (0xFF << 8) 868 #define LCD_CFG_TXBITS_SHIFT (8) 869 #define LCD_CFG_RXBITS(n) (((n) & 0xFF) << 16) 870 #define LCD_CFG_RXBITS_MASK (0xFF << 16) 871 #define LCD_CFG_RXBITS_SHIFT (16) 872 #define LCD_CFG_SCLKCNT(n) (((n) & 0xFF) << 24) 873 #define LCD_CFG_SCLKCNT_MASK (0xFF << 24) 874 #define LCD_CFG_SCLKCNT_SHIFT (24) 875 876 // reg_184 877 #define LCD_CFG_SPI_TXDATA(n) (((n) & 0xFFFFFFFF) << 0) 878 #define LCD_CFG_SPI_TXDATA_MASK (0xFFFFFFFF << 0) 879 #define LCD_CFG_SPI_TXDATA_SHIFT (0) 880 881 // reg_188 882 #define LCD_CFG_SMPN_ENA (1 << 0) 883 #define LCD_CFG_KEEPXFER (1 << 1) 884 #define LCD_CFG_68S80SB (1 << 2) 885 #define LCD_SMPN_RSTB (1 << 3) 886 #define LCD_CFG_SLV_ENA (1 << 4) 887 #define LCD_SMPN_SEL (1 << 5) 888 #define LCD_CFG_SWAPBYTES (1 << 6) 889 #define LCD_CFG_CMD32OR16B (1 << 7) 890 #define LCD_CFG_SMPNMODE(n) (((n) & 0xF) << 8) 891 #define LCD_CFG_SMPNMODE_MASK (0xF << 8) 892 #define LCD_CFG_SMPNMODE_SHIFT (8) 893 #define LCD_CFG_SLV_ONLY (1 << 12) 894 #define LCD_CFG_IORDY_MSK (1 << 13) 895 #define LCD_CFG_SMPNVSYNC(n) (((n) & 0x3) << 14) 896 #define LCD_CFG_SMPNVSYNC_MASK (0x3 << 14) 897 #define LCD_CFG_SMPNVSYNC_SHIFT (14) 898 #define LCD_CFG_ISA_TXHIGH(n) (((n) & 0xF) << 16) 899 #define LCD_CFG_ISA_TXHIGH_MASK (0xF << 16) 900 #define LCD_CFG_ISA_TXHIGH_SHIFT (16) 901 #define LCD_CFG_ISA_TXLOW(n) (((n) & 0xF) << 20) 902 #define LCD_CFG_ISA_TXLOW_MASK (0xF << 20) 903 #define LCD_CFG_ISA_TXLOW_SHIFT (20) 904 #define LCD_CFG_ISA_RXHIGH(n) (((n) & 0xF) << 24) 905 #define LCD_CFG_ISA_RXHIGH_MASK (0xF << 24) 906 #define LCD_CFG_ISA_RXHIGH_SHIFT (24) 907 #define LCD_CFG_ISA_RXLOW(n) (((n) & 0xF) << 28) 908 #define LCD_CFG_ISA_RXLOW_MASK (0xF << 28) 909 #define LCD_CFG_ISA_RXLOW_SHIFT (28) 910 911 // reg_18c 912 #define LCD_SLVD_COMMAND0_DATA(n) (((n) & 0xFF) << 0) 913 #define LCD_SLVD_COMMAND0_DATA_MASK (0xFF << 0) 914 #define LCD_SLVD_COMMAND0_DATA_SHIFT (0) 915 #define LCD_SLV_COMMAND0_WRITE (1 << 8) 916 #define LCD_SLV_COMMAND0_READ (1 << 9) 917 #define LCD_32_CMD_FMT_DATA(n) (((n) & 0x1F) << 10) 918 #define LCD_32_CMD_FMT_DATA_MASK (0x1F << 10) 919 #define LCD_32_CMD_FMT_DATA_SHIFT (10) 920 #define LCD_SLV_COMMAND0_A0 (1 << 15) 921 #define LCD_SLV_COMMAND1_DATA(n) (((n) & 0xFF) << 16) 922 #define LCD_SLV_COMMAND1_DATA_MASK (0xFF << 16) 923 #define LCD_SLV_COMMAND1_DATA_SHIFT (16) 924 #define LCD_SLV_COMMAND1_WRITE (1 << 24) 925 #define LCD_SLV_COMMAND1_READ (1 << 25) 926 #define LCD_COMMAND_A_A0 (1 << 31) 927 928 // reg_190 929 #define LCD_CFG_DMA_ENA (1 << 0) 930 #define LCD_CFG_YUV2RGB_DMA (1 << 1) 931 #define LCD_CFG_DMA_SWAPYU (1 << 2) 932 #define LCD_CFG_DMA_SWAPUV (1 << 3) 933 #define LCD_CFG_DMA_SWAPRB (1 << 4) 934 #define LCD_CFG_DMA_TSTMODE (1 << 5) 935 #define LCD_CFG_DMA_HSMOOTH (1 << 6) 936 #define LCD_CFG_DMA_FTOGGLE (1 << 7) 937 #define LCD_CFG_DMAFORMAT(n) (((n) & 0xF) << 8) 938 #define LCD_CFG_DMAFORMAT_MASK (0xF << 8) 939 #define LCD_CFG_DMAFORMAT_SHIFT (8) 940 941 // reg_194 942 #define LCD_CFG_PXLMD(n) (((n) & 0xFF) << 0) 943 #define LCD_CFG_PXLMD_MASK (0xFF << 0) 944 #define LCD_CFG_PXLMD_SHIFT (0) 945 #define LCD_CFG_PN_ALPHA(n) (((n) & 0xFF) << 8) 946 #define LCD_CFG_PN_ALPHA_MASK (0xFF << 8) 947 #define LCD_CFG_PN_ALPHA_SHIFT (8) 948 #define LCD_CFG_PN_ALPHA_MODE(n) (((n) & 0x3) << 16) 949 #define LCD_CFG_PN_ALPHA_MODE_MASK (0x3 << 16) 950 #define LCD_CFG_PN_ALPHA_MODE_SHIFT (16) 951 #define LCD_CFG_DSCALE(n) (((n) & 0x3) << 18) 952 #define LCD_CFG_DSCALE_MASK (0x3 << 18) 953 #define LCD_CFG_DSCALE_SHIFT (18) 954 #define LCD_CFG_PWRDN_ENA (1 << 20) 955 #define LCD_CFG_GATED_ENA (1 << 21) 956 #define LCD_CFG_LNBUF_ENA (1 << 22) 957 #define LCD_CFG_PN_CARRY (1 << 23) 958 #define LCD_CFG_PN_KEY_MODE(n) (((n) & 0x7) << 24) 959 #define LCD_CFG_PN_KEY_MODE_MASK (0x7 << 24) 960 #define LCD_CFG_PN_KEY_MODE_SHIFT (24) 961 #define LCD_CFG_PN_VSYNC_INV (1 << 27) 962 #define LCD_CFG_PN_VSYNC_MODE(n) (((n) & 0x7) << 28) 963 #define LCD_CFG_PN_VSYNC_MODE_MASK (0x7 << 28) 964 #define LCD_CFG_PN_VSYNC_MODE_SHIFT (28) 965 #define LCD_CFG_FRAME_TRIG (1 << 31) 966 967 // reg_198 968 #define LCD_CFG_SRAM_ADDR(n) (((n) & 0xFF) << 0) 969 #define LCD_CFG_SRAM_ADDR_MASK (0xFF << 0) 970 #define LCD_CFG_SRAM_ADDR_SHIFT (0) 971 #define LCD_CFG_SRAM_ADDR_LCDID(n) (((n) & 0xF) << 8) 972 #define LCD_CFG_SRAM_ADDR_LCDID_MASK (0xF << 8) 973 #define LCD_CFG_SRAM_ADDR_LCDID_SHIFT (8) 974 #define LCD_SRAM_INIT_WR_RD(n) (((n) & 0x3) << 14) 975 #define LCD_SRAM_INIT_WR_RD_MASK (0x3 << 14) 976 #define LCD_SRAM_INIT_WR_RD_SHIFT (14) 977 978 // reg_19c 979 #define LCD_CFG_SRAM_WRDAT(n) (((n) & 0xFF) << 0) 980 #define LCD_CFG_SRAM_WRDAT_MASK (0xFF << 0) 981 #define LCD_CFG_SRAM_WRDAT_SHIFT (0) 982 983 // reg_1a0 984 #define LCD_CFG_RTC128X66(n) (((n) & 0x3) << 0) 985 #define LCD_CFG_RTC128X66_MASK (0x3 << 0) 986 #define LCD_CFG_RTC128X66_SHIFT (0) 987 #define LCD_CFG_WTC128X66(n) (((n) & 0x3) << 2) 988 #define LCD_CFG_WTC128X66_MASK (0x3 << 2) 989 #define LCD_CFG_WTC128X66_SHIFT (2) 990 #define LCD_CFG_RTC64X66(n) (((n) & 0x3) << 4) 991 #define LCD_CFG_RTC64X66_MASK (0x3 << 4) 992 #define LCD_CFG_RTC64X66_SHIFT (4) 993 #define LCD_CFG_WTC64X66(n) (((n) & 0x3) << 6) 994 #define LCD_CFG_WTC64X66_MASK (0x3 << 6) 995 #define LCD_CFG_WTC64X66_SHIFT (6) 996 #define LCD_CFG_RTC32X66(n) (((n) & 0x3) << 8) 997 #define LCD_CFG_RTC32X66_MASK (0x3 << 8) 998 #define LCD_CFG_RTC32X66_SHIFT (8) 999 #define LCD_CFG_WTC32X66(n) (((n) & 0x3) << 10) 1000 #define LCD_CFG_WTC32X66_MASK (0x3 << 10) 1001 #define LCD_CFG_WTC32X66_SHIFT (10) 1002 #define LCD_CFG_RTC32X32(n) (((n) & 0x3) << 12) 1003 #define LCD_CFG_RTC32X32_MASK (0x3 << 12) 1004 #define LCD_CFG_RTC32X32_SHIFT (12) 1005 #define LCD_CFG_WTC32X32(n) (((n) & 0x3) << 14) 1006 #define LCD_CFG_WTC32X32_MASK (0x3 << 14) 1007 #define LCD_CFG_WTC32X32_SHIFT (14) 1008 #define LCD_CFG_RTC256X8(n) (((n) & 0x3) << 20) 1009 #define LCD_CFG_RTC256X8_MASK (0x3 << 20) 1010 #define LCD_CFG_RTC256X8_SHIFT (20) 1011 #define LCD_CFG_WTC256X8(n) (((n) & 0x3) << 22) 1012 #define LCD_CFG_WTC256X8_MASK (0x3 << 22) 1013 #define LCD_CFG_WTC256X8_SHIFT (22) 1014 #define LCD_CFG_RTC256X24(n) (((n) & 0x3) << 24) 1015 #define LCD_CFG_RTC256X24_MASK (0x3 << 24) 1016 #define LCD_CFG_RTC256X24_SHIFT (24) 1017 #define LCD_CFG_WTC256X24(n) (((n) & 0x3) << 26) 1018 #define LCD_CFG_WTC256X24_MASK (0x3 << 26) 1019 #define LCD_CFG_WTC256X24_SHIFT (26) 1020 #define LCD_CFG_RTC256X32(n) (((n) & 0x3) << 28) 1021 #define LCD_CFG_RTC256X32_MASK (0x3 << 28) 1022 #define LCD_CFG_RTC256X32_SHIFT (28) 1023 #define LCD_CFG_WTC256X32(n) (((n) & 0x3) << 30) 1024 #define LCD_CFG_WTC256X32_MASK (0x3 << 30) 1025 #define LCD_CFG_WTC256X32_SHIFT (30) 1026 1027 // reg_1a4 1028 #define LCD_CFG_PDWN128X66 (1 << 0) 1029 #define LCD_CFG_PDWN64X66 (1 << 1) 1030 #define LCD_CFG_PDWN32X66 (1 << 2) 1031 #define LCD_CFG_PDWN32X32 (1 << 3) 1032 #define LCD_CFG_PDWN256X8 (1 << 5) 1033 #define LCD_CFG_PDWN256X24 (1 << 6) 1034 #define LCD_CFG_PDWN256X32 (1 << 7) 1035 #define LCD_CFG_CSB_256X8 (1 << 13) 1036 #define LCD_CFG_CSB_256X24 (1 << 14) 1037 #define LCD_CFG_CSB_256X32 (1 << 15) 1038 1039 // reg_1a8 1040 #define LCD_CLK_INT_DIV(n) (((n) & 0xFF) << 0) 1041 #define LCD_CLK_INT_DIV_MASK (0xFF << 0) 1042 #define LCD_CLK_INT_DIV_SHIFT (0) 1043 #define LCD_DSI1_BITCLK_DIV(n) (((n) & 0xF) << 8) 1044 #define LCD_DSI1_BITCLK_DIV_MASK (0xF << 8) 1045 #define LCD_DSI1_BITCLK_DIV_SHIFT (8) 1046 #define LCD_CLK_FRAC_DIV(n) (((n) & 0xFFF) << 16) 1047 #define LCD_CLK_FRAC_DIV_MASK (0xFFF << 16) 1048 #define LCD_CLK_FRAC_DIV_SHIFT (16) 1049 #define LCD_CFG_SCLK_DISABLE (1 << 28) 1050 #define LCD_SCLK_SOURCE_SELECT(n) (((n) & 0x3) << 30) 1051 #define LCD_SCLK_SOURCE_SELECT_MASK (0x3 << 30) 1052 #define LCD_SCLK_SOURCE_SELECT_SHIFT (30) 1053 1054 // reg_1ac 1055 #define LCD_CFG_PN_CONTRAST(n) (((n) & 0xFFFF) << 0) 1056 #define LCD_CFG_PN_CONTRAST_MASK (0xFFFF << 0) 1057 #define LCD_CFG_PN_CONTRAST_SHIFT (0) 1058 #define LCD_CFG_PN_BRIGHTNESS(n) (((n) & 0xFFFF) << 16) 1059 #define LCD_CFG_PN_BRIGHTNESS_MASK (0xFFFF << 16) 1060 #define LCD_CFG_PN_BRIGHTNESS_SHIFT (16) 1061 1062 // reg_1b0 1063 #define LCD_CFG_PN_SATURATION(n) (((n) & 0xFFFF) << 0) 1064 #define LCD_CFG_PN_SATURATION_MASK (0xFFFF << 0) 1065 #define LCD_CFG_PN_SATURATION_SHIFT (0) 1066 #define LCD_CFG_PN_C_MULT_S(n) (((n) & 0xFFFF) << 16) 1067 #define LCD_CFG_PN_C_MULT_S_MASK (0xFFFF << 16) 1068 #define LCD_CFG_PN_C_MULT_S_SHIFT (16) 1069 1070 // reg_1b4 1071 #define LCD_CFG_PN_COS0(n) (((n) & 0xFFFF) << 0) 1072 #define LCD_CFG_PN_COS0_MASK (0xFFFF << 0) 1073 #define LCD_CFG_PN_COS0_SHIFT (0) 1074 #define LCD_CFG_PN_SIN0(n) (((n) & 0xFFFF) << 16) 1075 #define LCD_CFG_PN_SIN0_MASK (0xFFFF << 16) 1076 #define LCD_CFG_PN_SIN0_SHIFT (16) 1077 1078 // reg_1b8 1079 #define LCD_CFG_DUMB_ENA (1 << 0) 1080 #define LCD_CFG_PN_INV_PCLK (1 << 1) 1081 #define LCD_CFG_PN_INV_HSYNC (1 << 2) 1082 #define LCD_CFG_PN_INV_VSYNC (1 << 3) 1083 #define LCD_CFG_PN_INV_HENA (1 << 4) 1084 #define LCD_CFG_PN_INV_COMPSYNC (1 << 5) 1085 #define LCD_CFG_PN_INV_COMPBLANK (1 << 6) 1086 #define LCD_CFG_PN_REVERSE_RGB (1 << 7) 1087 #define LCD_CFG_PN_BIASOUT (1 << 8) 1088 #define LCD_CFG_PN_NO_IOPAD (1 << 9) 1089 #define LCD_CFG_GRA_PMBURST (1 << 11) 1090 #define LCD_CFG_LCDGPIO_ENA(n) (((n) & 0xFF) << 12) 1091 #define LCD_CFG_LCDGPIO_ENA_MASK (0xFF << 12) 1092 #define LCD_CFG_LCDGPIO_ENA_SHIFT (12) 1093 #define LCD_CFG_LCDGPIO_O(n) (((n) & 0xFF) << 20) 1094 #define LCD_CFG_LCDGPIO_O_MASK (0xFF << 20) 1095 #define LCD_CFG_LCDGPIO_O_SHIFT (20) 1096 #define LCD_CFG_DUMBMODE(n) (((n) & 0xF) << 28) 1097 #define LCD_CFG_DUMBMODE_MASK (0xF << 28) 1098 #define LCD_CFG_DUMBMODE_SHIFT (28) 1099 1100 // reg_1bc 1101 #define LCD_CFG_IOPADMODE(n) (((n) & 0xF) << 0) 1102 #define LCD_CFG_IOPADMODE_MASK (0xF << 0) 1103 #define LCD_CFG_IOPADMODE_SHIFT (0) 1104 #define LCD_CFG_CYC_BURST_LENGTH (1 << 4) 1105 #define LCD_CFG_BOUNDARY (1 << 5) 1106 #define LCD_CFG_PN_CSC(n) (((n) & 0x3) << 8) 1107 #define LCD_CFG_PN_CSC_MASK (0x3 << 8) 1108 #define LCD_CFG_PN_CSC_SHIFT (8) 1109 #define LCD_CFG_TV_CSC(n) (((n) & 0x3) << 10) 1110 #define LCD_CFG_TV_CSC_MASK (0x3 << 10) 1111 #define LCD_CFG_TV_CSC_SHIFT (10) 1112 #define LCD_CFG_CMD_VM_ENA (1 << 12) 1113 #define LCD_CFG_DMA_VM_ENA (1 << 13) 1114 #define LCD_CFG_GRA_VM_ENA (1 << 15) 1115 #define LCD_CFG_TVD_VM_ENA (1 << 17) 1116 #define LCD_CFG_TVG_VM_ENA (1 << 19) 1117 #define LCD_CFG_SA_ENABLE (1 << 20) 1118 #define LCD_CFG_TVD_SA_CMSK (1 << 22) 1119 #define LCD_CFG_DMA_SA_CMSK (1 << 23) 1120 #define LCD_CFG_TVG_SA_YMSK (1 << 24) 1121 #define LCD_CFG_TVD_SA_VMSK (1 << 25) 1122 #define LCD_CFG_TVD_SA_UMSK (1 << 26) 1123 #define LCD_CFG_TVD_SA_YMSK (1 << 27) 1124 #define LCD_CFG_GRA_SA_YMSK (1 << 28) 1125 #define LCD_CFG_DMA_SA_VMSK (1 << 29) 1126 #define LCD_CFG_DMA_SA_UMSK (1 << 30) 1127 #define LCD_CFG_DMA_SA_YMSK (1 << 31) 1128 1129 // reg_1c0 1130 #define LCD_TVIF_FRAMEDONE_ENA (1 << 8) 1131 #define LCD_TVG_FF_UNDERFLOW_ENA (1 << 9) 1132 #define LCD_TVG_FRAME_IRQ1_ENA (1 << 10) 1133 #define LCD_TVG_FRAME_IRQ0_ENA (1 << 11) 1134 #define LCD_TVSYN_IRQ_ENA (1 << 12) 1135 #define LCD_TVD_FF_UNDERFLOW_ENA (1 << 13) 1136 #define LCD_TVD_FRAME_IRQ1_ENA (1 << 14) 1137 #define LCD_TVD_FRAME_IRQ0_ENA (1 << 15) 1138 #define LCD_ERR_IRQ_ENA (1 << 16) 1139 #define LCD_PWRND_IRQ_ENA (1 << 17) 1140 #define LCD_SPI_IRQ_ENA (1 << 18) 1141 #define LCD_SLV_IRQ_ENA (1 << 19) 1142 #define LCD_HWC_FRAMEDONE_ENA (1 << 20) 1143 #define LCD_TWC_FRAMEDONE_ENA (1 << 21) 1144 #define LCD_DUMB_FRAMEDONE_ENA (1 << 22) 1145 #define LCD_VSYNC_IRQ_ENA (1 << 23) 1146 #define LCD_TVC_FRAMEDONE_ENA (1 << 24) 1147 #define LCD_GRA_FF_UNDERFLOW_ENA (1 << 25) 1148 #define LCD_GRA_FRAME_IRQ1_ENA (1 << 26) 1149 #define LCD_GRA_FRAME_IRQ0_ENA (1 << 27) 1150 #define LCD_M2A_IRQ_ENA (1 << 28) 1151 #define LCD_DMA_FF_UNDERFLOW_ENA (1 << 29) 1152 #define LCD_DMA_FRAME_IRQ1_ENA (1 << 30) 1153 #define LCD_DMA_FRAME_IRQ0_ENA (1 << 31) 1154 1155 // reg_1c4 1156 #define LCD_TVG_FF_EMPTY (1 << 0) 1157 #define LCD_TVD_FF_EMPTY (1 << 1) 1158 #define LCD_GRA_FF_EMPTY (1 << 2) 1159 #define LCD_DMA_FF_EMPTY (1 << 3) 1160 #define LCD_TVG_FRAME_CNT_0 (1 << 4) 1161 #define LCD_TVD_FRAME_CNT_0 (1 << 5) 1162 #define LCD_GRA_FRAME_CNT_0 (1 << 6) 1163 #define LCD_DMA_FRAME_CNT_0 (1 << 7) 1164 #define LCD_TVIF_FRAMEDONE (1 << 8) 1165 #define LCD_TVG_FF_UNDERFLOW (1 << 9) 1166 #define LCD_TVG_FRAME_IRQ1 (1 << 10) 1167 #define LCD_TVG_FRAME_IRQ0 (1 << 11) 1168 #define LCD_TV_VSYNC_IRQ (1 << 12) 1169 #define LCD_TVD_FF_UNDERFLOW (1 << 13) 1170 #define LCD_TVD_GRAME_IRQ1 (1 << 14) 1171 #define LCD_TVD_GRAME_IRQ0 (1 << 15) 1172 #define LCD_ERR_IRQ (1 << 16) 1173 #define LCD_PWRDN_IRQ (1 << 17) 1174 #define LCD_SPI_IRQ (1 << 18) 1175 #define LCD_SLV_IRQ (1 << 19) 1176 #define LCD_HWC_FRAMEDONE (1 << 20) 1177 #define LCD_TXC_FRAMEDONE (1 << 21) 1178 #define LCD_DUMB_FRAMEDONE (1 << 22) 1179 #define LCD_PN_VSYNC_IRQ (1 << 23) 1180 #define LCD_TVC_FRAMEDONE (1 << 24) 1181 #define LCD_GRA_FF_UNDERFLOW (1 << 25) 1182 #define LCD_GRA_FRAME_IRQ1 (1 << 26) 1183 #define LCD_GRA_FRAME_IRQ0 (1 << 27) 1184 #define LCD_M2A_IRQ (1 << 28) 1185 #define LCD_DMA_FF_UNDERFLOW (1 << 29) 1186 #define LCD_DMA_FRAME_IRQ1 (1 << 30) 1187 #define LCD_DMA_FRAME_IRQ0 (1 << 31) 1188 1189 // reg_1c8 1190 #define LCD_RSR(n) (((n) & 0xFFFFFF) << 8) 1191 #define LCD_RSR_MASK (0xFFFFFF << 8) 1192 #define LCD_RSR_SHIFT (8) 1193 1194 // reg_1cc 1195 #define LCD_CFG_GRA_CUTHPXL1(n) (((n) & 0xFFF) << 0) 1196 #define LCD_CFG_GRA_CUTHPXL1_MASK (0xFFF << 0) 1197 #define LCD_CFG_GRA_CUTHPXL1_SHIFT (0) 1198 #define LCD_GRA_CUTCOLOR_3_0(n) (((n) & 0xF) << 12) 1199 #define LCD_GRA_CUTCOLOR_3_0_MASK (0xF << 12) 1200 #define LCD_GRA_CUTCOLOR_3_0_SHIFT (12) 1201 #define LCD_CFG_GRA_CUTHPXL2(n) (((n) & 0xFFF) << 16) 1202 #define LCD_CFG_GRA_CUTHPXL2_MASK (0xFFF << 16) 1203 #define LCD_CFG_GRA_CUTHPXL2_SHIFT (16) 1204 #define LCD_GRA_CUTCOLOR_7_4(n) (((n) & 0xF) << 28) 1205 #define LCD_GRA_CUTCOLOR_7_4_MASK (0xF << 28) 1206 #define LCD_GRA_CUTCOLOR_7_4_SHIFT (28) 1207 1208 // reg_1d0 1209 #define LCD_CFG_GRA_CUTVLN1(n) (((n) & 0xFFF) << 0) 1210 #define LCD_CFG_GRA_CUTVLN1_MASK (0xFFF << 0) 1211 #define LCD_CFG_GRA_CUTVLN1_SHIFT (0) 1212 #define LCD_GRA_CUTCOLOR_11_8(n) (((n) & 0xF) << 12) 1213 #define LCD_GRA_CUTCOLOR_11_8_MASK (0xF << 12) 1214 #define LCD_GRA_CUTCOLOR_11_8_SHIFT (12) 1215 #define LCD_CFG_GRA_CUTVLN2(n) (((n) & 0xFFF) << 16) 1216 #define LCD_CFG_GRA_CUTVLN2_MASK (0xFFF << 16) 1217 #define LCD_CFG_GRA_CUTVLN2_SHIFT (16) 1218 #define LCD_GRA_CUTCOLOR_15_12(n) (((n) & 0xF) << 28) 1219 #define LCD_GRA_CUTCOLOR_15_12_MASK (0xF << 28) 1220 #define LCD_GRA_CUTCOLOR_15_12_SHIFT (28) 1221 1222 // reg_1d4 1223 #define LCD_CFG_TVG_CUTHPXL1(n) (((n) & 0xFFF) << 0) 1224 #define LCD_CFG_TVG_CUTHPXL1_MASK (0xFFF << 0) 1225 #define LCD_CFG_TVG_CUTHPXL1_SHIFT (0) 1226 #define LCD_TVG_CUTCOLOR_3_0(n) (((n) & 0xF) << 12) 1227 #define LCD_TVG_CUTCOLOR_3_0_MASK (0xF << 12) 1228 #define LCD_TVG_CUTCOLOR_3_0_SHIFT (12) 1229 #define LCD_CFG_TVG_CUTHPXL2(n) (((n) & 0xFFF) << 16) 1230 #define LCD_CFG_TVG_CUTHPXL2_MASK (0xFFF << 16) 1231 #define LCD_CFG_TVG_CUTHPXL2_SHIFT (16) 1232 #define LCD_TVG_CUTCOLOR_7_4(n) (((n) & 0xF) << 28) 1233 #define LCD_TVG_CUTCOLOR_7_4_MASK (0xF << 28) 1234 #define LCD_TVG_CUTCOLOR_7_4_SHIFT (28) 1235 1236 // reg_1d8 1237 #define LCD_CFG_TVG_CUTVLN1(n) (((n) & 0xFFF) << 0) 1238 #define LCD_CFG_TVG_CUTVLN1_MASK (0xFFF << 0) 1239 #define LCD_CFG_TVG_CUTVLN1_SHIFT (0) 1240 #define LCD_TVG_CUTCOLOR_11_8(n) (((n) & 0xF) << 12) 1241 #define LCD_TVG_CUTCOLOR_11_8_MASK (0xF << 12) 1242 #define LCD_TVG_CUTCOLOR_11_8_SHIFT (12) 1243 #define LCD_CFG_TVG_CUTVLN2(n) (((n) & 0xFFF) << 16) 1244 #define LCD_CFG_TVG_CUTVLN2_MASK (0xFFF << 16) 1245 #define LCD_CFG_TVG_CUTVLN2_SHIFT (16) 1246 #define LCD_TVG_CUTCOLOR_15_12(n) (((n) & 0xF) << 28) 1247 #define LCD_TVG_CUTCOLOR_15_12_MASK (0xF << 28) 1248 #define LCD_TVG_CUTCOLOR_15_12_SHIFT (28) 1249 1250 // reg_1dc 1251 #define LCD_CFG_AHB_WRCNT(n) (((n) & 0x3) << 4) 1252 #define LCD_CFG_AHB_WRCNT_MASK (0x3 << 4) 1253 #define LCD_CFG_AHB_WRCNT_SHIFT (4) 1254 #define LCD_CFG_AHB_RDCNT(n) (((n) & 0x3) << 6) 1255 #define LCD_CFG_AHB_RDCNT_MASK (0x3 << 6) 1256 #define LCD_CFG_AHB_RDCNT_SHIFT (6) 1257 #define LCD_CFG_DMA_BURST0TO3(n) (((n) & 0x3) << 8) 1258 #define LCD_CFG_DMA_BURST0TO3_MASK (0x3 << 8) 1259 #define LCD_CFG_DMA_BURST0TO3_SHIFT (8) 1260 #define LCD_CFG_GRA_BURST0TO3(n) (((n) & 0x3) << 10) 1261 #define LCD_CFG_GRA_BURST0TO3_MASK (0x3 << 10) 1262 #define LCD_CFG_GRA_BURST0TO3_SHIFT (10) 1263 #define LCD_CFG_TVD_BURST0TO3(n) (((n) & 0x3) << 12) 1264 #define LCD_CFG_TVD_BURST0TO3_MASK (0x3 << 12) 1265 #define LCD_CFG_TVD_BURST0TO3_SHIFT (12) 1266 #define LCD_CFG_TVG_BURST0TO3(n) (((n) & 0x3) << 14) 1267 #define LCD_CFG_TVG_BURST0TO3_MASK (0x3 << 14) 1268 #define LCD_CFG_TVG_BURST0TO3_SHIFT (14) 1269 #define LCD_CFG_PN_SWAPATH_ENA (1 << 16) 1270 #define LCD_CFG_PN_SWAPATH (1 << 17) 1271 #define LCD_CFG_TV_SWAPATH_ENA (1 << 18) 1272 #define LCD_CFG_TV_SWAPATH (1 << 19) 1273 #define LCD_CFG_MERGE_SCLKTCLK (1 << 20) 1274 #define LCD_CFG_T2S_S2TB (1 << 21) 1275 #define LCD_CFG_ALL2PNORTV(n) (((n) & 0x3) << 22) 1276 #define LCD_CFG_ALL2PNORTV_MASK (0x3 << 22) 1277 #define LCD_CFG_ALL2PNORTV_SHIFT (22) 1278 #define LCD_CFG_MIPIMODE(n) (((n) & 0xF) << 24) 1279 #define LCD_CFG_MIPIMODE_MASK (0xF << 24) 1280 #define LCD_CFG_MIPIMODE_SHIFT (24) 1281 #define LCD_INVERT_IOPAD_DENA (1 << 28) 1282 #define LCD_INVERT_IOPAD_PCLK (1 << 29) 1283 #define LCD_INVERT_IOPAD_HSYNC (1 << 30) 1284 #define LCD_INVERT_IOPAD_VSYNC (1 << 31) 1285 1286 // reg_1e0 1287 #define LCD_CFG_SQULN1_ENA (1 << 0) 1288 #define LCD_CFG_SQULN1_SIZE(n) (((n) & 0x1F) << 1) 1289 #define LCD_CFG_SQULN1_SIZE_MASK (0x1F << 1) 1290 #define LCD_CFG_SQULN1_SIZE_SHIFT (1) 1291 #define LCD_CFG_SQULN1_SA(n) (((n) & 0x3FFFFFF) << 6) 1292 #define LCD_CFG_SQULN1_SA_MASK (0x3FFFFFF << 6) 1293 #define LCD_CFG_SQULN1_SA_SHIFT (6) 1294 1295 // reg_1e4 1296 #define LCD_CFG_SQULN2_ENA (1 << 0) 1297 #define LCD_CFG_SQULN2_SIZE(n) (((n) & 0x1F) << 1) 1298 #define LCD_CFG_SQULN2_SIZE_MASK (0x1F << 1) 1299 #define LCD_CFG_SQULN2_SIZE_SHIFT (1) 1300 #define LCD_CFG_SQULN2_SA(n) (((n) & 0x3FFFFFF) << 6) 1301 #define LCD_CFG_SQULN2_SA_MASK (0x3FFFFFF << 6) 1302 #define LCD_CFG_SQULN2_SA_SHIFT (6) 1303 1304 // reg_1e8 1305 #define LCD_CFG_OVTOP(n) (((n) & 0x3) << 0) 1306 #define LCD_CFG_OVTOP_MASK (0x3 << 0) 1307 #define LCD_CFG_OVTOP_SHIFT (0) 1308 #define LCD_CFG_OVNXT(n) (((n) & 0x3) << 2) 1309 #define LCD_CFG_OVNXT_MASK (0x3 << 2) 1310 #define LCD_CFG_OVNXT_SHIFT (2) 1311 #define LCD_CFG_OVTOP_TVC (1 << 4) 1312 #define LCD_CFG_DMATVD_AMOD(n) (((n) & 0x3) << 8) 1313 #define LCD_CFG_DMATVD_AMOD_MASK (0x3 << 8) 1314 #define LCD_CFG_DMATVD_AMOD_SHIFT (8) 1315 #define LCD_CFG_DMATVG_AMOD(n) (((n) & 0x3) << 10) 1316 #define LCD_CFG_DMATVG_AMOD_MASK (0x3 << 10) 1317 #define LCD_CFG_DMATVG_AMOD_SHIFT (10) 1318 #define LCD_CFG_GRATVD_AMOD(n) (((n) & 0x3) << 12) 1319 #define LCD_CFG_GRATVD_AMOD_MASK (0x3 << 12) 1320 #define LCD_CFG_GRATVD_AMOD_SHIFT (12) 1321 #define LCD_CFG_GRATVG_AMOD(n) (((n) & 0x3) << 14) 1322 #define LCD_CFG_GRATVG_AMOD_MASK (0x3 << 14) 1323 #define LCD_CFG_GRATVG_AMOD_SHIFT (14) 1324 #define LCD_CFG_VSMTH_DMATVD(n) (((n) & 0x3) << 16) 1325 #define LCD_CFG_VSMTH_DMATVD_MASK (0x3 << 16) 1326 #define LCD_CFG_VSMTH_DMATVD_SHIFT (16) 1327 #define LCD_CFG_VSMTH_GRATVG(n) (((n) & 0x3) << 18) 1328 #define LCD_CFG_VSMTH_GRATVG_MASK (0x3 << 18) 1329 #define LCD_CFG_VSMTH_GRATVG_SHIFT (18) 1330 #define LCD_CFG_DMA_2ZMDN (1 << 20) 1331 #define LCD_CFG_GRA_2ZMDN (1 << 21) 1332 #define LCD_CFG_TVD_2ZMDN (1 << 22) 1333 #define LCD_CFG_TVG_2ZMDN (1 << 23) 1334 1335 // reg_1ec 1336 #define LCD_DITHER_EN_PN (1 << 0) 1337 #define LCD_DITHER_4X8_PN (1 << 1) 1338 #define LCD_DITHER_MODE_PN(n) (((n) & 0x7) << 4) 1339 #define LCD_DITHER_MODE_PN_MASK (0x7 << 4) 1340 #define LCD_DITHER_MODE_PN_SHIFT (4) 1341 #define LCD_DITHER_EN_TV (1 << 8) 1342 #define LCD_DITHER_4X8_TV (1 << 9) 1343 #define LCD_DITHER_MODE_TV(n) (((n) & 0x7) << 12) 1344 #define LCD_DITHER_MODE_TV_MASK (0x7 << 12) 1345 #define LCD_DITHER_MODE_TV_SHIFT (12) 1346 #define LCD_DITHER_TABLE_INDEX_SEL(n) (((n) & 0x3) << 16) 1347 #define LCD_DITHER_TABLE_INDEX_SEL_MASK (0x3 << 16) 1348 #define LCD_DITHER_TABLE_INDEX_SEL_SHIFT (16) 1349 1350 // reg_1f0 1351 #define LCD_DITHER_TBL_DATA(n) (((n) & 0xFFFFFFFF) << 0) 1352 #define LCD_DITHER_TBL_DATA_MASK (0xFFFFFFFF << 0) 1353 #define LCD_DITHER_TBL_DATA_SHIFT (0) 1354 1355 // reg_1f4 1356 #define LCD_DSI1_SEL (1 << 0) 1357 #define LCD_DSI2_SEL (1 << 1) 1358 #define LCD_MASTER_ENH_PN (1 << 4) 1359 #define LCD_MASTER_ENH_TV (1 << 5) 1360 #define LCD_MASTER_ENV_PN (1 << 6) 1361 #define LCD_MASTER_ENV_TV (1 << 7) 1362 #define LCD_DSI_START_PN_SEL (1 << 8) 1363 #define LCD_DSI_START_TV_SEL (1 << 9) 1364 #define LCD_HSTART_PN_SEL (1 << 10) 1365 #define LCD_VSTART_PN_SEL (1 << 11) 1366 #define LCD_HSTART_TV_SEL (1 << 12) 1367 #define LCD_VSTART_TV_SEL (1 << 13) 1368 #define LCD_CFG_RTC_DSI(n) (((n) & 0x3) << 14) 1369 #define LCD_CFG_RTC_DSI_MASK (0x3 << 14) 1370 #define LCD_CFG_RTC_DSI_SHIFT (14) 1371 #define LCD_CFG_WTC_DSI(n) (((n) & 0x3) << 16) 1372 #define LCD_CFG_WTC_DSI_MASK (0x3 << 16) 1373 #define LCD_CFG_WTC_DSI_SHIFT (16) 1374 #define LCD_CFG_PDWN_DSI (1 << 18) 1375 1376 // reg_1f8 1377 #define LCD_SPI_HW_CTRL (1 << 0) 1378 #define LCD_SMPN_SWAP_RB (1 << 1) 1379 #define LCD_SPI_2LN_MODE (1 << 2) 1380 #define LCD_SPI_3LINE_MODE (1 << 3) 1381 #define LCD_SMPN2SPI_MODE(n) (((n) & 0x3) << 4) 1382 #define LCD_SMPN2SPI_MODE_MASK (0x3 << 4) 1383 #define LCD_SMPN2SPI_MODE_SHIFT (4) 1384 #define LCD_SPI_4LN_MODE (1 << 6) 1385 1386 // reg_200 1387 #define LCD_WDMA_ENA (1 << 0) 1388 #define LCD_CFG_WDMA_SEL_DSI (1 << 1) 1389 #define LCD_WDMA_PIX_FMT(n) (((n) & 0x3) << 4) 1390 #define LCD_WDMA_PIX_FMT_MASK (0x3 << 4) 1391 #define LCD_WDMA_PIX_FMT_SHIFT (4) 1392 #define LCD_WDMA_BURST_LEN(n) (((n) & 0x1F) << 8) 1393 #define LCD_WDMA_BURST_LEN_MASK (0x1F << 8) 1394 #define LCD_WDMA_BURST_LEN_SHIFT (8) 1395 #define LCD_WDMA_IMG_PITCH(n) (((n) & 0xFFFF) << 16) 1396 #define LCD_WDMA_IMG_PITCH_MASK (0xFFFF << 16) 1397 #define LCD_WDMA_IMG_PITCH_SHIFT (16) 1398 1399 // reg_204 1400 #define LCD_WDMA_IMG_WIDTH(n) (((n) & 0x1FFF) << 0) 1401 #define LCD_WDMA_IMG_WIDTH_MASK (0x1FFF << 0) 1402 #define LCD_WDMA_IMG_WIDTH_SHIFT (0) 1403 #define LCD_WDMA_IMG_HEIGHT(n) (((n) & 0xFFF) << 16) 1404 #define LCD_WDMA_IMG_HEIGHT_MASK (0xFFF << 16) 1405 #define LCD_WDMA_IMG_HEIGHT_SHIFT (16) 1406 1407 // reg_208 1408 #define LCD_WDMA_BASE_ADDR(n) (((n) & 0xFFFFFFFF) << 0) 1409 #define LCD_WDMA_BASE_ADDR_MASK (0xFFFFFFFF << 0) 1410 #define LCD_WDMA_BASE_ADDR_SHIFT (0) 1411 1412 // reg_20c 1413 #define LCD_DMAC_CTRL(n) (((n) & 0xFFFFF) << 0) 1414 #define LCD_DMAC_CTRL_MASK (0xFFFFF << 0) 1415 #define LCD_DMAC_CTRL_SHIFT (0) 1416 1417 // reg_210 1418 #define LCD_CFG_VSYNC_TRIG_DISABLE_S (1 << 0) 1419 #define LCD_CFG_VSYNC_TRIG_DISABLE_A (1 << 1) 1420 #define LCD_CFG_TE_BYPASS (1 << 2) 1421 #define LCD_CFG_TE_SEL (1 << 3) 1422 #define LCD_CFG_EDGE_SEL (1 << 4) 1423 #define LCD_CFG_TE_MODE (1 << 5) 1424 #define LCD_CFG_NFRAME_ACTIVE(n) (((n) & 0xFF) << 6) 1425 #define LCD_CFG_NFRAME_ACTIVE_MASK (0xFF << 6) 1426 #define LCD_CFG_NFRAME_ACTIVE_SHIFT (6) 1427 #define LCD_CFG_EXTRA_DELAY(n) (((n) & 0x3FF) << 14) 1428 #define LCD_CFG_EXTRA_DELAY_MASK (0x3FF << 14) 1429 #define LCD_CFG_EXTRA_DELAY_SHIFT (14) 1430 #define LCD_CFG_TE_CLR (1 << 24) 1431 #define LCD_CFG_TE_MASK (1 << 25) 1432 #define LCD_CFG_DSI_DR (1 << 26) 1433 #define LCD_CFG_BACKLIGHT_EN (1 << 27) 1434 #define LCD_CFG_BACKLIGHT_DUMB_MASK (1 << 28) 1435 #define LCD_CFG_REG_GEN_FRAME (1 << 29) 1436 #define LCD_CFG_DSI_RD_MEM (1 << 30) 1437 #define LCD_CFG_DSI_SOURCE_SEL (1 << 31) 1438 1439 // reg_214 1440 #define LCD_CFG_HSYNC_LENGTH(n) (((n) & 0xFFFF) << 0) 1441 #define LCD_CFG_HSYNC_LENGTH_MASK (0xFFFF << 0) 1442 #define LCD_CFG_HSYNC_LENGTH_SHIFT (0) 1443 #define LCD_CFG_DEL_NLINE(n) (((n) & 0x3FF) << 16) 1444 #define LCD_CFG_DEL_NLINE_MASK (0x3FF << 16) 1445 #define LCD_CFG_DEL_NLINE_SHIFT (16) 1446 #define LCD_CFG_HWC_ENA (1 << 26) 1447 #define LCD_CFG_HWC_1BITENA (1 << 27) 1448 #define LCD_CFG_HWC_1BITMOD (1 << 28) 1449 #define LCD_CFG_SPI_CMD_START (1 << 29) 1450 #define LCD_CFG_DSI_RD_MEM_CMD (1 << 30) 1451 #define LCD_CFG_TE_INV (1 << 31) 1452 1453 // reg_218 1454 #define LCD_CFG_STBY_LENGTH(n) (((n) & 0xFFF) << 0) 1455 #define LCD_CFG_STBY_LENGTH_MASK (0xFFF << 0) 1456 #define LCD_CFG_STBY_LENGTH_SHIFT (0) 1457 #define LCD_CFG_VSYNC_START_LINE(n) (((n) & 0xFF) << 12) 1458 #define LCD_CFG_VSYNC_START_LINE_MASK (0xFF << 12) 1459 #define LCD_CFG_VSYNC_START_LINE_SHIFT (12) 1460 #define LCD_CFG_VSYNC_END_LINE(n) (((n) & 0xFF) << 20) 1461 #define LCD_CFG_VSYNC_END_LINE_MASK (0xFF << 20) 1462 #define LCD_CFG_VSYNC_END_LINE_SHIFT (20) 1463 1464 // reg_21c 1465 #define LCD_CFG_H_FRONT_PORCH_SMPN(n) (((n) & 0xFFF) << 0) 1466 #define LCD_CFG_H_FRONT_PORCH_SMPN_MASK (0xFFF << 0) 1467 #define LCD_CFG_H_FRONT_PORCH_SMPN_SHIFT (0) 1468 #define LCD_CFG_H_BACK_PORCH_SMPN(n) (((n) & 0xFFF) << 12) 1469 #define LCD_CFG_H_BACK_PORCH_SMPN_MASK (0xFFF << 12) 1470 #define LCD_CFG_H_BACK_PORCH_SMPN_SHIFT (12) 1471 #define LCD_CFG_VSYNC_NLINE(n) (((n) & 0xFF) << 24) 1472 #define LCD_CFG_VSYNC_NLINE_MASK (0xFF << 24) 1473 #define LCD_CFG_VSYNC_NLINE_SHIFT (24) 1474 1475 // reg_220 1476 #define LCD_CFG_VSYNC_START_PIX(n) (((n) & 0xFFFF) << 0) 1477 #define LCD_CFG_VSYNC_START_PIX_MASK (0xFFFF << 0) 1478 #define LCD_CFG_VSYNC_START_PIX_SHIFT (0) 1479 #define LCD_CFG_VSYNC_END_PIX(n) (((n) & 0xFFFF) << 16) 1480 #define LCD_CFG_VSYNC_END_PIX_MASK (0xFFFF << 16) 1481 #define LCD_CFG_VSYNC_END_PIX_SHIFT (16) 1482 1483 // reg_224 1484 #define LCD_GEN_FRAME_START(n) (((n) & 0xFFFFFFFF) << 0) 1485 #define LCD_GEN_FRAME_START_MASK (0xFFFFFFFF << 0) 1486 #define LCD_GEN_FRAME_START_SHIFT (0) 1487 1488 // reg_228 1489 #define LCD_CFG_FRAME_HALT_EN (1 << 0) 1490 #define LCD_CFG_FRAME_HALT (1 << 1) 1491 #define LCD_CFG_TEST_PATTERN_EN (1 << 2) 1492 #define LCD_CFG_PATTERN_MODE(n) (((n) & 0x7F) << 3) 1493 #define LCD_CFG_PATTERN_MODE_MASK (0x7F << 3) 1494 #define LCD_CFG_PATTERN_MODE_SHIFT (3) 1495 #define LCD_CFG_PATTERN_PIX_NUM(n) (((n) & 0x7FF) << 10) 1496 #define LCD_CFG_PATTERN_PIX_NUM_MASK (0x7FF << 10) 1497 #define LCD_CFG_PATTERN_PIX_NUM_SHIFT (10) 1498 #define LCD_CFG_PATTERN_RGB_ORDER(n) (((n) & 0x7) << 21) 1499 #define LCD_CFG_PATTERN_RGB_ORDER_MASK (0x7 << 21) 1500 #define LCD_CFG_PATTERN_RGB_ORDER_SHIFT (21) 1501 #define LCD_CFG_PATTERN_IS_CIR (1 << 24) 1502 #define LCD_CFG_DSI_DATA_SWAP(n) (((n) & 0x7) << 25) 1503 #define LCD_CFG_DSI_DATA_SWAP_MASK (0x7 << 25) 1504 #define LCD_CFG_DSI_DATA_SWAP_SHIFT (25) 1505 #define LCD_CFG_DSI_RGB888 (1 << 28) 1506 #define LCD_CFG_DSI_RGB666 (1 << 29) 1507 #define LCD_CFG_DSI_RGB565 (1 << 30) 1508 #define LCD_CFG_DSI_RGB101010 (1 << 31) 1509 1510 // reg_22c 1511 #define LCD_CFG_TXDATA_HEAD_24B(n) (((n) & 0xFFFFFF) << 0) 1512 #define LCD_CFG_TXDATA_HEAD_24B_MASK (0xFFFFFF << 0) 1513 #define LCD_CFG_TXDATA_HEAD_24B_SHIFT (0) 1514 #define LCD_CFG_SPI_HEAD_TYPE(n) (((n) & 0x3) << 24) 1515 #define LCD_CFG_SPI_HEAD_TYPE_MASK (0x3 << 24) 1516 #define LCD_CFG_SPI_HEAD_TYPE_SHIFT (24) 1517 #define LCD_CFG_USE_FRAME_HEAD (1 << 26) 1518 #define LCD_CFG_TXBIT_MINUS1 (1 << 27) 1519 #define LCD_CFG_SPI_4LN_888 (1 << 28) 1520 #define LCD_CFG_SPI_4LN_666 (1 << 29) 1521 #define LCD_CFG_SPI_1LN_RGB666_ORDER (1 << 30) 1522 #define LCD_CFG_SPI_4LN_565 (1 << 31) 1523 1524 // reg_230 1525 #define LCD_CFG_USE_MMU (1 << 0) 1526 #define LCD_CFG_MMU_ENA (1 << 1) 1527 #define LCD_CFG_MMU_BYPASS (1 << 2) 1528 #define LCD_CFG_SPI_DCX_DR (1 << 3) 1529 #define LCD_CFG_SPI_DCX (1 << 4) 1530 #define LCD_CFG_SPI_DCX_OENB (1 << 5) 1531 #define LCD_CFG_SPI_XCS_DR (1 << 6) 1532 #define LCD_CFG_SPI_XCS (1 << 7) 1533 #define LCD_CFG_SPI_HEAD_NUM(n) (((n) & 0x3F) << 8) 1534 #define LCD_CFG_SPI_HEAD_NUM_MASK (0x3F << 8) 1535 #define LCD_CFG_SPI_HEAD_NUM_SHIFT (8) 1536 1537 // reg_234 1538 #define LCD_CFG_DMA_WDATA_H(n) (((n) & 0xFFFFFFFF) << 0) 1539 #define LCD_CFG_DMA_WDATA_H_MASK (0xFFFFFFFF << 0) 1540 #define LCD_CFG_DMA_WDATA_H_SHIFT (0) 1541 1542 // reg_238 1543 #define LCD_CFG_DMA_WDATA_L(n) (((n) & 0xFFFFFFFF) << 0) 1544 #define LCD_CFG_DMA_WDATA_L_MASK (0xFFFFFFFF << 0) 1545 #define LCD_CFG_DMA_WDATA_L_SHIFT (0) 1546 1547 // reg_23c 1548 #define LCD_CFG_GRA_WDATA_H(n) (((n) & 0xFFFFFFFF) << 0) 1549 #define LCD_CFG_GRA_WDATA_H_MASK (0xFFFFFFFF << 0) 1550 #define LCD_CFG_GRA_WDATA_H_SHIFT (0) 1551 1552 // reg_240 1553 #define LCD_CFG_GRA_WDATA_L(n) (((n) & 0xFFFFFFFF) << 0) 1554 #define LCD_CFG_GRA_WDATA_L_MASK (0xFFFFFFFF << 0) 1555 #define LCD_CFG_GRA_WDATA_L_SHIFT (0) 1556 1557 // reg_244 1558 #define LCD_CFG_GRA2_WDATA_H(n) (((n) & 0xFFFFFFFF) << 0) 1559 #define LCD_CFG_GRA2_WDATA_H_MASK (0xFFFFFFFF << 0) 1560 #define LCD_CFG_GRA2_WDATA_H_SHIFT (0) 1561 1562 // reg_248 1563 #define LCD_CFG_GRA2_WDATA_L(n) (((n) & 0xFFFFFFFF) << 0) 1564 #define LCD_CFG_GRA2_WDATA_L_MASK (0xFFFFFFFF << 0) 1565 #define LCD_CFG_GRA2_WDATA_L_SHIFT (0) 1566 1567 // reg_24c 1568 #define LCD_CFG_DMA_MAP_ADDR(n) (((n) & 0x1FF) << 0) 1569 #define LCD_CFG_DMA_MAP_ADDR_MASK (0x1FF << 0) 1570 #define LCD_CFG_DMA_MAP_ADDR_SHIFT (0) 1571 #define LCD_CFG_GRA_MAP_ADDR(n) (((n) & 0x1FF) << 9) 1572 #define LCD_CFG_GRA_MAP_ADDR_MASK (0x1FF << 9) 1573 #define LCD_CFG_GRA_MAP_ADDR_SHIFT (9) 1574 #define LCD_CFG_GRA2_MAP_ADDR(n) (((n) & 0x1FF) << 18) 1575 #define LCD_CFG_GRA2_MAP_ADDR_MASK (0x1FF << 18) 1576 #define LCD_CFG_GRA2_MAP_ADDR_SHIFT (18) 1577 1578 // reg_250 1579 #define LCD_CFG_MMU_UNVALID_DATA(n) (((n) & 0xFFFFFFFF) << 0) 1580 #define LCD_CFG_MMU_UNVALID_DATA_MASK (0xFFFFFFFF << 0) 1581 #define LCD_CFG_MMU_UNVALID_DATA_SHIFT (0) 1582 1583 // reg_254 1584 #define LCD_CFG_TE_DB_TARGET(n) (((n) & 0xFF) << 0) 1585 #define LCD_CFG_TE_DB_TARGET_MASK (0xFF << 0) 1586 #define LCD_CFG_TE_DB_TARGET_SHIFT (0) 1587 #define LCD_CFG_TE_DB_BYPASS (1 << 8) 1588 #define LCD_CFG_TE_USE_SW (1 << 9) 1589 1590 // reg_258 1591 #define LCD_CFG_FRAME_VALID(n) (((n) & 0xFFFFFFFF) << 0) 1592 #define LCD_CFG_FRAME_VALID_MASK (0xFFFFFFFF << 0) 1593 #define LCD_CFG_FRAME_VALID_SHIFT (0) 1594 1595 // reg_260 1596 #define LCD_CFG_TVD_ENA (1 << 0) 1597 #define LCD_CFG_YUV2RGB_TVD (1 << 1) 1598 #define LCD_CFG_TVD_SWAPYU (1 << 2) 1599 #define LCD_CFG_TVD_SWAPUV (1 << 3) 1600 #define LCD_CFG_TVD_SWAPRB (1 << 4) 1601 #define LCD_CFG_TVD_TSTMODE (1 << 5) 1602 #define LCD_CFG_TVD_HSMOOTH (1 << 6) 1603 #define LCD_CFG_TVD_FTOGGLE (1 << 7) 1604 #define LCD_CFG_TVDFORMAT(n) (((n) & 0xF) << 8) 1605 #define LCD_CFG_TVDFORMAT_MASK (0xF << 8) 1606 #define LCD_CFG_TVDFORMAT_SHIFT (8) 1607 #define LCD_FORCE_BLANKCOLOR (1 << 24) 1608 #define LCD_DLY_CS_ENA (1 << 25) 1609 #define LCD_CFG_ARBFAST_ENA (1 << 27) 1610 #define LCD_CFG_PN_PALETTE_ENA (1 << 28) 1611 #define LCD_CFG_PN_CBSH_ENA (1 << 29) 1612 #define LCD_CFG_PN_GAMMA_ENA (1 << 30) 1613 #define LCD_CFG_PN_NOBLENDING (1 << 31) 1614 1615 // reg_264 1616 #define LCD_CFG_GRA_ENA (1 << 0) 1617 #define LCD_CFG_YUV2RGB_GRA (1 << 1) 1618 #define LCD_CFG_GRA_SWAPYU (1 << 2) 1619 #define LCD_CFG_GRA_SWAPUV (1 << 3) 1620 #define LCD_CFG_GRA_SWAPRB (1 << 4) 1621 #define LCD_CFG_GRA_TSTMODE (1 << 5) 1622 #define LCD_CFG_GRA_HSMOOTH (1 << 6) 1623 #define LCD_CFG_GRA_FTOGGLE (1 << 7) 1624 #define LCD_CFG_GRAFORMAT(n) (((n) & 0xF) << 8) 1625 #define LCD_CFG_GRAFORMAT_MASK (0xF << 8) 1626 #define LCD_CFG_GRAFORMAT_SHIFT (8) 1627 1628 #endif 1629 1630