1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #include "soc/interrupts.h" 16 17 const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = { 18 [0] = "WIFI_MAC", 19 [1] = "WIFI_NMI", 20 [2] = "WIFI_BB", 21 [3] = "BT_MAC", 22 [4] = "BT_BB", 23 [5] = "BT_BB_NMI", 24 [6] = "RWBT", 25 [7] = "RWBLE", 26 [8] = "RWBT_NMI", 27 [9] = "RWBLE_NMI", 28 [10] = "SLC0", 29 [11] = "SLC1", 30 [12] = "UHCI0", 31 [13] = "UHCI1", 32 [14] = "TG0_T0_LEVEL", 33 [15] = "TG0_T1_LEVEL", 34 [16] = "TG0_WDT_LEVEL", 35 [17] = "TG0_LACT_LEVEL", 36 [18] = "TG1_T0_LEVEL", 37 [19] = "TG1_T1_LEVEL", 38 [20] = "TG1_WDT_LEVEL", 39 [21] = "TG1_LACT_LEVEL", 40 [22] = "GPIO", 41 [23] = "GPIO_NMI", 42 [24] = "FROM_CPU0", 43 [25] = "FROM_CPU1", 44 [26] = "FROM_CPU2", 45 [27] = "FROM_CPU3", 46 [28] = "SPI0", 47 [29] = "SPI1", 48 [30] = "SPI2", 49 [31] = "SPI3", 50 [32] = "I2S0", 51 [33] = "I2S1", 52 [34] = "UART0", 53 [35] = "UART1", 54 [36] = "UART2", 55 [37] = "SDIO_HOST", 56 [38] = "ETH_MAC", 57 [39] = "PWM0", 58 [40] = "PWM1", 59 [41] = "PWM2", 60 [42] = "PWM3", 61 [43] = "LEDC", 62 [44] = "EFUSE", 63 [45] = "CAN", 64 [46] = "RTC_CORE", 65 [47] = "RMT", 66 [48] = "PCNT", 67 [49] = "I2C_EXT0", 68 [50] = "I2C_EXT1", 69 [51] = "RSA", 70 [52] = "SPI1_DMA", 71 [53] = "SPI2_DMA", 72 [54] = "SPI3_DMA", 73 [55] = "WDT", 74 [56] = "TIMER1", 75 [57] = "TIMER2", 76 [58] = "TG0_T0_EDGE", 77 [59] = "TG0_T1_EDGE", 78 [60] = "TG0_WDT_EDGE", 79 [61] = "TG0_LACT_EDGE", 80 [62] = "TG1_T0_EDGE", 81 [63] = "TG1_T1_EDGE", 82 [64] = "TG1_WDT_EDGE", 83 [65] = "TG1_LACT_EDGE", 84 [66] = "MMU_IA", 85 [67] = "MPU_IA", 86 [68] = "CACHE_IA", 87 }; 88