1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_I2S_STRUCT_H_ 15 #define _SOC_I2S_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct i2s_dev_s { 24 uint32_t reserved_0; 25 uint32_t reserved_4; 26 union { 27 struct { 28 uint32_t tx_reset: 1; 29 uint32_t rx_reset: 1; 30 uint32_t tx_fifo_reset: 1; 31 uint32_t rx_fifo_reset: 1; 32 uint32_t tx_start: 1; 33 uint32_t rx_start: 1; 34 uint32_t tx_slave_mod: 1; 35 uint32_t rx_slave_mod: 1; 36 uint32_t tx_right_first: 1; 37 uint32_t rx_right_first: 1; 38 uint32_t tx_msb_shift: 1; 39 uint32_t rx_msb_shift: 1; 40 uint32_t tx_short_sync: 1; 41 uint32_t rx_short_sync: 1; 42 uint32_t tx_mono: 1; 43 uint32_t rx_mono: 1; 44 uint32_t tx_msb_right: 1; 45 uint32_t rx_msb_right: 1; 46 uint32_t sig_loopback: 1; 47 uint32_t reserved19: 13; 48 }; 49 uint32_t val; 50 } conf; 51 union { 52 struct { 53 uint32_t rx_take_data: 1; 54 uint32_t tx_put_data: 1; 55 uint32_t rx_wfull: 1; 56 uint32_t rx_rempty: 1; 57 uint32_t tx_wfull: 1; 58 uint32_t tx_rempty: 1; 59 uint32_t rx_hung: 1; 60 uint32_t tx_hung: 1; 61 uint32_t in_done: 1; 62 uint32_t in_suc_eof: 1; 63 uint32_t in_err_eof: 1; 64 uint32_t out_done: 1; 65 uint32_t out_eof: 1; 66 uint32_t in_dscr_err: 1; 67 uint32_t out_dscr_err: 1; 68 uint32_t in_dscr_empty: 1; 69 uint32_t out_total_eof: 1; 70 uint32_t reserved17: 15; 71 }; 72 uint32_t val; 73 } int_raw; 74 union { 75 struct { 76 uint32_t rx_take_data: 1; 77 uint32_t tx_put_data: 1; 78 uint32_t rx_wfull: 1; 79 uint32_t rx_rempty: 1; 80 uint32_t tx_wfull: 1; 81 uint32_t tx_rempty: 1; 82 uint32_t rx_hung: 1; 83 uint32_t tx_hung: 1; 84 uint32_t in_done: 1; 85 uint32_t in_suc_eof: 1; 86 uint32_t in_err_eof: 1; 87 uint32_t out_done: 1; 88 uint32_t out_eof: 1; 89 uint32_t in_dscr_err: 1; 90 uint32_t out_dscr_err: 1; 91 uint32_t in_dscr_empty: 1; 92 uint32_t out_total_eof: 1; 93 uint32_t reserved17: 15; 94 }; 95 uint32_t val; 96 } int_st; 97 union { 98 struct { 99 uint32_t rx_take_data: 1; 100 uint32_t tx_put_data: 1; 101 uint32_t rx_wfull: 1; 102 uint32_t rx_rempty: 1; 103 uint32_t tx_wfull: 1; 104 uint32_t tx_rempty: 1; 105 uint32_t rx_hung: 1; 106 uint32_t tx_hung: 1; 107 uint32_t in_done: 1; 108 uint32_t in_suc_eof: 1; 109 uint32_t in_err_eof: 1; 110 uint32_t out_done: 1; 111 uint32_t out_eof: 1; 112 uint32_t in_dscr_err: 1; 113 uint32_t out_dscr_err: 1; 114 uint32_t in_dscr_empty: 1; 115 uint32_t out_total_eof: 1; 116 uint32_t reserved17: 15; 117 }; 118 uint32_t val; 119 } int_ena; 120 union { 121 struct { 122 uint32_t take_data: 1; 123 uint32_t put_data: 1; 124 uint32_t rx_wfull: 1; 125 uint32_t rx_rempty: 1; 126 uint32_t tx_wfull: 1; 127 uint32_t tx_rempty: 1; 128 uint32_t rx_hung: 1; 129 uint32_t tx_hung: 1; 130 uint32_t in_done: 1; 131 uint32_t in_suc_eof: 1; 132 uint32_t in_err_eof: 1; 133 uint32_t out_done: 1; 134 uint32_t out_eof: 1; 135 uint32_t in_dscr_err: 1; 136 uint32_t out_dscr_err: 1; 137 uint32_t in_dscr_empty: 1; 138 uint32_t out_total_eof: 1; 139 uint32_t reserved17: 15; 140 }; 141 uint32_t val; 142 } int_clr; 143 union { 144 struct { 145 uint32_t tx_bck_in_delay: 2; 146 uint32_t tx_ws_in_delay: 2; 147 uint32_t rx_bck_in_delay: 2; 148 uint32_t rx_ws_in_delay: 2; 149 uint32_t rx_sd_in_delay: 2; 150 uint32_t tx_bck_out_delay: 2; 151 uint32_t tx_ws_out_delay: 2; 152 uint32_t tx_sd_out_delay: 2; 153 uint32_t rx_ws_out_delay: 2; 154 uint32_t rx_bck_out_delay: 2; 155 uint32_t tx_dsync_sw: 1; 156 uint32_t rx_dsync_sw: 1; 157 uint32_t data_enable_delay: 2; 158 uint32_t tx_bck_in_inv: 1; 159 uint32_t reserved25: 7; 160 }; 161 uint32_t val; 162 } timing; 163 union { 164 struct { 165 uint32_t rx_data_num: 6; 166 uint32_t tx_data_num: 6; 167 uint32_t dscr_en: 1; 168 uint32_t tx_fifo_mod: 3; 169 uint32_t rx_fifo_mod: 3; 170 uint32_t tx_fifo_mod_force_en: 1; 171 uint32_t rx_fifo_mod_force_en: 1; 172 uint32_t reserved21: 11; 173 }; 174 uint32_t val; 175 } fifo_conf; 176 uint32_t rx_eof_num; 177 uint32_t conf_single_data; 178 union { 179 struct { 180 uint32_t tx_chan_mod: 3; 181 uint32_t rx_chan_mod: 2; 182 uint32_t reserved5: 27; 183 }; 184 uint32_t val; 185 } conf_chan; 186 union { 187 struct { 188 uint32_t addr: 20; 189 uint32_t reserved20: 8; 190 uint32_t stop: 1; 191 uint32_t start: 1; 192 uint32_t restart: 1; 193 uint32_t park: 1; 194 }; 195 uint32_t val; 196 } out_link; 197 union { 198 struct { 199 uint32_t addr: 20; 200 uint32_t reserved20: 8; 201 uint32_t stop: 1; 202 uint32_t start: 1; 203 uint32_t restart: 1; 204 uint32_t park: 1; 205 }; 206 uint32_t val; 207 } in_link; 208 uint32_t out_eof_des_addr; 209 uint32_t in_eof_des_addr; 210 uint32_t out_eof_bfr_des_addr; 211 union { 212 struct { 213 uint32_t mode: 3; 214 uint32_t reserved3: 1; 215 uint32_t addr: 2; 216 uint32_t reserved6: 26; 217 }; 218 uint32_t val; 219 } ahb_test; 220 uint32_t in_link_dscr; 221 uint32_t in_link_dscr_bf0; 222 uint32_t in_link_dscr_bf1; 223 uint32_t out_link_dscr; 224 uint32_t out_link_dscr_bf0; 225 uint32_t out_link_dscr_bf1; 226 union { 227 struct { 228 uint32_t in_rst: 1; 229 uint32_t out_rst: 1; 230 uint32_t ahbm_fifo_rst: 1; 231 uint32_t ahbm_rst: 1; 232 uint32_t out_loop_test: 1; 233 uint32_t in_loop_test: 1; 234 uint32_t out_auto_wrback: 1; 235 uint32_t out_no_restart_clr: 1; 236 uint32_t out_eof_mode: 1; 237 uint32_t outdscr_burst_en: 1; 238 uint32_t indscr_burst_en: 1; 239 uint32_t out_data_burst_en: 1; 240 uint32_t check_owner: 1; 241 uint32_t mem_trans_en: 1; 242 uint32_t reserved14: 18; 243 }; 244 uint32_t val; 245 } lc_conf; 246 union { 247 struct { 248 uint32_t wdata: 9; 249 uint32_t reserved9: 7; 250 uint32_t push: 1; 251 uint32_t reserved17: 15; 252 }; 253 uint32_t val; 254 } out_fifo_push; 255 union { 256 struct { 257 uint32_t rdata: 12; 258 uint32_t reserved12: 4; 259 uint32_t pop: 1; 260 uint32_t reserved17: 15; 261 }; 262 uint32_t val; 263 } in_fifo_pop; 264 uint32_t lc_state0; 265 uint32_t lc_state1; 266 union { 267 struct { 268 uint32_t fifo_timeout: 8; 269 uint32_t fifo_timeout_shift: 3; 270 uint32_t fifo_timeout_ena: 1; 271 uint32_t reserved12: 20; 272 }; 273 uint32_t val; 274 } lc_hung_conf; 275 uint32_t reserved_78; 276 uint32_t reserved_7c; 277 union { 278 struct { 279 uint32_t y_max:16; 280 uint32_t y_min:16; 281 }; 282 uint32_t val; 283 } cvsd_conf0; 284 union { 285 struct { 286 uint32_t sigma_max:16; 287 uint32_t sigma_min:16; 288 }; 289 uint32_t val; 290 } cvsd_conf1; 291 union { 292 struct { 293 uint32_t cvsd_k: 3; 294 uint32_t cvsd_j: 3; 295 uint32_t cvsd_beta: 10; 296 uint32_t cvsd_h: 3; 297 uint32_t reserved19:13; 298 }; 299 uint32_t val; 300 } cvsd_conf2; 301 union { 302 struct { 303 uint32_t good_pack_max: 6; 304 uint32_t n_err_seg: 3; 305 uint32_t shift_rate: 3; 306 uint32_t max_slide_sample: 8; 307 uint32_t pack_len_8k: 5; 308 uint32_t n_min_err: 3; 309 uint32_t reserved28: 4; 310 }; 311 uint32_t val; 312 } plc_conf0; 313 union { 314 struct { 315 uint32_t bad_cef_atten_para: 8; 316 uint32_t bad_cef_atten_para_shift: 4; 317 uint32_t bad_ola_win2_para_shift: 4; 318 uint32_t bad_ola_win2_para: 8; 319 uint32_t slide_win_len: 8; 320 }; 321 uint32_t val; 322 } plc_conf1; 323 union { 324 struct { 325 uint32_t cvsd_seg_mod: 2; 326 uint32_t min_period: 5; 327 uint32_t reserved7: 25; 328 }; 329 uint32_t val; 330 } plc_conf2; 331 union { 332 struct { 333 uint32_t en: 1; 334 uint32_t chan_mod: 1; 335 uint32_t cvsd_dec_pack_err: 1; 336 uint32_t cvsd_pack_len_8k: 5; 337 uint32_t cvsd_inf_en: 1; 338 uint32_t cvsd_dec_start: 1; 339 uint32_t cvsd_dec_reset: 1; 340 uint32_t plc_en: 1; 341 uint32_t plc2dma_en: 1; 342 uint32_t reserved13: 19; 343 }; 344 uint32_t val; 345 } esco_conf0; 346 union { 347 struct { 348 uint32_t with_en: 1; 349 uint32_t no_en: 1; 350 uint32_t cvsd_enc_start: 1; 351 uint32_t cvsd_enc_reset: 1; 352 uint32_t reserved4: 28; 353 }; 354 uint32_t val; 355 } sco_conf0; 356 union { 357 struct { 358 uint32_t tx_pcm_conf: 3; 359 uint32_t tx_pcm_bypass: 1; 360 uint32_t rx_pcm_conf: 3; 361 uint32_t rx_pcm_bypass: 1; 362 uint32_t tx_stop_en: 1; 363 uint32_t tx_zeros_rm_en: 1; 364 uint32_t reserved10: 22; 365 }; 366 uint32_t val; 367 } conf1; 368 union { 369 struct { 370 uint32_t fifo_force_pd: 1; 371 uint32_t fifo_force_pu: 1; 372 uint32_t plc_mem_force_pd: 1; 373 uint32_t plc_mem_force_pu: 1; 374 uint32_t reserved4: 28; 375 }; 376 uint32_t val; 377 } pd_conf; 378 union { 379 struct { 380 uint32_t camera_en: 1; 381 uint32_t lcd_tx_wrx2_en: 1; 382 uint32_t lcd_tx_sdx2_en: 1; 383 uint32_t data_enable_test_en: 1; 384 uint32_t data_enable: 1; 385 uint32_t lcd_en: 1; 386 uint32_t ext_adc_start_en: 1; 387 uint32_t inter_valid_en: 1; 388 uint32_t reserved8: 24; 389 }; 390 uint32_t val; 391 } conf2; 392 union { 393 struct { 394 uint32_t clkm_div_num: 8; 395 uint32_t clkm_div_b: 6; 396 uint32_t clkm_div_a: 6; 397 uint32_t clk_en: 1; 398 uint32_t clka_en: 1; 399 uint32_t reserved22: 10; 400 }; 401 uint32_t val; 402 } clkm_conf; 403 union { 404 struct { 405 uint32_t tx_bck_div_num: 6; 406 uint32_t rx_bck_div_num: 6; 407 uint32_t tx_bits_mod: 6; 408 uint32_t rx_bits_mod: 6; 409 uint32_t reserved24: 8; 410 }; 411 uint32_t val; 412 } sample_rate_conf; 413 union { 414 struct { 415 uint32_t tx_pdm_en: 1; 416 uint32_t rx_pdm_en: 1; 417 uint32_t pcm2pdm_conv_en: 1; 418 uint32_t pdm2pcm_conv_en: 1; 419 uint32_t tx_sinc_osr2: 4; 420 uint32_t tx_prescale: 8; 421 uint32_t tx_hp_in_shift: 2; 422 uint32_t tx_lp_in_shift: 2; 423 uint32_t tx_sinc_in_shift: 2; 424 uint32_t tx_sigmadelta_in_shift: 2; 425 uint32_t rx_sinc_dsr_16_en: 1; 426 uint32_t txhp_bypass: 1; 427 uint32_t reserved26: 6; 428 }; 429 uint32_t val; 430 } pdm_conf; 431 union { 432 struct { 433 uint32_t tx_pdm_fs: 10; 434 uint32_t tx_pdm_fp: 10; 435 uint32_t reserved20:12; 436 }; 437 uint32_t val; 438 } pdm_freq_conf; 439 union { 440 struct { 441 uint32_t tx_idle: 1; 442 uint32_t tx_fifo_reset_back: 1; 443 uint32_t rx_fifo_reset_back: 1; 444 uint32_t reserved3: 29; 445 }; 446 uint32_t val; 447 } state; 448 uint32_t reserved_c0; 449 uint32_t reserved_c4; 450 uint32_t reserved_c8; 451 uint32_t reserved_cc; 452 uint32_t reserved_d0; 453 uint32_t reserved_d4; 454 uint32_t reserved_d8; 455 uint32_t reserved_dc; 456 uint32_t reserved_e0; 457 uint32_t reserved_e4; 458 uint32_t reserved_e8; 459 uint32_t reserved_ec; 460 uint32_t reserved_f0; 461 uint32_t reserved_f4; 462 uint32_t reserved_f8; 463 uint32_t date; /**/ 464 } i2s_dev_t; 465 extern i2s_dev_t I2S0; 466 extern i2s_dev_t I2S1; 467 468 #ifdef __cplusplus 469 } 470 #endif 471 472 #endif /* _SOC_I2S_STRUCT_H_ */ 473