1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_RMT_REG_H_ 15 #define _SOC_RMT_REG_H_ 16 17 #include "soc.h" 18 #define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) 19 20 #define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) 21 22 #define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) 23 24 #define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) 25 26 #define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) 27 28 #define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) 29 30 #define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) 31 32 #define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) 33 34 #define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) 35 /* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 36 /*description: This bit is used to control clock.when software config RMT 37 internal registers it controls the register clock.*/ 38 #define RMT_CLK_EN (BIT(31)) 39 #define RMT_CLK_EN_M (BIT(31)) 40 #define RMT_CLK_EN_V 0x1 41 #define RMT_CLK_EN_S 31 42 /* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ 43 /*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/ 44 #define RMT_MEM_PD (BIT(30)) 45 #define RMT_MEM_PD_M (BIT(30)) 46 #define RMT_MEM_PD_V 0x1 47 #define RMT_MEM_PD_S 30 48 /* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */ 49 /*description: This bit is used to configure the way carrier wave is modulated 50 for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ 51 #define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) 52 #define RMT_CARRIER_OUT_LV_CH0_M (BIT(29)) 53 #define RMT_CARRIER_OUT_LV_CH0_V 0x1 54 #define RMT_CARRIER_OUT_LV_CH0_S 29 55 /* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */ 56 /*description: This is the carrier modulation enable control bit for channel0.*/ 57 #define RMT_CARRIER_EN_CH0 (BIT(28)) 58 #define RMT_CARRIER_EN_CH0_M (BIT(28)) 59 #define RMT_CARRIER_EN_CH0_V 0x1 60 #define RMT_CARRIER_EN_CH0_S 28 61 /* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ 62 /*description: This register is used to configure the the amount of memory blocks 63 allocated to channel0.*/ 64 #define RMT_MEM_SIZE_CH0 0x0000000F 65 #define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) 66 #define RMT_MEM_SIZE_CH0_V 0xF 67 #define RMT_MEM_SIZE_CH0_S 24 68 /* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ 69 /*description: In receive mode when no edge is detected on the input signal 70 for longer than reg_idle_thres_ch0 then the receive process is done.*/ 71 #define RMT_IDLE_THRES_CH0 0x0000FFFF 72 #define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S)) 73 #define RMT_IDLE_THRES_CH0_V 0xFFFF 74 #define RMT_IDLE_THRES_CH0_S 8 75 /* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ 76 /*description: This register is used to configure the frequency divider's factor in channel0.*/ 77 #define RMT_DIV_CNT_CH0 0x000000FF 78 #define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) 79 #define RMT_DIV_CNT_CH0_V 0xFF 80 #define RMT_DIV_CNT_CH0_S 0 81 82 #define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024) 83 /* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ 84 /*description: This is the output enable control bit for channel0 in IDLE state.*/ 85 #define RMT_IDLE_OUT_EN_CH0 (BIT(19)) 86 #define RMT_IDLE_OUT_EN_CH0_M (BIT(19)) 87 #define RMT_IDLE_OUT_EN_CH0_V 0x1 88 #define RMT_IDLE_OUT_EN_CH0_S 19 89 /* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 90 /*description: This bit configures the output signal's level for channel0 in IDLE state.*/ 91 #define RMT_IDLE_OUT_LV_CH0 (BIT(18)) 92 #define RMT_IDLE_OUT_LV_CH0_M (BIT(18)) 93 #define RMT_IDLE_OUT_LV_CH0_V 0x1 94 #define RMT_IDLE_OUT_LV_CH0_S 18 95 /* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 96 /*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ 97 #define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) 98 #define RMT_REF_ALWAYS_ON_CH0_M (BIT(17)) 99 #define RMT_REF_ALWAYS_ON_CH0_V 0x1 100 #define RMT_REF_ALWAYS_ON_CH0_S 17 101 /* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 102 /*description: This bit is used to reset divider in channel0.*/ 103 #define RMT_REF_CNT_RST_CH0 (BIT(16)) 104 #define RMT_REF_CNT_RST_CH0_M (BIT(16)) 105 #define RMT_REF_CNT_RST_CH0_V 0x1 106 #define RMT_REF_CNT_RST_CH0_S 16 107 /* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ 108 /*description: in receive mode channel0 ignore input pulse when the pulse width 109 is smaller then this value.*/ 110 #define RMT_RX_FILTER_THRES_CH0 0x000000FF 111 #define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S)) 112 #define RMT_RX_FILTER_THRES_CH0_V 0xFF 113 #define RMT_RX_FILTER_THRES_CH0_S 8 114 /* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ 115 /*description: This is the receive filter enable bit for channel0.*/ 116 #define RMT_RX_FILTER_EN_CH0 (BIT(7)) 117 #define RMT_RX_FILTER_EN_CH0_M (BIT(7)) 118 #define RMT_RX_FILTER_EN_CH0_V 0x1 119 #define RMT_RX_FILTER_EN_CH0_S 7 120 /* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 121 /*description: Set this bit to continue sending from the first data to the 122 last data in channel0 again and again.*/ 123 #define RMT_TX_CONTI_MODE_CH0 (BIT(6)) 124 #define RMT_TX_CONTI_MODE_CH0_M (BIT(6)) 125 #define RMT_TX_CONTI_MODE_CH0_V 0x1 126 #define RMT_TX_CONTI_MODE_CH0_S 6 127 /* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ 128 /*description: This is the mark of channel0's ram usage right.1'b1：receiver 129 uses the ram 0：transmitter uses the ram*/ 130 #define RMT_MEM_OWNER_CH0 (BIT(5)) 131 #define RMT_MEM_OWNER_CH0_M (BIT(5)) 132 #define RMT_MEM_OWNER_CH0_V 0x1 133 #define RMT_MEM_OWNER_CH0_S 5 134 /* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 135 /*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/ 136 #define RMT_APB_MEM_RST_CH0 (BIT(4)) 137 #define RMT_APB_MEM_RST_CH0_M (BIT(4)) 138 #define RMT_APB_MEM_RST_CH0_V 0x1 139 #define RMT_APB_MEM_RST_CH0_S 4 140 /* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 141 /*description: Set this bit to reset read ram address for channel0 by transmitter access.*/ 142 #define RMT_MEM_RD_RST_CH0 (BIT(3)) 143 #define RMT_MEM_RD_RST_CH0_M (BIT(3)) 144 #define RMT_MEM_RD_RST_CH0_V 0x1 145 #define RMT_MEM_RD_RST_CH0_S 3 146 /* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 147 /*description: Set this bit to reset write ram address for channel0 by receiver access.*/ 148 #define RMT_MEM_WR_RST_CH0 (BIT(2)) 149 #define RMT_MEM_WR_RST_CH0_M (BIT(2)) 150 #define RMT_MEM_WR_RST_CH0_V 0x1 151 #define RMT_MEM_WR_RST_CH0_S 2 152 /* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */ 153 /*description: Set this bit to enbale receving data for channel0.*/ 154 #define RMT_RX_EN_CH0 (BIT(1)) 155 #define RMT_RX_EN_CH0_M (BIT(1)) 156 #define RMT_RX_EN_CH0_V 0x1 157 #define RMT_RX_EN_CH0_S 1 158 /* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 159 /*description: Set this bit to start sending data for channel0.*/ 160 #define RMT_TX_START_CH0 (BIT(0)) 161 #define RMT_TX_START_CH0_M (BIT(0)) 162 #define RMT_TX_START_CH0_V 0x1 163 #define RMT_TX_START_CH0_S 0 164 165 #define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028) 166 /* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */ 167 /*description: This bit is used to configure the way carrier wave is modulated 168 for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ 169 #define RMT_CARRIER_OUT_LV_CH1 (BIT(29)) 170 #define RMT_CARRIER_OUT_LV_CH1_M (BIT(29)) 171 #define RMT_CARRIER_OUT_LV_CH1_V 0x1 172 #define RMT_CARRIER_OUT_LV_CH1_S 29 173 /* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */ 174 /*description: This is the carrier modulation enable control bit for channel1.*/ 175 #define RMT_CARRIER_EN_CH1 (BIT(28)) 176 #define RMT_CARRIER_EN_CH1_M (BIT(28)) 177 #define RMT_CARRIER_EN_CH1_V 0x1 178 #define RMT_CARRIER_EN_CH1_S 28 179 /* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ 180 /*description: This register is used to configure the the amount of memory blocks 181 allocated to channel1.*/ 182 #define RMT_MEM_SIZE_CH1 0x0000000F 183 #define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) 184 #define RMT_MEM_SIZE_CH1_V 0xF 185 #define RMT_MEM_SIZE_CH1_S 24 186 /* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ 187 /*description: This register is used to configure the the amount of memory blocks 188 allocated to channel1.*/ 189 #define RMT_IDLE_THRES_CH1 0x0000FFFF 190 #define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S)) 191 #define RMT_IDLE_THRES_CH1_V 0xFFFF 192 #define RMT_IDLE_THRES_CH1_S 8 193 /* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ 194 /*description: This register is used to configure the frequency divider's factor in channel1.*/ 195 #define RMT_DIV_CNT_CH1 0x000000FF 196 #define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) 197 #define RMT_DIV_CNT_CH1_V 0xFF 198 #define RMT_DIV_CNT_CH1_S 0 199 200 #define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c) 201 /* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ 202 /*description: This is the output enable control bit for channel1 in IDLE state.*/ 203 #define RMT_IDLE_OUT_EN_CH1 (BIT(19)) 204 #define RMT_IDLE_OUT_EN_CH1_M (BIT(19)) 205 #define RMT_IDLE_OUT_EN_CH1_V 0x1 206 #define RMT_IDLE_OUT_EN_CH1_S 19 207 /* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 208 /*description: This bit configures the output signal's level for channel1 in IDLE state.*/ 209 #define RMT_IDLE_OUT_LV_CH1 (BIT(18)) 210 #define RMT_IDLE_OUT_LV_CH1_M (BIT(18)) 211 #define RMT_IDLE_OUT_LV_CH1_V 0x1 212 #define RMT_IDLE_OUT_LV_CH1_S 18 213 /* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 214 /*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ 215 #define RMT_REF_ALWAYS_ON_CH1 (BIT(17)) 216 #define RMT_REF_ALWAYS_ON_CH1_M (BIT(17)) 217 #define RMT_REF_ALWAYS_ON_CH1_V 0x1 218 #define RMT_REF_ALWAYS_ON_CH1_S 17 219 /* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 220 /*description: This bit is used to reset divider in channel1.*/ 221 #define RMT_REF_CNT_RST_CH1 (BIT(16)) 222 #define RMT_REF_CNT_RST_CH1_M (BIT(16)) 223 #define RMT_REF_CNT_RST_CH1_V 0x1 224 #define RMT_REF_CNT_RST_CH1_S 16 225 /* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ 226 /*description: in receive mode channel1 ignore input pulse when the pulse width 227 is smaller then this value.*/ 228 #define RMT_RX_FILTER_THRES_CH1 0x000000FF 229 #define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S)) 230 #define RMT_RX_FILTER_THRES_CH1_V 0xFF 231 #define RMT_RX_FILTER_THRES_CH1_S 8 232 /* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ 233 /*description: This is the receive filter enable bit for channel1.*/ 234 #define RMT_RX_FILTER_EN_CH1 (BIT(7)) 235 #define RMT_RX_FILTER_EN_CH1_M (BIT(7)) 236 #define RMT_RX_FILTER_EN_CH1_V 0x1 237 #define RMT_RX_FILTER_EN_CH1_S 7 238 /* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 239 /*description: Set this bit to continue sending from the first data to the 240 last data in channel1 again and again.*/ 241 #define RMT_TX_CONTI_MODE_CH1 (BIT(6)) 242 #define RMT_TX_CONTI_MODE_CH1_M (BIT(6)) 243 #define RMT_TX_CONTI_MODE_CH1_V 0x1 244 #define RMT_TX_CONTI_MODE_CH1_S 6 245 /* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ 246 /*description: This is the mark of channel1's ram usage right.1'b1：receiver 247 uses the ram 0：transmitter uses the ram*/ 248 #define RMT_MEM_OWNER_CH1 (BIT(5)) 249 #define RMT_MEM_OWNER_CH1_M (BIT(5)) 250 #define RMT_MEM_OWNER_CH1_V 0x1 251 #define RMT_MEM_OWNER_CH1_S 5 252 /* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 253 /*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/ 254 #define RMT_APB_MEM_RST_CH1 (BIT(4)) 255 #define RMT_APB_MEM_RST_CH1_M (BIT(4)) 256 #define RMT_APB_MEM_RST_CH1_V 0x1 257 #define RMT_APB_MEM_RST_CH1_S 4 258 /* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 259 /*description: Set this bit to reset read ram address for channel1 by transmitter access.*/ 260 #define RMT_MEM_RD_RST_CH1 (BIT(3)) 261 #define RMT_MEM_RD_RST_CH1_M (BIT(3)) 262 #define RMT_MEM_RD_RST_CH1_V 0x1 263 #define RMT_MEM_RD_RST_CH1_S 3 264 /* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 265 /*description: Set this bit to reset write ram address for channel1 by receiver access.*/ 266 #define RMT_MEM_WR_RST_CH1 (BIT(2)) 267 #define RMT_MEM_WR_RST_CH1_M (BIT(2)) 268 #define RMT_MEM_WR_RST_CH1_V 0x1 269 #define RMT_MEM_WR_RST_CH1_S 2 270 /* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ 271 /*description: Set this bit to enbale receving data for channel1.*/ 272 #define RMT_RX_EN_CH1 (BIT(1)) 273 #define RMT_RX_EN_CH1_M (BIT(1)) 274 #define RMT_RX_EN_CH1_V 0x1 275 #define RMT_RX_EN_CH1_S 1 276 /* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 277 /*description: Set this bit to start sending data for channel1.*/ 278 #define RMT_TX_START_CH1 (BIT(0)) 279 #define RMT_TX_START_CH1_M (BIT(0)) 280 #define RMT_TX_START_CH1_V 0x1 281 #define RMT_TX_START_CH1_S 0 282 283 #define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030) 284 /* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ 285 /*description: This bit is used to configure carrier wave's position for channel2.1'b1:add 286 on low level 1'b0:add on high level.*/ 287 #define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) 288 #define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) 289 #define RMT_CARRIER_OUT_LV_CH2_V 0x1 290 #define RMT_CARRIER_OUT_LV_CH2_S 29 291 /* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ 292 /*description: This is the carrier modulation enable control bit for channel2.*/ 293 #define RMT_CARRIER_EN_CH2 (BIT(28)) 294 #define RMT_CARRIER_EN_CH2_M (BIT(28)) 295 #define RMT_CARRIER_EN_CH2_V 0x1 296 #define RMT_CARRIER_EN_CH2_S 28 297 /* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ 298 /*description: This register is used to configure the the amount of memory blocks 299 allocated to channel2.*/ 300 #define RMT_MEM_SIZE_CH2 0x0000000F 301 #define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) 302 #define RMT_MEM_SIZE_CH2_V 0xF 303 #define RMT_MEM_SIZE_CH2_S 24 304 /* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ 305 /*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2 306 then the receive process is done.*/ 307 #define RMT_IDLE_THRES_CH2 0x0000FFFF 308 #define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) 309 #define RMT_IDLE_THRES_CH2_V 0xFFFF 310 #define RMT_IDLE_THRES_CH2_S 8 311 /* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ 312 /*description: This register is used to configure the frequency divider's factor in channel2.*/ 313 #define RMT_DIV_CNT_CH2 0x000000FF 314 #define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) 315 #define RMT_DIV_CNT_CH2_V 0xFF 316 #define RMT_DIV_CNT_CH2_S 0 317 318 #define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034) 319 /* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ 320 /*description: This is the output enable control bit for channel2 in IDLE state.*/ 321 #define RMT_IDLE_OUT_EN_CH2 (BIT(19)) 322 #define RMT_IDLE_OUT_EN_CH2_M (BIT(19)) 323 #define RMT_IDLE_OUT_EN_CH2_V 0x1 324 #define RMT_IDLE_OUT_EN_CH2_S 19 325 /* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 326 /*description: This bit configures the output signal's level for channel2 in IDLE state.*/ 327 #define RMT_IDLE_OUT_LV_CH2 (BIT(18)) 328 #define RMT_IDLE_OUT_LV_CH2_M (BIT(18)) 329 #define RMT_IDLE_OUT_LV_CH2_V 0x1 330 #define RMT_IDLE_OUT_LV_CH2_S 18 331 /* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 332 /*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ 333 #define RMT_REF_ALWAYS_ON_CH2 (BIT(17)) 334 #define RMT_REF_ALWAYS_ON_CH2_M (BIT(17)) 335 #define RMT_REF_ALWAYS_ON_CH2_V 0x1 336 #define RMT_REF_ALWAYS_ON_CH2_S 17 337 /* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 338 /*description: This bit is used to reset divider in channel2.*/ 339 #define RMT_REF_CNT_RST_CH2 (BIT(16)) 340 #define RMT_REF_CNT_RST_CH2_M (BIT(16)) 341 #define RMT_REF_CNT_RST_CH2_V 0x1 342 #define RMT_REF_CNT_RST_CH2_S 16 343 /* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ 344 /*description: in receive mode channel2 ignore input pulse when the pulse width 345 is smaller then this value.*/ 346 #define RMT_RX_FILTER_THRES_CH2 0x000000FF 347 #define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) 348 #define RMT_RX_FILTER_THRES_CH2_V 0xFF 349 #define RMT_RX_FILTER_THRES_CH2_S 8 350 /* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ 351 /*description: This is the receive filter enable bit for channel2.*/ 352 #define RMT_RX_FILTER_EN_CH2 (BIT(7)) 353 #define RMT_RX_FILTER_EN_CH2_M (BIT(7)) 354 #define RMT_RX_FILTER_EN_CH2_V 0x1 355 #define RMT_RX_FILTER_EN_CH2_S 7 356 /* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 357 /*description: Set this bit to continue sending from the first data to the 358 last data in channel2.*/ 359 #define RMT_TX_CONTI_MODE_CH2 (BIT(6)) 360 #define RMT_TX_CONTI_MODE_CH2_M (BIT(6)) 361 #define RMT_TX_CONTI_MODE_CH2_V 0x1 362 #define RMT_TX_CONTI_MODE_CH2_S 6 363 /* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ 364 /*description: This is the mark of channel2's ram usage right.1'b1：receiver 365 uses the ram 0：transmitter uses the ram*/ 366 #define RMT_MEM_OWNER_CH2 (BIT(5)) 367 #define RMT_MEM_OWNER_CH2_M (BIT(5)) 368 #define RMT_MEM_OWNER_CH2_V 0x1 369 #define RMT_MEM_OWNER_CH2_S 5 370 /* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 371 /*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/ 372 #define RMT_APB_MEM_RST_CH2 (BIT(4)) 373 #define RMT_APB_MEM_RST_CH2_M (BIT(4)) 374 #define RMT_APB_MEM_RST_CH2_V 0x1 375 #define RMT_APB_MEM_RST_CH2_S 4 376 /* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 377 /*description: Set this bit to reset read ram address for channel2 by transmitter access.*/ 378 #define RMT_MEM_RD_RST_CH2 (BIT(3)) 379 #define RMT_MEM_RD_RST_CH2_M (BIT(3)) 380 #define RMT_MEM_RD_RST_CH2_V 0x1 381 #define RMT_MEM_RD_RST_CH2_S 3 382 /* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 383 /*description: Set this bit to reset write ram address for channel2 by receiver access.*/ 384 #define RMT_MEM_WR_RST_CH2 (BIT(2)) 385 #define RMT_MEM_WR_RST_CH2_M (BIT(2)) 386 #define RMT_MEM_WR_RST_CH2_V 0x1 387 #define RMT_MEM_WR_RST_CH2_S 2 388 /* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */ 389 /*description: Set this bit to enbale receving data for channel2.*/ 390 #define RMT_RX_EN_CH2 (BIT(1)) 391 #define RMT_RX_EN_CH2_M (BIT(1)) 392 #define RMT_RX_EN_CH2_V 0x1 393 #define RMT_RX_EN_CH2_S 1 394 /* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 395 /*description: Set this bit to start sending data for channel2.*/ 396 #define RMT_TX_START_CH2 (BIT(0)) 397 #define RMT_TX_START_CH2_M (BIT(0)) 398 #define RMT_TX_START_CH2_V 0x1 399 #define RMT_TX_START_CH2_S 0 400 401 #define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038) 402 /* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ 403 /*description: This bit is used to configure carrier wave's position for channel3.1'b1:add 404 on low level 1'b0:add on high level.*/ 405 #define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) 406 #define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) 407 #define RMT_CARRIER_OUT_LV_CH3_V 0x1 408 #define RMT_CARRIER_OUT_LV_CH3_S 29 409 /* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ 410 /*description: This is the carrier modulation enable control bit for channel3.*/ 411 #define RMT_CARRIER_EN_CH3 (BIT(28)) 412 #define RMT_CARRIER_EN_CH3_M (BIT(28)) 413 #define RMT_CARRIER_EN_CH3_V 0x1 414 #define RMT_CARRIER_EN_CH3_S 28 415 /* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ 416 /*description: This register is used to configure the the amount of memory blocks 417 allocated to channel3.*/ 418 #define RMT_MEM_SIZE_CH3 0x0000000F 419 #define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) 420 #define RMT_MEM_SIZE_CH3_V 0xF 421 #define RMT_MEM_SIZE_CH3_S 24 422 /* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ 423 /*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3 424 then the receive process is done.*/ 425 #define RMT_IDLE_THRES_CH3 0x0000FFFF 426 #define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) 427 #define RMT_IDLE_THRES_CH3_V 0xFFFF 428 #define RMT_IDLE_THRES_CH3_S 8 429 /* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ 430 /*description: This register is used to configure the frequency divider's factor in channel3.*/ 431 #define RMT_DIV_CNT_CH3 0x000000FF 432 #define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) 433 #define RMT_DIV_CNT_CH3_V 0xFF 434 #define RMT_DIV_CNT_CH3_S 0 435 436 #define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c) 437 /* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ 438 /*description: This is the output enable control bit for channel3 in IDLE state.*/ 439 #define RMT_IDLE_OUT_EN_CH3 (BIT(19)) 440 #define RMT_IDLE_OUT_EN_CH3_M (BIT(19)) 441 #define RMT_IDLE_OUT_EN_CH3_V 0x1 442 #define RMT_IDLE_OUT_EN_CH3_S 19 443 /* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 444 /*description: This bit configures the output signal's level for channel3 in IDLE state.*/ 445 #define RMT_IDLE_OUT_LV_CH3 (BIT(18)) 446 #define RMT_IDLE_OUT_LV_CH3_M (BIT(18)) 447 #define RMT_IDLE_OUT_LV_CH3_V 0x1 448 #define RMT_IDLE_OUT_LV_CH3_S 18 449 /* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 450 /*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ 451 #define RMT_REF_ALWAYS_ON_CH3 (BIT(17)) 452 #define RMT_REF_ALWAYS_ON_CH3_M (BIT(17)) 453 #define RMT_REF_ALWAYS_ON_CH3_V 0x1 454 #define RMT_REF_ALWAYS_ON_CH3_S 17 455 /* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 456 /*description: This bit is used to reset divider in channel3.*/ 457 #define RMT_REF_CNT_RST_CH3 (BIT(16)) 458 #define RMT_REF_CNT_RST_CH3_M (BIT(16)) 459 #define RMT_REF_CNT_RST_CH3_V 0x1 460 #define RMT_REF_CNT_RST_CH3_S 16 461 /* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ 462 /*description: in receive mode channel3 ignore input pulse when the pulse width 463 is smaller then this value.*/ 464 #define RMT_RX_FILTER_THRES_CH3 0x000000FF 465 #define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) 466 #define RMT_RX_FILTER_THRES_CH3_V 0xFF 467 #define RMT_RX_FILTER_THRES_CH3_S 8 468 /* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ 469 /*description: This is the receive filter enable bit for channel3.*/ 470 #define RMT_RX_FILTER_EN_CH3 (BIT(7)) 471 #define RMT_RX_FILTER_EN_CH3_M (BIT(7)) 472 #define RMT_RX_FILTER_EN_CH3_V 0x1 473 #define RMT_RX_FILTER_EN_CH3_S 7 474 /* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 475 /*description: Set this bit to continue sending from the first data to the 476 last data in channel3.*/ 477 #define RMT_TX_CONTI_MODE_CH3 (BIT(6)) 478 #define RMT_TX_CONTI_MODE_CH3_M (BIT(6)) 479 #define RMT_TX_CONTI_MODE_CH3_V 0x1 480 #define RMT_TX_CONTI_MODE_CH3_S 6 481 /* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ 482 /*description: This is the mark of channel3's ram usage right.1'b1：receiver 483 uses the ram 0：transmitter uses the ram*/ 484 #define RMT_MEM_OWNER_CH3 (BIT(5)) 485 #define RMT_MEM_OWNER_CH3_M (BIT(5)) 486 #define RMT_MEM_OWNER_CH3_V 0x1 487 #define RMT_MEM_OWNER_CH3_S 5 488 /* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 489 /*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/ 490 #define RMT_APB_MEM_RST_CH3 (BIT(4)) 491 #define RMT_APB_MEM_RST_CH3_M (BIT(4)) 492 #define RMT_APB_MEM_RST_CH3_V 0x1 493 #define RMT_APB_MEM_RST_CH3_S 4 494 /* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 495 /*description: Set this bit to reset read ram address for channel3 by transmitter access.*/ 496 #define RMT_MEM_RD_RST_CH3 (BIT(3)) 497 #define RMT_MEM_RD_RST_CH3_M (BIT(3)) 498 #define RMT_MEM_RD_RST_CH3_V 0x1 499 #define RMT_MEM_RD_RST_CH3_S 3 500 /* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 501 /*description: Set this bit to reset write ram address for channel3 by receiver access.*/ 502 #define RMT_MEM_WR_RST_CH3 (BIT(2)) 503 #define RMT_MEM_WR_RST_CH3_M (BIT(2)) 504 #define RMT_MEM_WR_RST_CH3_V 0x1 505 #define RMT_MEM_WR_RST_CH3_S 2 506 /* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */ 507 /*description: Set this bit to enbale receving data for channel3.*/ 508 #define RMT_RX_EN_CH3 (BIT(1)) 509 #define RMT_RX_EN_CH3_M (BIT(1)) 510 #define RMT_RX_EN_CH3_V 0x1 511 #define RMT_RX_EN_CH3_S 1 512 /* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 513 /*description: Set this bit to start sending data for channel3.*/ 514 #define RMT_TX_START_CH3 (BIT(0)) 515 #define RMT_TX_START_CH3_M (BIT(0)) 516 #define RMT_TX_START_CH3_V 0x1 517 #define RMT_TX_START_CH3_S 0 518 519 #define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040) 520 /* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ 521 /*description: This bit is used to configure carrier wave's position for channel4.1'b1:add 522 on low level 1'b0:add on high level.*/ 523 #define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) 524 #define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) 525 #define RMT_CARRIER_OUT_LV_CH4_V 0x1 526 #define RMT_CARRIER_OUT_LV_CH4_S 29 527 /* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ 528 /*description: This is the carrier modulation enable control bit for channel4.*/ 529 #define RMT_CARRIER_EN_CH4 (BIT(28)) 530 #define RMT_CARRIER_EN_CH4_M (BIT(28)) 531 #define RMT_CARRIER_EN_CH4_V 0x1 532 #define RMT_CARRIER_EN_CH4_S 28 533 /* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ 534 /*description: This register is used to configure the the amount of memory blocks 535 allocated to channel4.*/ 536 #define RMT_MEM_SIZE_CH4 0x0000000F 537 #define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) 538 #define RMT_MEM_SIZE_CH4_V 0xF 539 #define RMT_MEM_SIZE_CH4_S 24 540 /* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ 541 /*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4 542 then the receive process is done.*/ 543 #define RMT_IDLE_THRES_CH4 0x0000FFFF 544 #define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) 545 #define RMT_IDLE_THRES_CH4_V 0xFFFF 546 #define RMT_IDLE_THRES_CH4_S 8 547 /* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ 548 /*description: This register is used to configure the frequency divider's factor in channel4.*/ 549 #define RMT_DIV_CNT_CH4 0x000000FF 550 #define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) 551 #define RMT_DIV_CNT_CH4_V 0xFF 552 #define RMT_DIV_CNT_CH4_S 0 553 554 #define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044) 555 /* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */ 556 /*description: This is the output enable control bit for channel4 in IDLE state.*/ 557 #define RMT_IDLE_OUT_EN_CH4 (BIT(19)) 558 #define RMT_IDLE_OUT_EN_CH4_M (BIT(19)) 559 #define RMT_IDLE_OUT_EN_CH4_V 0x1 560 #define RMT_IDLE_OUT_EN_CH4_S 19 561 /* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 562 /*description: This bit configures the output signal's level for channel4 in IDLE state.*/ 563 #define RMT_IDLE_OUT_LV_CH4 (BIT(18)) 564 #define RMT_IDLE_OUT_LV_CH4_M (BIT(18)) 565 #define RMT_IDLE_OUT_LV_CH4_V 0x1 566 #define RMT_IDLE_OUT_LV_CH4_S 18 567 /* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 568 /*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ 569 #define RMT_REF_ALWAYS_ON_CH4 (BIT(17)) 570 #define RMT_REF_ALWAYS_ON_CH4_M (BIT(17)) 571 #define RMT_REF_ALWAYS_ON_CH4_V 0x1 572 #define RMT_REF_ALWAYS_ON_CH4_S 17 573 /* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 574 /*description: This bit is used to reset divider in channel4.*/ 575 #define RMT_REF_CNT_RST_CH4 (BIT(16)) 576 #define RMT_REF_CNT_RST_CH4_M (BIT(16)) 577 #define RMT_REF_CNT_RST_CH4_V 0x1 578 #define RMT_REF_CNT_RST_CH4_S 16 579 /* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ 580 /*description: in receive mode channel4 ignore input pulse when the pulse width 581 is smaller then this value.*/ 582 #define RMT_RX_FILTER_THRES_CH4 0x000000FF 583 #define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) 584 #define RMT_RX_FILTER_THRES_CH4_V 0xFF 585 #define RMT_RX_FILTER_THRES_CH4_S 8 586 /* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ 587 /*description: This is the receive filter enable bit for channel4.*/ 588 #define RMT_RX_FILTER_EN_CH4 (BIT(7)) 589 #define RMT_RX_FILTER_EN_CH4_M (BIT(7)) 590 #define RMT_RX_FILTER_EN_CH4_V 0x1 591 #define RMT_RX_FILTER_EN_CH4_S 7 592 /* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 593 /*description: Set this bit to continue sending from the first data to the 594 last data in channel4.*/ 595 #define RMT_TX_CONTI_MODE_CH4 (BIT(6)) 596 #define RMT_TX_CONTI_MODE_CH4_M (BIT(6)) 597 #define RMT_TX_CONTI_MODE_CH4_V 0x1 598 #define RMT_TX_CONTI_MODE_CH4_S 6 599 /* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ 600 /*description: This is the mark of channel4's ram usage right.1'b1：receiver 601 uses the ram 0：transmitter uses the ram*/ 602 #define RMT_MEM_OWNER_CH4 (BIT(5)) 603 #define RMT_MEM_OWNER_CH4_M (BIT(5)) 604 #define RMT_MEM_OWNER_CH4_V 0x1 605 #define RMT_MEM_OWNER_CH4_S 5 606 /* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 607 /*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/ 608 #define RMT_APB_MEM_RST_CH4 (BIT(4)) 609 #define RMT_APB_MEM_RST_CH4_M (BIT(4)) 610 #define RMT_APB_MEM_RST_CH4_V 0x1 611 #define RMT_APB_MEM_RST_CH4_S 4 612 /* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 613 /*description: Set this bit to reset read ram address for channel4 by transmitter access.*/ 614 #define RMT_MEM_RD_RST_CH4 (BIT(3)) 615 #define RMT_MEM_RD_RST_CH4_M (BIT(3)) 616 #define RMT_MEM_RD_RST_CH4_V 0x1 617 #define RMT_MEM_RD_RST_CH4_S 3 618 /* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 619 /*description: Set this bit to reset write ram address for channel4 by receiver access.*/ 620 #define RMT_MEM_WR_RST_CH4 (BIT(2)) 621 #define RMT_MEM_WR_RST_CH4_M (BIT(2)) 622 #define RMT_MEM_WR_RST_CH4_V 0x1 623 #define RMT_MEM_WR_RST_CH4_S 2 624 /* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */ 625 /*description: Set this bit to enbale receving data for channel4.*/ 626 #define RMT_RX_EN_CH4 (BIT(1)) 627 #define RMT_RX_EN_CH4_M (BIT(1)) 628 #define RMT_RX_EN_CH4_V 0x1 629 #define RMT_RX_EN_CH4_S 1 630 /* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 631 /*description: Set this bit to start sending data for channel4.*/ 632 #define RMT_TX_START_CH4 (BIT(0)) 633 #define RMT_TX_START_CH4_M (BIT(0)) 634 #define RMT_TX_START_CH4_V 0x1 635 #define RMT_TX_START_CH4_S 0 636 637 #define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048) 638 /* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ 639 /*description: This bit is used to configure carrier wave's position for channel5.1'b1:add 640 on low level 1'b0:add on high level.*/ 641 #define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) 642 #define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) 643 #define RMT_CARRIER_OUT_LV_CH5_V 0x1 644 #define RMT_CARRIER_OUT_LV_CH5_S 29 645 /* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ 646 /*description: This is the carrier modulation enable control bit for channel5.*/ 647 #define RMT_CARRIER_EN_CH5 (BIT(28)) 648 #define RMT_CARRIER_EN_CH5_M (BIT(28)) 649 #define RMT_CARRIER_EN_CH5_V 0x1 650 #define RMT_CARRIER_EN_CH5_S 28 651 /* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ 652 /*description: This register is used to configure the the amount of memory blocks 653 allocated to channel5.*/ 654 #define RMT_MEM_SIZE_CH5 0x0000000F 655 #define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) 656 #define RMT_MEM_SIZE_CH5_V 0xF 657 #define RMT_MEM_SIZE_CH5_S 24 658 /* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ 659 /*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5 660 then the receive process is done.*/ 661 #define RMT_IDLE_THRES_CH5 0x0000FFFF 662 #define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) 663 #define RMT_IDLE_THRES_CH5_V 0xFFFF 664 #define RMT_IDLE_THRES_CH5_S 8 665 /* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ 666 /*description: This register is used to configure the frequency divider's factor in channel5.*/ 667 #define RMT_DIV_CNT_CH5 0x000000FF 668 #define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) 669 #define RMT_DIV_CNT_CH5_V 0xFF 670 #define RMT_DIV_CNT_CH5_S 0 671 672 #define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c) 673 /* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */ 674 /*description: This is the output enable control bit for channel5 in IDLE state.*/ 675 #define RMT_IDLE_OUT_EN_CH5 (BIT(19)) 676 #define RMT_IDLE_OUT_EN_CH5_M (BIT(19)) 677 #define RMT_IDLE_OUT_EN_CH5_V 0x1 678 #define RMT_IDLE_OUT_EN_CH5_S 19 679 /* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 680 /*description: This bit configures the output signal's level for channel5 in IDLE state.*/ 681 #define RMT_IDLE_OUT_LV_CH5 (BIT(18)) 682 #define RMT_IDLE_OUT_LV_CH5_M (BIT(18)) 683 #define RMT_IDLE_OUT_LV_CH5_V 0x1 684 #define RMT_IDLE_OUT_LV_CH5_S 18 685 /* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 686 /*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ 687 #define RMT_REF_ALWAYS_ON_CH5 (BIT(17)) 688 #define RMT_REF_ALWAYS_ON_CH5_M (BIT(17)) 689 #define RMT_REF_ALWAYS_ON_CH5_V 0x1 690 #define RMT_REF_ALWAYS_ON_CH5_S 17 691 /* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 692 /*description: This bit is used to reset divider in channel5.*/ 693 #define RMT_REF_CNT_RST_CH5 (BIT(16)) 694 #define RMT_REF_CNT_RST_CH5_M (BIT(16)) 695 #define RMT_REF_CNT_RST_CH5_V 0x1 696 #define RMT_REF_CNT_RST_CH5_S 16 697 /* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ 698 /*description: in receive mode channel5 ignore input pulse when the pulse width 699 is smaller then this value.*/ 700 #define RMT_RX_FILTER_THRES_CH5 0x000000FF 701 #define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) 702 #define RMT_RX_FILTER_THRES_CH5_V 0xFF 703 #define RMT_RX_FILTER_THRES_CH5_S 8 704 /* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ 705 /*description: This is the receive filter enable bit for channel5.*/ 706 #define RMT_RX_FILTER_EN_CH5 (BIT(7)) 707 #define RMT_RX_FILTER_EN_CH5_M (BIT(7)) 708 #define RMT_RX_FILTER_EN_CH5_V 0x1 709 #define RMT_RX_FILTER_EN_CH5_S 7 710 /* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 711 /*description: Set this bit to continue sending from the first data to the 712 last data in channel5.*/ 713 #define RMT_TX_CONTI_MODE_CH5 (BIT(6)) 714 #define RMT_TX_CONTI_MODE_CH5_M (BIT(6)) 715 #define RMT_TX_CONTI_MODE_CH5_V 0x1 716 #define RMT_TX_CONTI_MODE_CH5_S 6 717 /* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */ 718 /*description: This is the mark of channel5's ram usage right.1'b1：receiver 719 uses the ram 0：transmitter uses the ram*/ 720 #define RMT_MEM_OWNER_CH5 (BIT(5)) 721 #define RMT_MEM_OWNER_CH5_M (BIT(5)) 722 #define RMT_MEM_OWNER_CH5_V 0x1 723 #define RMT_MEM_OWNER_CH5_S 5 724 /* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 725 /*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/ 726 #define RMT_APB_MEM_RST_CH5 (BIT(4)) 727 #define RMT_APB_MEM_RST_CH5_M (BIT(4)) 728 #define RMT_APB_MEM_RST_CH5_V 0x1 729 #define RMT_APB_MEM_RST_CH5_S 4 730 /* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 731 /*description: Set this bit to reset read ram address for channel5 by transmitter access.*/ 732 #define RMT_MEM_RD_RST_CH5 (BIT(3)) 733 #define RMT_MEM_RD_RST_CH5_M (BIT(3)) 734 #define RMT_MEM_RD_RST_CH5_V 0x1 735 #define RMT_MEM_RD_RST_CH5_S 3 736 /* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 737 /*description: Set this bit to reset write ram address for channel5 by receiver access.*/ 738 #define RMT_MEM_WR_RST_CH5 (BIT(2)) 739 #define RMT_MEM_WR_RST_CH5_M (BIT(2)) 740 #define RMT_MEM_WR_RST_CH5_V 0x1 741 #define RMT_MEM_WR_RST_CH5_S 2 742 /* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */ 743 /*description: Set this bit to enbale receving data for channel5.*/ 744 #define RMT_RX_EN_CH5 (BIT(1)) 745 #define RMT_RX_EN_CH5_M (BIT(1)) 746 #define RMT_RX_EN_CH5_V 0x1 747 #define RMT_RX_EN_CH5_S 1 748 /* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 749 /*description: Set this bit to start sending data for channel5.*/ 750 #define RMT_TX_START_CH5 (BIT(0)) 751 #define RMT_TX_START_CH5_M (BIT(0)) 752 #define RMT_TX_START_CH5_V 0x1 753 #define RMT_TX_START_CH5_S 0 754 755 #define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050) 756 /* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ 757 /*description: This bit is used to configure carrier wave's position for channel6.1'b1:add 758 on low level 1'b0:add on high level.*/ 759 #define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) 760 #define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) 761 #define RMT_CARRIER_OUT_LV_CH6_V 0x1 762 #define RMT_CARRIER_OUT_LV_CH6_S 29 763 /* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ 764 /*description: This is the carrier modulation enable control bit for channel6.*/ 765 #define RMT_CARRIER_EN_CH6 (BIT(28)) 766 #define RMT_CARRIER_EN_CH6_M (BIT(28)) 767 #define RMT_CARRIER_EN_CH6_V 0x1 768 #define RMT_CARRIER_EN_CH6_S 28 769 /* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ 770 /*description: This register is used to configure the the amount of memory blocks 771 allocated to channel6.*/ 772 #define RMT_MEM_SIZE_CH6 0x0000000F 773 #define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) 774 #define RMT_MEM_SIZE_CH6_V 0xF 775 #define RMT_MEM_SIZE_CH6_S 24 776 /* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ 777 /*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6 778 then the receive process is done.*/ 779 #define RMT_IDLE_THRES_CH6 0x0000FFFF 780 #define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) 781 #define RMT_IDLE_THRES_CH6_V 0xFFFF 782 #define RMT_IDLE_THRES_CH6_S 8 783 /* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ 784 /*description: This register is used to configure the frequency divider's factor in channel6.*/ 785 #define RMT_DIV_CNT_CH6 0x000000FF 786 #define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) 787 #define RMT_DIV_CNT_CH6_V 0xFF 788 #define RMT_DIV_CNT_CH6_S 0 789 790 #define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054) 791 /* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */ 792 /*description: This is the output enable control bit for channel6 in IDLE state.*/ 793 #define RMT_IDLE_OUT_EN_CH6 (BIT(19)) 794 #define RMT_IDLE_OUT_EN_CH6_M (BIT(19)) 795 #define RMT_IDLE_OUT_EN_CH6_V 0x1 796 #define RMT_IDLE_OUT_EN_CH6_S 19 797 /* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 798 /*description: This bit configures the output signal's level for channel6 in IDLE state.*/ 799 #define RMT_IDLE_OUT_LV_CH6 (BIT(18)) 800 #define RMT_IDLE_OUT_LV_CH6_M (BIT(18)) 801 #define RMT_IDLE_OUT_LV_CH6_V 0x1 802 #define RMT_IDLE_OUT_LV_CH6_S 18 803 /* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 804 /*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ 805 #define RMT_REF_ALWAYS_ON_CH6 (BIT(17)) 806 #define RMT_REF_ALWAYS_ON_CH6_M (BIT(17)) 807 #define RMT_REF_ALWAYS_ON_CH6_V 0x1 808 #define RMT_REF_ALWAYS_ON_CH6_S 17 809 /* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 810 /*description: This bit is used to reset divider in channel6.*/ 811 #define RMT_REF_CNT_RST_CH6 (BIT(16)) 812 #define RMT_REF_CNT_RST_CH6_M (BIT(16)) 813 #define RMT_REF_CNT_RST_CH6_V 0x1 814 #define RMT_REF_CNT_RST_CH6_S 16 815 /* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ 816 /*description: in receive mode channel6 ignore input pulse when the pulse width 817 is smaller then this value.*/ 818 #define RMT_RX_FILTER_THRES_CH6 0x000000FF 819 #define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) 820 #define RMT_RX_FILTER_THRES_CH6_V 0xFF 821 #define RMT_RX_FILTER_THRES_CH6_S 8 822 /* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */ 823 /*description: This is the receive filter enable bit for channel6.*/ 824 #define RMT_RX_FILTER_EN_CH6 (BIT(7)) 825 #define RMT_RX_FILTER_EN_CH6_M (BIT(7)) 826 #define RMT_RX_FILTER_EN_CH6_V 0x1 827 #define RMT_RX_FILTER_EN_CH6_S 7 828 /* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 829 /*description: Set this bit to continue sending from the first data to the 830 last data in channel6.*/ 831 #define RMT_TX_CONTI_MODE_CH6 (BIT(6)) 832 #define RMT_TX_CONTI_MODE_CH6_M (BIT(6)) 833 #define RMT_TX_CONTI_MODE_CH6_V 0x1 834 #define RMT_TX_CONTI_MODE_CH6_S 6 835 /* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */ 836 /*description: This is the mark of channel6's ram usage right.1'b1：receiver 837 uses the ram 0：transmitter uses the ram*/ 838 #define RMT_MEM_OWNER_CH6 (BIT(5)) 839 #define RMT_MEM_OWNER_CH6_M (BIT(5)) 840 #define RMT_MEM_OWNER_CH6_V 0x1 841 #define RMT_MEM_OWNER_CH6_S 5 842 /* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 843 /*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/ 844 #define RMT_APB_MEM_RST_CH6 (BIT(4)) 845 #define RMT_APB_MEM_RST_CH6_M (BIT(4)) 846 #define RMT_APB_MEM_RST_CH6_V 0x1 847 #define RMT_APB_MEM_RST_CH6_S 4 848 /* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 849 /*description: Set this bit to reset read ram address for channel6 by transmitter access.*/ 850 #define RMT_MEM_RD_RST_CH6 (BIT(3)) 851 #define RMT_MEM_RD_RST_CH6_M (BIT(3)) 852 #define RMT_MEM_RD_RST_CH6_V 0x1 853 #define RMT_MEM_RD_RST_CH6_S 3 854 /* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 855 /*description: Set this bit to reset write ram address for channel6 by receiver access.*/ 856 #define RMT_MEM_WR_RST_CH6 (BIT(2)) 857 #define RMT_MEM_WR_RST_CH6_M (BIT(2)) 858 #define RMT_MEM_WR_RST_CH6_V 0x1 859 #define RMT_MEM_WR_RST_CH6_S 2 860 /* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */ 861 /*description: Set this bit to enbale receving data for channel6.*/ 862 #define RMT_RX_EN_CH6 (BIT(1)) 863 #define RMT_RX_EN_CH6_M (BIT(1)) 864 #define RMT_RX_EN_CH6_V 0x1 865 #define RMT_RX_EN_CH6_S 1 866 /* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 867 /*description: Set this bit to start sending data for channel6.*/ 868 #define RMT_TX_START_CH6 (BIT(0)) 869 #define RMT_TX_START_CH6_M (BIT(0)) 870 #define RMT_TX_START_CH6_V 0x1 871 #define RMT_TX_START_CH6_S 0 872 873 #define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058) 874 /* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ 875 /*description: This bit is used to configure carrier wave's position for channel7.1'b1:add 876 on low level 1'b0:add on high level.*/ 877 #define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) 878 #define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) 879 #define RMT_CARRIER_OUT_LV_CH7_V 0x1 880 #define RMT_CARRIER_OUT_LV_CH7_S 29 881 /* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ 882 /*description: This is the carrier modulation enable control bit for channel7.*/ 883 #define RMT_CARRIER_EN_CH7 (BIT(28)) 884 #define RMT_CARRIER_EN_CH7_M (BIT(28)) 885 #define RMT_CARRIER_EN_CH7_V 0x1 886 #define RMT_CARRIER_EN_CH7_S 28 887 /* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ 888 /*description: This register is used to configure the the amount of memory blocks 889 allocated to channel7.*/ 890 #define RMT_MEM_SIZE_CH7 0x0000000F 891 #define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) 892 #define RMT_MEM_SIZE_CH7_V 0xF 893 #define RMT_MEM_SIZE_CH7_S 24 894 /* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ 895 /*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7 896 then the receive process is done.*/ 897 #define RMT_IDLE_THRES_CH7 0x0000FFFF 898 #define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) 899 #define RMT_IDLE_THRES_CH7_V 0xFFFF 900 #define RMT_IDLE_THRES_CH7_S 8 901 /* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ 902 /*description: This register is used to configure the frequency divider's factor in channel7.*/ 903 #define RMT_DIV_CNT_CH7 0x000000FF 904 #define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) 905 #define RMT_DIV_CNT_CH7_V 0xFF 906 #define RMT_DIV_CNT_CH7_S 0 907 908 #define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c) 909 /* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */ 910 /*description: This is the output enable control bit for channel6 in IDLE state.*/ 911 #define RMT_IDLE_OUT_EN_CH7 (BIT(19)) 912 #define RMT_IDLE_OUT_EN_CH7_M (BIT(19)) 913 #define RMT_IDLE_OUT_EN_CH7_V 0x1 914 #define RMT_IDLE_OUT_EN_CH7_S 19 915 /* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 916 /*description: This bit configures the output signal's level for channel7 in IDLE state.*/ 917 #define RMT_IDLE_OUT_LV_CH7 (BIT(18)) 918 #define RMT_IDLE_OUT_LV_CH7_M (BIT(18)) 919 #define RMT_IDLE_OUT_LV_CH7_V 0x1 920 #define RMT_IDLE_OUT_LV_CH7_S 18 921 /* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 922 /*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ 923 #define RMT_REF_ALWAYS_ON_CH7 (BIT(17)) 924 #define RMT_REF_ALWAYS_ON_CH7_M (BIT(17)) 925 #define RMT_REF_ALWAYS_ON_CH7_V 0x1 926 #define RMT_REF_ALWAYS_ON_CH7_S 17 927 /* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 928 /*description: This bit is used to reset divider in channel7.*/ 929 #define RMT_REF_CNT_RST_CH7 (BIT(16)) 930 #define RMT_REF_CNT_RST_CH7_M (BIT(16)) 931 #define RMT_REF_CNT_RST_CH7_V 0x1 932 #define RMT_REF_CNT_RST_CH7_S 16 933 /* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ 934 /*description: in receive mode channel7 ignore input pulse when the pulse width 935 is smaller then this value.*/ 936 #define RMT_RX_FILTER_THRES_CH7 0x000000FF 937 #define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) 938 #define RMT_RX_FILTER_THRES_CH7_V 0xFF 939 #define RMT_RX_FILTER_THRES_CH7_S 8 940 /* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */ 941 /*description: This is the receive filter enable bit for channel7.*/ 942 #define RMT_RX_FILTER_EN_CH7 (BIT(7)) 943 #define RMT_RX_FILTER_EN_CH7_M (BIT(7)) 944 #define RMT_RX_FILTER_EN_CH7_V 0x1 945 #define RMT_RX_FILTER_EN_CH7_S 7 946 /* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */ 947 /*description: Set this bit to continue sending from the first data to the 948 last data in channel7.*/ 949 #define RMT_TX_CONTI_MODE_CH7 (BIT(6)) 950 #define RMT_TX_CONTI_MODE_CH7_M (BIT(6)) 951 #define RMT_TX_CONTI_MODE_CH7_V 0x1 952 #define RMT_TX_CONTI_MODE_CH7_S 6 953 /* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */ 954 /*description: This is the mark of channel7's ram usage right.1'b1：receiver 955 uses the ram 0：transmitter uses the ram*/ 956 #define RMT_MEM_OWNER_CH7 (BIT(5)) 957 #define RMT_MEM_OWNER_CH7_M (BIT(5)) 958 #define RMT_MEM_OWNER_CH7_V 0x1 959 #define RMT_MEM_OWNER_CH7_S 5 960 /* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 961 /*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/ 962 #define RMT_APB_MEM_RST_CH7 (BIT(4)) 963 #define RMT_APB_MEM_RST_CH7_M (BIT(4)) 964 #define RMT_APB_MEM_RST_CH7_V 0x1 965 #define RMT_APB_MEM_RST_CH7_S 4 966 /* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 967 /*description: Set this bit to reset read ram address for channel7 by transmitter access.*/ 968 #define RMT_MEM_RD_RST_CH7 (BIT(3)) 969 #define RMT_MEM_RD_RST_CH7_M (BIT(3)) 970 #define RMT_MEM_RD_RST_CH7_V 0x1 971 #define RMT_MEM_RD_RST_CH7_S 3 972 /* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */ 973 /*description: Set this bit to reset write ram address for channel7 by receiver access.*/ 974 #define RMT_MEM_WR_RST_CH7 (BIT(2)) 975 #define RMT_MEM_WR_RST_CH7_M (BIT(2)) 976 #define RMT_MEM_WR_RST_CH7_V 0x1 977 #define RMT_MEM_WR_RST_CH7_S 2 978 /* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */ 979 /*description: Set this bit to enbale receving data for channel7.*/ 980 #define RMT_RX_EN_CH7 (BIT(1)) 981 #define RMT_RX_EN_CH7_M (BIT(1)) 982 #define RMT_RX_EN_CH7_V 0x1 983 #define RMT_RX_EN_CH7_S 1 984 /* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 985 /*description: Set this bit to start sending data for channel7.*/ 986 #define RMT_TX_START_CH7 (BIT(0)) 987 #define RMT_TX_START_CH7_M (BIT(0)) 988 #define RMT_TX_START_CH7_V 0x1 989 #define RMT_TX_START_CH7_S 0 990 991 #define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060) 992 /* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 993 /*description: The status for channel0*/ 994 #define RMT_STATUS_CH0 0xFFFFFFFF 995 #define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S)) 996 #define RMT_STATUS_CH0_V 0xFFFFFFFF 997 #define RMT_STATUS_CH0_S 0 998 /* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[31] ;default: 1'b0 ; */ 999 /*description: The apb read memory status bit for channel0 turns to 1000 high level when the apb read address exceeds the configuration range.*/ 1001 #define RMT_APB_MEM_RD_ERR_CH0 (BIT(31)) 1002 #define RMT_APB_MEM_RD_ERR_CH0_M ((RMT_APB_MEM_RD_ERR_CH0_V)<<(RMT_APB_MEM_RD_ERR_CH0_S)) 1003 #define RMT_APB_MEM_RD_ERR_CH0_V 0x1 1004 #define RMT_APB_MEM_RD_ERR_CH0_S 31 1005 /* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[30] ;default: 1'b0 ; */ 1006 /*description: The apb write memory status bit for channel0 turns to 1007 high level when the apb write address exceeds the configuration range.*/ 1008 #define RMT_APB_MEM_WR_ERR_CH0 (BIT(30)) 1009 #define RMT_APB_MEM_WR_ERR_CH0_M ((RMT_APB_MEM_WR_ERR_CH0_V)<<(RMT_APB_MEM_WR_ERR_CH0_S)) 1010 #define RMT_APB_MEM_WR_ERR_CH0_V 0x1 1011 #define RMT_APB_MEM_WR_ERR_CH0_S 30 1012 /* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[29] ;default: 1'b0 ; */ 1013 /*description: The memory empty status bit for channel0. in acyclic mode, 1014 this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ 1015 #define RMT_MEM_EMPTY_CH0 (BIT(29)) 1016 #define RMT_MEM_EMPTY_CH0_M ((RMT_MEM_EMPTY_CH0_V)<<(RMT_MEM_EMPTY_CH0_S)) 1017 #define RMT_MEM_EMPTY_CH0_V 0x1 1018 #define RMT_MEM_EMPTY_CH0_S 29 1019 /* RMT_MEM_FULL_CH0 : RO ;bitpos:[28] ;default: 1'b0 ; */ 1020 /*description: The memory full status bit for channel0 turns to high level 1021 when mem_waddr_ex is greater than or equal to the configuration range.*/ 1022 #define RMT_MEM_FULL_CH0 (BIT(28)) 1023 #define RMT_MEM_FULL_CH0_M ((RMT_MEM_FULL_CH0_V)<<(RMT_MEM_FULL_CH0_S)) 1024 #define RMT_MEM_FULL_CH0_V 0x1 1025 #define RMT_MEM_FULL_CH0_S 28 1026 /* RMT_MEM_OWNER_ERR_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */ 1027 /*description: When channel0 is configured for receive mode, this bit will turn to high level 1028 if rmt_mem_owner register is not set to 1.*/ 1029 #define RMT_MEM_OWNER_ERR_CH0 (BIT(27)) 1030 #define RMT_MEM_OWNER_ERR_CH0_M ((RMT_MEM_OWNER_ERR_CH0_V)<<(RMT_MEM_OWNER_ERR_CH0_S)) 1031 #define RMT_MEM_OWNER_ERR_CH0_V 0x1 1032 #define RMT_MEM_OWNER_ERR_CH0_S 27 1033 /* RMT_STATE_CH0 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ 1034 /*description: The channel0 state machine status register. 1035 3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ 1036 #define RMT_STATE_CH0 0x07000000 1037 #define RMT_STATE_CH0_M ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S)) 1038 #define RMT_STATE_CH0_V 0x7 1039 #define RMT_STATE_CH0_S 24 1040 /* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ 1041 /*description: The current memory write address of channel0.*/ 1042 #define RMT_MEM_RADDR_EX_CH0 0x003ff000 1043 #define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S)) 1044 #define RMT_MEM_RADDR_EX_CH0_V 0x3ff 1045 #define RMT_MEM_RADDR_EX_CH0_S 12 1046 /* RMT_MEM_WADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 1047 /*description: The current memory read address of channel0.*/ 1048 #define RMT_MEM_WADDR_EX_CH0 0x000003ff 1049 #define RMT_MEM_WADDR_EX_CH0_M ((RMT_MEM_WADDR_EX_CH0_V)<<(RMT_MEM_WADDR_EX_CH0_S)) 1050 #define RMT_MEM_WADDR_EX_CH0_V 0x3ff 1051 #define RMT_MEM_WADDR_EX_CH0_S 0 1052 1053 #define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064) 1054 /* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1055 /*description: The status for channel1*/ 1056 #define RMT_STATUS_CH1 0xFFFFFFFF 1057 #define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S)) 1058 #define RMT_STATUS_CH1_V 0xFFFFFFFF 1059 #define RMT_STATUS_CH1_S 0 1060 /* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[31] ;default: 1'b0 ; */ 1061 /*description: The apb read memory status bit for channel1 turns to 1062 high level when the apb read address exceeds the configuration range.*/ 1063 #define RMT_APB_MEM_RD_ERR_CH1 (BIT(31)) 1064 #define RMT_APB_MEM_RD_ERR_CH1_M ((RMT_APB_MEM_RD_ERR_CH1_V)<<(RMT_APB_MEM_RD_ERR_CH1_S)) 1065 #define RMT_APB_MEM_RD_ERR_CH1_V 0x1 1066 #define RMT_APB_MEM_RD_ERR_CH1_S 31 1067 /* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[30] ;default: 1'b0 ; */ 1068 /*description: The apb write memory status bit for channel1 turns to 1069 high level when the apb write address exceeds the configuration range.*/ 1070 #define RMT_APB_MEM_WR_ERR_CH1 (BIT(30)) 1071 #define RMT_APB_MEM_WR_ERR_CH1_M ((RMT_APB_MEM_WR_ERR_CH1_V)<<(RMT_APB_MEM_WR_ERR_CH1_S)) 1072 #define RMT_APB_MEM_WR_ERR_CH1_V 0x1 1073 #define RMT_APB_MEM_WR_ERR_CH1_S 30 1074 /* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[29] ;default: 1'b0 ; */ 1075 /*description: The memory empty status bit for channel1. in acyclic mode, 1076 this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ 1077 #define RMT_MEM_EMPTY_CH1 (BIT(29)) 1078 #define RMT_MEM_EMPTY_CH1_M ((RMT_MEM_EMPTY_CH1_V)<<(RMT_MEM_EMPTY_CH1_S)) 1079 #define RMT_MEM_EMPTY_CH1_V 0x1 1080 #define RMT_MEM_EMPTY_CH1_S 29 1081 /* RMT_MEM_FULL_CH1 : RO ;bitpos:[28] ;default: 1'b0 ; */ 1082 /*description: The memory full status bit for channel1 turns to high level 1083 when mem_waddr_ex is greater than or equal to the configuration range.*/ 1084 #define RMT_MEM_FULL_CH1 (BIT(28)) 1085 #define RMT_MEM_FULL_CH1_M ((RMT_MEM_FULL_CH1_V)<<(RMT_MEM_FULL_CH1_S)) 1086 #define RMT_MEM_FULL_CH1_V 0x1 1087 #define RMT_MEM_FULL_CH1_S 28 1088 /* RMT_MEM_OWNER_ERR_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */ 1089 /*description: When channel1 is configured for receive mode, this bit will turn to high level 1090 if rmt_mem_owner register is not set to 1.*/ 1091 #define RMT_MEM_OWNER_ERR_CH1 (BIT(27)) 1092 #define RMT_MEM_OWNER_ERR_CH1_M ((RMT_MEM_OWNER_ERR_CH1_V)<<(RMT_MEM_OWNER_ERR_CH1_S)) 1093 #define RMT_MEM_OWNER_ERR_CH1_V 0x1 1094 #define RMT_MEM_OWNER_ERR_CH1_S 27 1095 /* RMT_STATE_CH1 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ 1096 /*description: The channel1 state machine status register. 1097 3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ 1098 #define RMT_STATE_CH1 0x07000000 1099 #define RMT_STATE_CH1_M ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S)) 1100 #define RMT_STATE_CH1_V 0x7 1101 #define RMT_STATE_CH1_S 24 1102 /* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ 1103 /*description: The current memory write address of channel1.*/ 1104 #define RMT_MEM_RADDR_EX_CH1 0x003ff000 1105 #define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S)) 1106 #define RMT_MEM_RADDR_EX_CH1_V 0x3ff 1107 #define RMT_MEM_RADDR_EX_CH1_S 12 1108 /* RMT_MEM_WADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 1109 /*description: The current memory read address of channel1.*/ 1110 #define RMT_MEM_WADDR_EX_CH1 0x000003ff 1111 #define RMT_MEM_WADDR_EX_CH1_M ((RMT_MEM_WADDR_EX_CH1_V)<<(RMT_MEM_WADDR_EX_CH1_S)) 1112 #define RMT_MEM_WADDR_EX_CH1_V 0x3ff 1113 #define RMT_MEM_WADDR_EX_CH1_S 0 1114 1115 #define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068) 1116 /* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1117 /*description: The status for channel2*/ 1118 #define RMT_STATUS_CH2 0xFFFFFFFF 1119 #define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S)) 1120 #define RMT_STATUS_CH2_V 0xFFFFFFFF 1121 #define RMT_STATUS_CH2_S 0 1122 /* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[31] ;default: 1'b0 ; */ 1123 /*description: The apb read memory status bit for channel2 turns to 1124 high level when the apb read address exceeds the configuration range.*/ 1125 #define RMT_APB_MEM_RD_ERR_CH2 (BIT(31)) 1126 #define RMT_APB_MEM_RD_ERR_CH2_M ((RMT_APB_MEM_RD_ERR_CH2_V)<<(RMT_APB_MEM_RD_ERR_CH2_S)) 1127 #define RMT_APB_MEM_RD_ERR_CH2_V 0x1 1128 #define RMT_APB_MEM_RD_ERR_CH2_S 31 1129 /* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[30] ;default: 1'b0 ; */ 1130 /*description: The apb write memory status bit for channel2 turns to 1131 high level when the apb write address exceeds the configuration range.*/ 1132 #define RMT_APB_MEM_WR_ERR_CH2 (BIT(30)) 1133 #define RMT_APB_MEM_WR_ERR_CH2_M ((RMT_APB_MEM_WR_ERR_CH2_V)<<(RMT_APB_MEM_WR_ERR_CH2_S)) 1134 #define RMT_APB_MEM_WR_ERR_CH2_V 0x1 1135 #define RMT_APB_MEM_WR_ERR_CH2_S 30 1136 /* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[29] ;default: 1'b0 ; */ 1137 /*description: The memory empty status bit for channel2. in acyclic mode, 1138 this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ 1139 #define RMT_MEM_EMPTY_CH2 (BIT(29)) 1140 #define RMT_MEM_EMPTY_CH2_M ((RMT_MEM_EMPTY_CH2_V)<<(RMT_MEM_EMPTY_CH2_S)) 1141 #define RMT_MEM_EMPTY_CH2_V 0x1 1142 #define RMT_MEM_EMPTY_CH2_S 29 1143 /* RMT_MEM_FULL_CH2 : RO ;bitpos:[28] ;default: 1'b0 ; */ 1144 /*description: The memory full status bit for channel2 turns to high level 1145 when mem_waddr_ex is greater than or equal to the configuration range.*/ 1146 #define RMT_MEM_FULL_CH2 (BIT(28)) 1147 #define RMT_MEM_FULL_CH2_M ((RMT_MEM_FULL_CH2_V)<<(RMT_MEM_FULL_CH2_S)) 1148 #define RMT_MEM_FULL_CH2_V 0x1 1149 #define RMT_MEM_FULL_CH2_S 28 1150 /* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */ 1151 /*description: When channel2 is configured for receive mode, this bit will turn to high level 1152 if rmt_mem_owner register is not set to 1.*/ 1153 #define RMT_MEM_OWNER_ERR_CH2 (BIT(27)) 1154 #define RMT_MEM_OWNER_ERR_CH2_M ((RMT_MEM_OWNER_ERR_CH2_V)<<(RMT_MEM_OWNER_ERR_CH2_S)) 1155 #define RMT_MEM_OWNER_ERR_CH2_V 0x1 1156 #define RMT_MEM_OWNER_ERR_CH2_S 27 1157 /* RMT_STATE_CH2 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ 1158 /*description: The channel2 state machine status register. 1159 3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ 1160 #define RMT_STATE_CH2 0x07000000 1161 #define RMT_STATE_CH2_M ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S)) 1162 #define RMT_STATE_CH2_V 0x7 1163 #define RMT_STATE_CH2_S 24 1164 /* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ 1165 /*description: The current memory write address of channel2.*/ 1166 #define RMT_MEM_RADDR_EX_CH2 0x003ff000 1167 #define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S)) 1168 #define RMT_MEM_RADDR_EX_CH2_V 0x3ff 1169 #define RMT_MEM_RADDR_EX_CH2_S 12 1170 /* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 1171 /*description: The current memory read address of channel2.*/ 1172 #define RMT_MEM_WADDR_EX_CH2 0x000003ff 1173 #define RMT_MEM_WADDR_EX_CH2_M ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S)) 1174 #define RMT_MEM_WADDR_EX_CH2_V 0x3ff 1175 #define RMT_MEM_WADDR_EX_CH2_S 0 1176 1177 #define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c) 1178 /* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1179 /*description: The status for channel3*/ 1180 #define RMT_STATUS_CH3 0xFFFFFFFF 1181 #define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S)) 1182 #define RMT_STATUS_CH3_V 0xFFFFFFFF 1183 #define RMT_STATUS_CH3_S 0 1184 /* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[31] ;default: 1'b0 ; */ 1185 /*description: The apb read memory status bit for channel3 turns to 1186 high level when the apb read address exceeds the configuration range.*/ 1187 #define RMT_APB_MEM_RD_ERR_CH3 (BIT(31)) 1188 #define RMT_APB_MEM_RD_ERR_CH3_M ((RMT_APB_MEM_RD_ERR_CH3_V)<<(RMT_APB_MEM_RD_ERR_CH3_S)) 1189 #define RMT_APB_MEM_RD_ERR_CH3_V 0x1 1190 #define RMT_APB_MEM_RD_ERR_CH3_S 31 1191 /* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[30] ;default: 1'b0 ; */ 1192 /*description: The apb write memory status bit for channel3 turns to 1193 high level when the apb write address exceeds the configuration range.*/ 1194 #define RMT_APB_MEM_WR_ERR_CH3 (BIT(30)) 1195 #define RMT_APB_MEM_WR_ERR_CH3_M ((RMT_APB_MEM_WR_ERR_CH3_V)<<(RMT_APB_MEM_WR_ERR_CH3_S)) 1196 #define RMT_APB_MEM_WR_ERR_CH3_V 0x1 1197 #define RMT_APB_MEM_WR_ERR_CH3_S 30 1198 /* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[29] ;default: 1'b0 ; */ 1199 /*description: The memory empty status bit for channel3. in acyclic mode, 1200 this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ 1201 #define RMT_MEM_EMPTY_CH3 (BIT(29)) 1202 #define RMT_MEM_EMPTY_CH3_M ((RMT_MEM_EMPTY_CH3_V)<<(RMT_MEM_EMPTY_CH3_S)) 1203 #define RMT_MEM_EMPTY_CH3_V 0x1 1204 #define RMT_MEM_EMPTY_CH3_S 29 1205 /* RMT_MEM_FULL_CH3 : RO ;bitpos:[28] ;default: 1'b0 ; */ 1206 /*description: The memory full status bit for channel3 turns to high level 1207 when mem_waddr_ex is greater than or equal to the configuration range.*/ 1208 #define RMT_MEM_FULL_CH3 (BIT(28)) 1209 #define RMT_MEM_FULL_CH3_M ((RMT_MEM_FULL_CH3_V)<<(RMT_MEM_FULL_CH3_S)) 1210 #define RMT_MEM_FULL_CH3_V 0x1 1211 #define RMT_MEM_FULL_CH3_S 28 1212 /* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */ 1213 /*description: When channel3 is configured for receive mode, this bit will turn to high level 1214 if rmt_mem_owner register is not set to 1.*/ 1215 #define RMT_MEM_OWNER_ERR_CH3 (BIT(27)) 1216 #define RMT_MEM_OWNER_ERR_CH3_M ((RMT_MEM_OWNER_ERR_CH3_V)<<(RMT_MEM_OWNER_ERR_CH3_S)) 1217 #define RMT_MEM_OWNER_ERR_CH3_V 0x1 1218 #define RMT_MEM_OWNER_ERR_CH3_S 27 1219 /* RMT_STATE_CH3 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ 1220 /*description: The channel3 state machine status register. 1221 3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ 1222 #define RMT_STATE_CH3 0x07000000 1223 #define RMT_STATE_CH3_M ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S)) 1224 #define RMT_STATE_CH3_V 0x7 1225 #define RMT_STATE_CH3_S 24 1226 /* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ 1227 /*description: The current memory write address of channel3.*/ 1228 #define RMT_MEM_RADDR_EX_CH3 0x003ff000 1229 #define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S)) 1230 #define RMT_MEM_RADDR_EX_CH3_V 0x3ff 1231 #define RMT_MEM_RADDR_EX_CH3_S 12 1232 /* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 1233 /*description: The current memory read address of channel3.*/ 1234 #define RMT_MEM_WADDR_EX_CH3 0x000003ff 1235 #define RMT_MEM_WADDR_EX_CH3_M ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S)) 1236 #define RMT_MEM_WADDR_EX_CH3_V 0x3ff 1237 #define RMT_MEM_WADDR_EX_CH3_S 0 1238 1239 #define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070) 1240 /* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1241 /*description: The status for channel4*/ 1242 #define RMT_STATUS_CH4 0xFFFFFFFF 1243 #define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S)) 1244 #define RMT_STATUS_CH4_V 0xFFFFFFFF 1245 #define RMT_STATUS_CH4_S 0 1246 /* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[31] ;default: 1'b0 ; */ 1247 /*description: The apb read memory status bit for channel4 turns to 1248 high level when the apb read address exceeds the configuration range.*/ 1249 #define RMT_APB_MEM_RD_ERR_CH4 (BIT(31)) 1250 #define RMT_APB_MEM_RD_ERR_CH4_M ((RMT_APB_MEM_RD_ERR_CH4_V)<<(RMT_APB_MEM_RD_ERR_CH4_S)) 1251 #define RMT_APB_MEM_RD_ERR_CH4_V 0x1 1252 #define RMT_APB_MEM_RD_ERR_CH4_S 31 1253 /* RMT_APB_MEM_WR_ERR_CH4 : RO ;bitpos:[30] ;default: 1'b0 ; */ 1254 /*description: The apb write memory status bit for channel4 turns to 1255 high level when the apb write address exceeds the configuration range.*/ 1256 #define RMT_APB_MEM_WR_ERR_CH4 (BIT(30)) 1257 #define RMT_APB_MEM_WR_ERR_CH4_M ((RMT_APB_MEM_WR_ERR_CH4_V)<<(RMT_APB_MEM_WR_ERR_CH4_S)) 1258 #define RMT_APB_MEM_WR_ERR_CH4_V 0x1 1259 #define RMT_APB_MEM_WR_ERR_CH4_S 30 1260 /* RMT_MEM_EMPTY_CH4 : RO ;bitpos:[29] ;default: 1'b0 ; */ 1261 /*description: The memory empty status bit for channel4. in acyclic mode, 1262 this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ 1263 #define RMT_MEM_EMPTY_CH4 (BIT(29)) 1264 #define RMT_MEM_EMPTY_CH4_M ((RMT_MEM_EMPTY_CH4_V)<<(RMT_MEM_EMPTY_CH4_S)) 1265 #define RMT_MEM_EMPTY_CH4_V 0x1 1266 #define RMT_MEM_EMPTY_CH4_S 29 1267 /* RMT_MEM_FULL_CH4 : RO ;bitpos:[28] ;default: 1'b0 ; */ 1268 /*description: The memory full status bit for channel4 turns to high level 1269 when mem_waddr_ex is greater than or equal to the configuration range.*/ 1270 #define RMT_MEM_FULL_CH4 (BIT(28)) 1271 #define RMT_MEM_FULL_CH4_M ((RMT_MEM_FULL_CH4_V)<<(RMT_MEM_FULL_CH4_S)) 1272 #define RMT_MEM_FULL_CH4_V 0x1 1273 #define RMT_MEM_FULL_CH4_S 28 1274 /* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */ 1275 /*description: When channel4 is configured for receive mode, this bit will turn to high level 1276 if rmt_mem_owner register is not set to 1.*/ 1277 #define RMT_MEM_OWNER_ERR_CH4 (BIT(27)) 1278 #define RMT_MEM_OWNER_ERR_CH4_M ((RMT_MEM_OWNER_ERR_CH4_V)<<(RMT_MEM_OWNER_ERR_CH4_S)) 1279 #define RMT_MEM_OWNER_ERR_CH4_V 0x1 1280 #define RMT_MEM_OWNER_ERR_CH4_S 27 1281 /* RMT_STATE_CH4 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ 1282 /*description: The channel4 state machine status register. 1283 3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ 1284 #define RMT_STATE_CH4 0x07000000 1285 #define RMT_STATE_CH4_M ((RMT_STATE_CH4_V)<<(RMT_STATE_CH4_S)) 1286 #define RMT_STATE_CH4_V 0x7 1287 #define RMT_STATE_CH4_S 24 1288 /* RMT_MEM_RADDR_EX_CH4 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ 1289 /*description: The current memory write address of channel4.*/ 1290 #define RMT_MEM_RADDR_EX_CH4 0x003ff000 1291 #define RMT_MEM_RADDR_EX_CH4_M ((RMT_MEM_RADDR_EX_CH4_V)<<(RMT_MEM_RADDR_EX_CH4_S)) 1292 #define RMT_MEM_RADDR_EX_CH4_V 0x3ff 1293 #define RMT_MEM_RADDR_EX_CH4_S 12 1294 /* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 1295 /*description: The current memory read address of channel4.*/ 1296 #define RMT_MEM_WADDR_EX_CH4 0x000003ff 1297 #define RMT_MEM_WADDR_EX_CH4_M ((RMT_MEM_WADDR_EX_CH4_V)<<(RMT_MEM_WADDR_EX_CH4_S)) 1298 #define RMT_MEM_WADDR_EX_CH4_V 0x3ff 1299 #define RMT_MEM_WADDR_EX_CH4_S 0 1300 1301 #define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074) 1302 /* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1303 /*description: The status for channel5*/ 1304 #define RMT_STATUS_CH5 0xFFFFFFFF 1305 #define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S)) 1306 #define RMT_STATUS_CH5_V 0xFFFFFFFF 1307 #define RMT_STATUS_CH5_S 0 1308 /* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[31] ;default: 1'b0 ; */ 1309 /*description: The apb read memory status bit for channel5 turns to 1310 high level when the apb read address exceeds the configuration range.*/ 1311 #define RMT_APB_MEM_RD_ERR_CH5 (BIT(31)) 1312 #define RMT_APB_MEM_RD_ERR_CH5_M ((RMT_APB_MEM_RD_ERR_CH5_V)<<(RMT_APB_MEM_RD_ERR_CH5_S)) 1313 #define RMT_APB_MEM_RD_ERR_CH5_V 0x1 1314 #define RMT_APB_MEM_RD_ERR_CH5_S 31 1315 /* RMT_APB_MEM_WR_ERR_CH5 : RO ;bitpos:[30] ;default: 1'b0 ; */ 1316 /*description: The apb write memory status bit for channel5 turns to 1317 high level when the apb write address exceeds the configuration range.*/ 1318 #define RMT_APB_MEM_WR_ERR_CH5 (BIT(30)) 1319 #define RMT_APB_MEM_WR_ERR_CH5_M ((RMT_APB_MEM_WR_ERR_CH5_V)<<(RMT_APB_MEM_WR_ERR_CH5_S)) 1320 #define RMT_APB_MEM_WR_ERR_CH5_V 0x1 1321 #define RMT_APB_MEM_WR_ERR_CH5_S 30 1322 /* RMT_MEM_EMPTY_CH5 : RO ;bitpos:[29] ;default: 1'b0 ; */ 1323 /*description: The memory empty status bit for channel5. in acyclic mode, 1324 this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ 1325 #define RMT_MEM_EMPTY_CH5 (BIT(29)) 1326 #define RMT_MEM_EMPTY_CH5_M ((RMT_MEM_EMPTY_CH5_V)<<(RMT_MEM_EMPTY_CH5_S)) 1327 #define RMT_MEM_EMPTY_CH5_V 0x1 1328 #define RMT_MEM_EMPTY_CH5_S 29 1329 /* RMT_MEM_FULL_CH5 : RO ;bitpos:[28] ;default: 1'b0 ; */ 1330 /*description: The memory full status bit for channel5 turns to high level 1331 when mem_waddr_ex is greater than or equal to the configuration range.*/ 1332 #define RMT_MEM_FULL_CH5 (BIT(28)) 1333 #define RMT_MEM_FULL_CH5_M ((RMT_MEM_FULL_CH5_V)<<(RMT_MEM_FULL_CH5_S)) 1334 #define RMT_MEM_FULL_CH5_V 0x1 1335 #define RMT_MEM_FULL_CH5_S 28 1336 /* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */ 1337 /*description: When channel5 is configured for receive mode, this bit will turn to high level 1338 if rmt_mem_owner register is not set to 1.*/ 1339 #define RMT_MEM_OWNER_ERR_CH5 (BIT(27)) 1340 #define RMT_MEM_OWNER_ERR_CH5_M ((RMT_MEM_OWNER_ERR_CH5_V)<<(RMT_MEM_OWNER_ERR_CH5_S)) 1341 #define RMT_MEM_OWNER_ERR_CH5_V 0x1 1342 #define RMT_MEM_OWNER_ERR_CH5_S 27 1343 /* RMT_STATE_CH5 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ 1344 /*description: The channel5 state machine status register. 1345 3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ 1346 #define RMT_STATE_CH5 0x07000000 1347 #define RMT_STATE_CH5_M ((RMT_STATE_CH5_V)<<(RMT_STATE_CH5_S)) 1348 #define RMT_STATE_CH5_V 0x7 1349 #define RMT_STATE_CH5_S 24 1350 /* RMT_MEM_RADDR_EX_CH5 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ 1351 /*description: The current memory write address of channel5.*/ 1352 #define RMT_MEM_RADDR_EX_CH5 0x003ff000 1353 #define RMT_MEM_RADDR_EX_CH5_M ((RMT_MEM_RADDR_EX_CH5_V)<<(RMT_MEM_RADDR_EX_CH5_S)) 1354 #define RMT_MEM_RADDR_EX_CH5_V 0x3ff 1355 #define RMT_MEM_RADDR_EX_CH5_S 12 1356 /* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 1357 /*description: The current memory read address of channel5.*/ 1358 #define RMT_MEM_WADDR_EX_CH5 0x000003ff 1359 #define RMT_MEM_WADDR_EX_CH5_M ((RMT_MEM_WADDR_EX_CH5_V)<<(RMT_MEM_WADDR_EX_CH5_S)) 1360 #define RMT_MEM_WADDR_EX_CH5_V 0x3ff 1361 #define RMT_MEM_WADDR_EX_CH5_S 0 1362 1363 #define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078) 1364 /* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1365 /*description: The status for channel6*/ 1366 #define RMT_STATUS_CH6 0xFFFFFFFF 1367 #define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S)) 1368 #define RMT_STATUS_CH6_V 0xFFFFFFFF 1369 #define RMT_STATUS_CH6_S 0 1370 /* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[31] ;default: 1'b0 ; */ 1371 /*description: The apb read memory status bit for channel6 turns to 1372 high level when the apb read address exceeds the configuration range.*/ 1373 #define RMT_APB_MEM_RD_ERR_CH6 (BIT(31)) 1374 #define RMT_APB_MEM_RD_ERR_CH6_M ((RMT_APB_MEM_RD_ERR_CH6_V)<<(RMT_APB_MEM_RD_ERR_CH6_S)) 1375 #define RMT_APB_MEM_RD_ERR_CH6_V 0x1 1376 #define RMT_APB_MEM_RD_ERR_CH6_S 31 1377 /* RMT_APB_MEM_WR_ERR_CH6 : RO ;bitpos:[30] ;default: 1'b0 ; */ 1378 /*description: The apb write memory status bit for channel6 turns to 1379 high level when the apb write address exceeds the configuration range.*/ 1380 #define RMT_APB_MEM_WR_ERR_CH6 (BIT(30)) 1381 #define RMT_APB_MEM_WR_ERR_CH6_M ((RMT_APB_MEM_WR_ERR_CH6_V)<<(RMT_APB_MEM_WR_ERR_CH6_S)) 1382 #define RMT_APB_MEM_WR_ERR_CH6_V 0x1 1383 #define RMT_APB_MEM_WR_ERR_CH6_S 30 1384 /* RMT_MEM_EMPTY_CH6 : RO ;bitpos:[29] ;default: 1'b0 ; */ 1385 /*description: The memory empty status bit for channel6. in acyclic mode, 1386 this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ 1387 #define RMT_MEM_EMPTY_CH6 (BIT(29)) 1388 #define RMT_MEM_EMPTY_CH6_M ((RMT_MEM_EMPTY_CH6_V)<<(RMT_MEM_EMPTY_CH6_S)) 1389 #define RMT_MEM_EMPTY_CH6_V 0x1 1390 #define RMT_MEM_EMPTY_CH6_S 29 1391 /* RMT_MEM_FULL_CH6 : RO ;bitpos:[28] ;default: 1'b0 ; */ 1392 /*description: The memory full status bit for channel6 turns to high level 1393 when mem_waddr_ex is greater than or equal to the configuration range.*/ 1394 #define RMT_MEM_FULL_CH6 (BIT(28)) 1395 #define RMT_MEM_FULL_CH6_M ((RMT_MEM_FULL_CH6_V)<<(RMT_MEM_FULL_CH6_S)) 1396 #define RMT_MEM_FULL_CH6_V 0x1 1397 #define RMT_MEM_FULL_CH6_S 28 1398 /* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */ 1399 /*description: When channel6 is configured for receive mode, this bit will turn to high level 1400 if rmt_mem_owner register is not set to 1.*/ 1401 #define RMT_MEM_OWNER_ERR_CH6 (BIT(27)) 1402 #define RMT_MEM_OWNER_ERR_CH6_M ((RMT_MEM_OWNER_ERR_CH6_V)<<(RMT_MEM_OWNER_ERR_CH6_S)) 1403 #define RMT_MEM_OWNER_ERR_CH6_V 0x1 1404 #define RMT_MEM_OWNER_ERR_CH6_S 27 1405 /* RMT_STATE_CH6 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ 1406 /*description: The channel6 state machine status register. 1407 3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ 1408 #define RMT_STATE_CH6 0x07000000 1409 #define RMT_STATE_CH6_M ((RMT_STATE_CH6_V)<<(RMT_STATE_CH6_S)) 1410 #define RMT_STATE_CH6_V 0x7 1411 #define RMT_STATE_CH6_S 24 1412 /* RMT_MEM_RADDR_EX_CH6 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ 1413 /*description: The current memory write address of channel6.*/ 1414 #define RMT_MEM_RADDR_EX_CH6 0x003ff000 1415 #define RMT_MEM_RADDR_EX_CH6_M ((RMT_MEM_RADDR_EX_CH6_V)<<(RMT_MEM_RADDR_EX_CH6_S)) 1416 #define RMT_MEM_RADDR_EX_CH6_V 0x3ff 1417 #define RMT_MEM_RADDR_EX_CH6_S 12 1418 /* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 1419 /*description: The current memory read address of channel6.*/ 1420 #define RMT_MEM_WADDR_EX_CH6 0x000003ff 1421 #define RMT_MEM_WADDR_EX_CH6_M ((RMT_MEM_WADDR_EX_CH6_V)<<(RMT_MEM_WADDR_EX_CH6_S)) 1422 #define RMT_MEM_WADDR_EX_CH6_V 0x3ff 1423 #define RMT_MEM_WADDR_EX_CH6_S 0 1424 1425 #define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c) 1426 /* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1427 /*description: The status for channel7*/ 1428 #define RMT_STATUS_CH7 0xFFFFFFFF 1429 #define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S)) 1430 #define RMT_STATUS_CH7_V 0xFFFFFFFF 1431 #define RMT_STATUS_CH7_S 0 1432 /* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[31] ;default: 1'b0 ; */ 1433 /*description: The apb read memory status bit for channel7 turns to 1434 high level when the apb read address exceeds the configuration range.*/ 1435 #define RMT_APB_MEM_RD_ERR_CH7 (BIT(31)) 1436 #define RMT_APB_MEM_RD_ERR_CH7_M ((RMT_APB_MEM_RD_ERR_CH7_V)<<(RMT_APB_MEM_RD_ERR_CH7_S)) 1437 #define RMT_APB_MEM_RD_ERR_CH7_V 0x1 1438 #define RMT_APB_MEM_RD_ERR_CH7_S 31 1439 /* RMT_APB_MEM_WR_ERR_CH7 : RO ;bitpos:[30] ;default: 1'b0 ; */ 1440 /*description: The apb write memory status bit for channel7 turns to 1441 high level when the apb write address exceeds the configuration range.*/ 1442 #define RMT_APB_MEM_WR_ERR_CH7 (BIT(30)) 1443 #define RMT_APB_MEM_WR_ERR_CH7_M ((RMT_APB_MEM_WR_ERR_CH7_V)<<(RMT_APB_MEM_WR_ERR_CH7_S)) 1444 #define RMT_APB_MEM_WR_ERR_CH7_V 0x1 1445 #define RMT_APB_MEM_WR_ERR_CH7_S 30 1446 /* RMT_MEM_EMPTY_CH7 : RO ;bitpos:[29] ;default: 1'b0 ; */ 1447 /*description: The memory empty status bit for channel7. in acyclic mode, 1448 this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/ 1449 #define RMT_MEM_EMPTY_CH7 (BIT(29)) 1450 #define RMT_MEM_EMPTY_CH7_M ((RMT_MEM_EMPTY_CH7_V)<<(RMT_MEM_EMPTY_CH7_S)) 1451 #define RMT_MEM_EMPTY_CH7_V 0x1 1452 #define RMT_MEM_EMPTY_CH7_S 29 1453 /* RMT_MEM_FULL_CH7 : RO ;bitpos:[28] ;default: 1'b0 ; */ 1454 /*description: The memory full status bit for channel7 turns to high level 1455 when mem_waddr_ex is greater than or equal to the configuration range.*/ 1456 #define RMT_MEM_FULL_CH7 (BIT(28)) 1457 #define RMT_MEM_FULL_CH7_M ((RMT_MEM_FULL_CH7_V)<<(RMT_MEM_FULL_CH7_S)) 1458 #define RMT_MEM_FULL_CH7_V 0x1 1459 #define RMT_MEM_FULL_CH7_S 28 1460 /* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */ 1461 /*description: When channel7 is configured for receive mode, this bit will turn to high level 1462 if rmt_mem_owner register is not set to 1.*/ 1463 #define RMT_MEM_OWNER_ERR_CH7 (BIT(27)) 1464 #define RMT_MEM_OWNER_ERR_CH7_M ((RMT_MEM_OWNER_ERR_CH7_V)<<(RMT_MEM_OWNER_ERR_CH7_S)) 1465 #define RMT_MEM_OWNER_ERR_CH7_V 0x1 1466 #define RMT_MEM_OWNER_ERR_CH7_S 27 1467 /* RMT_STATE_CH7 : RO ;bitpos:[26:24] ;default: 3'h0 ; */ 1468 /*description: The channel7 state machine status register. 1469 3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/ 1470 #define RMT_STATE_CH7 0x07000000 1471 #define RMT_STATE_CH7_M ((RMT_STATE_CH7_V)<<(RMT_STATE_CH7_S)) 1472 #define RMT_STATE_CH7_V 0x7 1473 #define RMT_STATE_CH7_S 24 1474 /* RMT_MEM_RADDR_EX_CH7 : RO ;bitpos:[21:12] ;default: 10'h0 ; */ 1475 /*description: The current memory write address of channel7.*/ 1476 #define RMT_MEM_RADDR_EX_CH7 0x003ff000 1477 #define RMT_MEM_RADDR_EX_CH7_M ((RMT_MEM_RADDR_EX_CH7_V)<<(RMT_MEM_RADDR_EX_CH7_S)) 1478 #define RMT_MEM_RADDR_EX_CH7_V 0x3ff 1479 #define RMT_MEM_RADDR_EX_CH7_S 12 1480 /* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 1481 /*description: The current memory read address of channel7.*/ 1482 #define RMT_MEM_WADDR_EX_CH7 0x000003ff 1483 #define RMT_MEM_WADDR_EX_CH7_M ((RMT_MEM_WADDR_EX_CH7_V)<<(RMT_MEM_WADDR_EX_CH7_S)) 1484 #define RMT_MEM_WADDR_EX_CH7_V 0x3ff 1485 #define RMT_MEM_WADDR_EX_CH7_S 0 1486 1487 #define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080) 1488 /* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1489 /*description: The ram relative address in channel0 by apb fifo access*/ 1490 #define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF 1491 #define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S)) 1492 #define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF 1493 #define RMT_APB_MEM_ADDR_CH0_S 0 1494 1495 #define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084) 1496 /* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1497 /*description: The ram relative address in channel1 by apb fifo access*/ 1498 #define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF 1499 #define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S)) 1500 #define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF 1501 #define RMT_APB_MEM_ADDR_CH1_S 0 1502 1503 #define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088) 1504 /* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1505 /*description: The ram relative address in channel2 by apb fifo access*/ 1506 #define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF 1507 #define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S)) 1508 #define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF 1509 #define RMT_APB_MEM_ADDR_CH2_S 0 1510 1511 #define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c) 1512 /* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1513 /*description: The ram relative address in channel3 by apb fifo access*/ 1514 #define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF 1515 #define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S)) 1516 #define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF 1517 #define RMT_APB_MEM_ADDR_CH3_S 0 1518 1519 #define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090) 1520 /* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1521 /*description: The ram relative address in channel4 by apb fifo access*/ 1522 #define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF 1523 #define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S)) 1524 #define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF 1525 #define RMT_APB_MEM_ADDR_CH4_S 0 1526 1527 #define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094) 1528 /* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1529 /*description: The ram relative address in channel5 by apb fifo access*/ 1530 #define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF 1531 #define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S)) 1532 #define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF 1533 #define RMT_APB_MEM_ADDR_CH5_S 0 1534 1535 #define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098) 1536 /* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1537 /*description: The ram relative address in channel6 by apb fifo access*/ 1538 #define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF 1539 #define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S)) 1540 #define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF 1541 #define RMT_APB_MEM_ADDR_CH6_S 0 1542 1543 #define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c) 1544 /* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1545 /*description: The ram relative address in channel7 by apb fifo access*/ 1546 #define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF 1547 #define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S)) 1548 #define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF 1549 #define RMT_APB_MEM_ADDR_CH7_S 0 1550 1551 #define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0) 1552 /* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ 1553 /*description: The interrupt raw bit for channel7 turns to high level when 1554 transmitter in channle 7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/ 1555 #define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31)) 1556 #define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31)) 1557 #define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1 1558 #define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31 1559 /* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ 1560 /*description: The interrupt raw bit for channel 6 turns to high level when 1561 transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/ 1562 #define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30)) 1563 #define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30)) 1564 #define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1 1565 #define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30 1566 /* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ 1567 /*description: The interrupt raw bit for channel 5 turns to high level when 1568 transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/ 1569 #define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29)) 1570 #define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29)) 1571 #define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1 1572 #define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29 1573 /* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ 1574 /*description: The interrupt raw bit for channel 4 turns to high level when 1575 transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/ 1576 #define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28)) 1577 #define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28)) 1578 #define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1 1579 #define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28 1580 /* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ 1581 /*description: The interrupt raw bit for channel 3 turns to high level when 1582 transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/ 1583 #define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27)) 1584 #define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27)) 1585 #define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 1586 #define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27 1587 /* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ 1588 /*description: The interrupt raw bit for channel 2 turns to high level when 1589 transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/ 1590 #define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26)) 1591 #define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26)) 1592 #define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 1593 #define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26 1594 /* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ 1595 /*description: The interrupt raw bit for channel 1 turns to high level when 1596 transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/ 1597 #define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25)) 1598 #define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25)) 1599 #define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 1600 #define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25 1601 /* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ 1602 /*description: The interrupt raw bit for channel 0 turns to high level when 1603 transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/ 1604 #define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24)) 1605 #define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24)) 1606 #define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 1607 #define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24 1608 /* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ 1609 /*description: The interrupt raw bit for channel 7 turns to high level when 1610 channle 7 detects some errors.*/ 1611 #define RMT_CH7_ERR_INT_RAW (BIT(23)) 1612 #define RMT_CH7_ERR_INT_RAW_M (BIT(23)) 1613 #define RMT_CH7_ERR_INT_RAW_V 0x1 1614 #define RMT_CH7_ERR_INT_RAW_S 23 1615 /* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ 1616 /*description: The interrupt raw bit for channel 7 turns to high level when 1617 the receive process is done.*/ 1618 #define RMT_CH7_RX_END_INT_RAW (BIT(22)) 1619 #define RMT_CH7_RX_END_INT_RAW_M (BIT(22)) 1620 #define RMT_CH7_RX_END_INT_RAW_V 0x1 1621 #define RMT_CH7_RX_END_INT_RAW_S 22 1622 /* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ 1623 /*description: The interrupt raw bit for channel 7 turns to high level when 1624 the transmit process is done.*/ 1625 #define RMT_CH7_TX_END_INT_RAW (BIT(21)) 1626 #define RMT_CH7_TX_END_INT_RAW_M (BIT(21)) 1627 #define RMT_CH7_TX_END_INT_RAW_V 0x1 1628 #define RMT_CH7_TX_END_INT_RAW_S 21 1629 /* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ 1630 /*description: The interrupt raw bit for channel 6 turns to high level when 1631 channle 6 detects some errors.*/ 1632 #define RMT_CH6_ERR_INT_RAW (BIT(20)) 1633 #define RMT_CH6_ERR_INT_RAW_M (BIT(20)) 1634 #define RMT_CH6_ERR_INT_RAW_V 0x1 1635 #define RMT_CH6_ERR_INT_RAW_S 20 1636 /* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ 1637 /*description: The interrupt raw bit for channel 6 turns to high level when 1638 the receive process is done.*/ 1639 #define RMT_CH6_RX_END_INT_RAW (BIT(19)) 1640 #define RMT_CH6_RX_END_INT_RAW_M (BIT(19)) 1641 #define RMT_CH6_RX_END_INT_RAW_V 0x1 1642 #define RMT_CH6_RX_END_INT_RAW_S 19 1643 /* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ 1644 /*description: The interrupt raw bit for channel 6 turns to high level when 1645 the transmit process is done.*/ 1646 #define RMT_CH6_TX_END_INT_RAW (BIT(18)) 1647 #define RMT_CH6_TX_END_INT_RAW_M (BIT(18)) 1648 #define RMT_CH6_TX_END_INT_RAW_V 0x1 1649 #define RMT_CH6_TX_END_INT_RAW_S 18 1650 /* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ 1651 /*description: The interrupt raw bit for channel 5 turns to high level when 1652 channle 5 detects some errors.*/ 1653 #define RMT_CH5_ERR_INT_RAW (BIT(17)) 1654 #define RMT_CH5_ERR_INT_RAW_M (BIT(17)) 1655 #define RMT_CH5_ERR_INT_RAW_V 0x1 1656 #define RMT_CH5_ERR_INT_RAW_S 17 1657 /* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 1658 /*description: The interrupt raw bit for channel 5 turns to high level when 1659 the receive process is done.*/ 1660 #define RMT_CH5_RX_END_INT_RAW (BIT(16)) 1661 #define RMT_CH5_RX_END_INT_RAW_M (BIT(16)) 1662 #define RMT_CH5_RX_END_INT_RAW_V 0x1 1663 #define RMT_CH5_RX_END_INT_RAW_S 16 1664 /* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 1665 /*description: The interrupt raw bit for channel 5 turns to high level when 1666 the transmit process is done.*/ 1667 #define RMT_CH5_TX_END_INT_RAW (BIT(15)) 1668 #define RMT_CH5_TX_END_INT_RAW_M (BIT(15)) 1669 #define RMT_CH5_TX_END_INT_RAW_V 0x1 1670 #define RMT_CH5_TX_END_INT_RAW_S 15 1671 /* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ 1672 /*description: The interrupt raw bit for channel 4 turns to high level when 1673 channle 4 detects some errors.*/ 1674 #define RMT_CH4_ERR_INT_RAW (BIT(14)) 1675 #define RMT_CH4_ERR_INT_RAW_M (BIT(14)) 1676 #define RMT_CH4_ERR_INT_RAW_V 0x1 1677 #define RMT_CH4_ERR_INT_RAW_S 14 1678 /* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ 1679 /*description: The interrupt raw bit for channel 4 turns to high level when 1680 the receive process is done.*/ 1681 #define RMT_CH4_RX_END_INT_RAW (BIT(13)) 1682 #define RMT_CH4_RX_END_INT_RAW_M (BIT(13)) 1683 #define RMT_CH4_RX_END_INT_RAW_V 0x1 1684 #define RMT_CH4_RX_END_INT_RAW_S 13 1685 /* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ 1686 /*description: The interrupt raw bit for channel 4 turns to high level when 1687 the transmit process is done.*/ 1688 #define RMT_CH4_TX_END_INT_RAW (BIT(12)) 1689 #define RMT_CH4_TX_END_INT_RAW_M (BIT(12)) 1690 #define RMT_CH4_TX_END_INT_RAW_V 0x1 1691 #define RMT_CH4_TX_END_INT_RAW_S 12 1692 /* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 1693 /*description: The interrupt raw bit for channel 3 turns to high level when 1694 channle 3 detects some errors.*/ 1695 #define RMT_CH3_ERR_INT_RAW (BIT(11)) 1696 #define RMT_CH3_ERR_INT_RAW_M (BIT(11)) 1697 #define RMT_CH3_ERR_INT_RAW_V 0x1 1698 #define RMT_CH3_ERR_INT_RAW_S 11 1699 /* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 1700 /*description: The interrupt raw bit for channel 3 turns to high level when 1701 the receive process is done.*/ 1702 #define RMT_CH3_RX_END_INT_RAW (BIT(10)) 1703 #define RMT_CH3_RX_END_INT_RAW_M (BIT(10)) 1704 #define RMT_CH3_RX_END_INT_RAW_V 0x1 1705 #define RMT_CH3_RX_END_INT_RAW_S 10 1706 /* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 1707 /*description: The interrupt raw bit for channel 3 turns to high level when 1708 the transmit process is done.*/ 1709 #define RMT_CH3_TX_END_INT_RAW (BIT(9)) 1710 #define RMT_CH3_TX_END_INT_RAW_M (BIT(9)) 1711 #define RMT_CH3_TX_END_INT_RAW_V 0x1 1712 #define RMT_CH3_TX_END_INT_RAW_S 9 1713 /* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 1714 /*description: The interrupt raw bit for channel 2 turns to high level when 1715 channle 2 detects some errors.*/ 1716 #define RMT_CH2_ERR_INT_RAW (BIT(8)) 1717 #define RMT_CH2_ERR_INT_RAW_M (BIT(8)) 1718 #define RMT_CH2_ERR_INT_RAW_V 0x1 1719 #define RMT_CH2_ERR_INT_RAW_S 8 1720 /* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 1721 /*description: The interrupt raw bit for channel 2 turns to high level when 1722 the receive process is done.*/ 1723 #define RMT_CH2_RX_END_INT_RAW (BIT(7)) 1724 #define RMT_CH2_RX_END_INT_RAW_M (BIT(7)) 1725 #define RMT_CH2_RX_END_INT_RAW_V 0x1 1726 #define RMT_CH2_RX_END_INT_RAW_S 7 1727 /* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 1728 /*description: The interrupt raw bit for channel 2 turns to high level when 1729 the transmit process is done.*/ 1730 #define RMT_CH2_TX_END_INT_RAW (BIT(6)) 1731 #define RMT_CH2_TX_END_INT_RAW_M (BIT(6)) 1732 #define RMT_CH2_TX_END_INT_RAW_V 0x1 1733 #define RMT_CH2_TX_END_INT_RAW_S 6 1734 /* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 1735 /*description: The interrupt raw bit for channel 1 turns to high level when 1736 channle 1 detects some errors.*/ 1737 #define RMT_CH1_ERR_INT_RAW (BIT(5)) 1738 #define RMT_CH1_ERR_INT_RAW_M (BIT(5)) 1739 #define RMT_CH1_ERR_INT_RAW_V 0x1 1740 #define RMT_CH1_ERR_INT_RAW_S 5 1741 /* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 1742 /*description: The interrupt raw bit for channel 1 turns to high level when 1743 the receive process is done.*/ 1744 #define RMT_CH1_RX_END_INT_RAW (BIT(4)) 1745 #define RMT_CH1_RX_END_INT_RAW_M (BIT(4)) 1746 #define RMT_CH1_RX_END_INT_RAW_V 0x1 1747 #define RMT_CH1_RX_END_INT_RAW_S 4 1748 /* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 1749 /*description: The interrupt raw bit for channel 1 turns to high level when 1750 the transmit process is done.*/ 1751 #define RMT_CH1_TX_END_INT_RAW (BIT(3)) 1752 #define RMT_CH1_TX_END_INT_RAW_M (BIT(3)) 1753 #define RMT_CH1_TX_END_INT_RAW_V 0x1 1754 #define RMT_CH1_TX_END_INT_RAW_S 3 1755 /* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 1756 /*description: The interrupt raw bit for channel 0 turns to high level when 1757 channle 0 detects some errors.*/ 1758 #define RMT_CH0_ERR_INT_RAW (BIT(2)) 1759 #define RMT_CH0_ERR_INT_RAW_M (BIT(2)) 1760 #define RMT_CH0_ERR_INT_RAW_V 0x1 1761 #define RMT_CH0_ERR_INT_RAW_S 2 1762 /* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 1763 /*description: The interrupt raw bit for channel 0 turns to high level when 1764 the receive process is done.*/ 1765 #define RMT_CH0_RX_END_INT_RAW (BIT(1)) 1766 #define RMT_CH0_RX_END_INT_RAW_M (BIT(1)) 1767 #define RMT_CH0_RX_END_INT_RAW_V 0x1 1768 #define RMT_CH0_RX_END_INT_RAW_S 1 1769 /* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 1770 /*description: The interrupt raw bit for channel 0 turns to high level when 1771 the transmit process is done.*/ 1772 #define RMT_CH0_TX_END_INT_RAW (BIT(0)) 1773 #define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) 1774 #define RMT_CH0_TX_END_INT_RAW_V 0x1 1775 #define RMT_CH0_TX_END_INT_RAW_S 0 1776 1777 #define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4) 1778 /* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ 1779 /*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw 1780 when mt_ch7_tx_thr_event_int_ena is set to 1.*/ 1781 #define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31)) 1782 #define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31)) 1783 #define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1 1784 #define RMT_CH7_TX_THR_EVENT_INT_ST_S 31 1785 /* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ 1786 /*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw 1787 when mt_ch6_tx_thr_event_int_ena is set to 1.*/ 1788 #define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30)) 1789 #define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30)) 1790 #define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1 1791 #define RMT_CH6_TX_THR_EVENT_INT_ST_S 30 1792 /* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ 1793 /*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw 1794 when mt_ch5_tx_thr_event_int_ena is set to 1.*/ 1795 #define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29)) 1796 #define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29)) 1797 #define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1 1798 #define RMT_CH5_TX_THR_EVENT_INT_ST_S 29 1799 /* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ 1800 /*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw 1801 when mt_ch4_tx_thr_event_int_ena is set to 1.*/ 1802 #define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28)) 1803 #define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28)) 1804 #define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1 1805 #define RMT_CH4_TX_THR_EVENT_INT_ST_S 28 1806 /* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ 1807 /*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw 1808 when mt_ch3_tx_thr_event_int_ena is set to 1.*/ 1809 #define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27)) 1810 #define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27)) 1811 #define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 1812 #define RMT_CH3_TX_THR_EVENT_INT_ST_S 27 1813 /* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ 1814 /*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw 1815 when mt_ch2_tx_thr_event_int_ena is set to 1.*/ 1816 #define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26)) 1817 #define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26)) 1818 #define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 1819 #define RMT_CH2_TX_THR_EVENT_INT_ST_S 26 1820 /* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ 1821 /*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw 1822 when mt_ch1_tx_thr_event_int_ena is set to 1.*/ 1823 #define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25)) 1824 #define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25)) 1825 #define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 1826 #define RMT_CH1_TX_THR_EVENT_INT_ST_S 25 1827 /* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ 1828 /*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw 1829 when mt_ch0_tx_thr_event_int_ena is set to 1.*/ 1830 #define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24)) 1831 #define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24)) 1832 #define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 1833 #define RMT_CH0_TX_THR_EVENT_INT_ST_S 24 1834 /* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ 1835 /*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw 1836 when rmt_ch7_err_int_ena is set to 1.*/ 1837 #define RMT_CH7_ERR_INT_ST (BIT(23)) 1838 #define RMT_CH7_ERR_INT_ST_M (BIT(23)) 1839 #define RMT_CH7_ERR_INT_ST_V 0x1 1840 #define RMT_CH7_ERR_INT_ST_S 23 1841 /* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ 1842 /*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw 1843 when rmt_ch7_rx_end_int_ena is set to 1.*/ 1844 #define RMT_CH7_RX_END_INT_ST (BIT(22)) 1845 #define RMT_CH7_RX_END_INT_ST_M (BIT(22)) 1846 #define RMT_CH7_RX_END_INT_ST_V 0x1 1847 #define RMT_CH7_RX_END_INT_ST_S 22 1848 /* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ 1849 /*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw 1850 when mt_ch7_tx_end_int_ena is set to 1.*/ 1851 #define RMT_CH7_TX_END_INT_ST (BIT(21)) 1852 #define RMT_CH7_TX_END_INT_ST_M (BIT(21)) 1853 #define RMT_CH7_TX_END_INT_ST_V 0x1 1854 #define RMT_CH7_TX_END_INT_ST_S 21 1855 /* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ 1856 /*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw 1857 when rmt_ch6_err_int_ena is set to 1.*/ 1858 #define RMT_CH6_ERR_INT_ST (BIT(20)) 1859 #define RMT_CH6_ERR_INT_ST_M (BIT(20)) 1860 #define RMT_CH6_ERR_INT_ST_V 0x1 1861 #define RMT_CH6_ERR_INT_ST_S 20 1862 /* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ 1863 /*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw 1864 when rmt_ch6_rx_end_int_ena is set to 1.*/ 1865 #define RMT_CH6_RX_END_INT_ST (BIT(19)) 1866 #define RMT_CH6_RX_END_INT_ST_M (BIT(19)) 1867 #define RMT_CH6_RX_END_INT_ST_V 0x1 1868 #define RMT_CH6_RX_END_INT_ST_S 19 1869 /* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ 1870 /*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw 1871 when mt_ch6_tx_end_int_ena is set to 1.*/ 1872 #define RMT_CH6_TX_END_INT_ST (BIT(18)) 1873 #define RMT_CH6_TX_END_INT_ST_M (BIT(18)) 1874 #define RMT_CH6_TX_END_INT_ST_V 0x1 1875 #define RMT_CH6_TX_END_INT_ST_S 18 1876 /* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ 1877 /*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw 1878 when rmt_ch5_err_int_ena is set to 1.*/ 1879 #define RMT_CH5_ERR_INT_ST (BIT(17)) 1880 #define RMT_CH5_ERR_INT_ST_M (BIT(17)) 1881 #define RMT_CH5_ERR_INT_ST_V 0x1 1882 #define RMT_CH5_ERR_INT_ST_S 17 1883 /* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 1884 /*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw 1885 when rmt_ch5_rx_end_int_ena is set to 1.*/ 1886 #define RMT_CH5_RX_END_INT_ST (BIT(16)) 1887 #define RMT_CH5_RX_END_INT_ST_M (BIT(16)) 1888 #define RMT_CH5_RX_END_INT_ST_V 0x1 1889 #define RMT_CH5_RX_END_INT_ST_S 16 1890 /* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 1891 /*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw 1892 when mt_ch5_tx_end_int_ena is set to 1.*/ 1893 #define RMT_CH5_TX_END_INT_ST (BIT(15)) 1894 #define RMT_CH5_TX_END_INT_ST_M (BIT(15)) 1895 #define RMT_CH5_TX_END_INT_ST_V 0x1 1896 #define RMT_CH5_TX_END_INT_ST_S 15 1897 /* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ 1898 /*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw 1899 when rmt_ch4_err_int_ena is set to 1.*/ 1900 #define RMT_CH4_ERR_INT_ST (BIT(14)) 1901 #define RMT_CH4_ERR_INT_ST_M (BIT(14)) 1902 #define RMT_CH4_ERR_INT_ST_V 0x1 1903 #define RMT_CH4_ERR_INT_ST_S 14 1904 /* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ 1905 /*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw 1906 when rmt_ch4_rx_end_int_ena is set to 1.*/ 1907 #define RMT_CH4_RX_END_INT_ST (BIT(13)) 1908 #define RMT_CH4_RX_END_INT_ST_M (BIT(13)) 1909 #define RMT_CH4_RX_END_INT_ST_V 0x1 1910 #define RMT_CH4_RX_END_INT_ST_S 13 1911 /* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ 1912 /*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw 1913 when mt_ch4_tx_end_int_ena is set to 1.*/ 1914 #define RMT_CH4_TX_END_INT_ST (BIT(12)) 1915 #define RMT_CH4_TX_END_INT_ST_M (BIT(12)) 1916 #define RMT_CH4_TX_END_INT_ST_V 0x1 1917 #define RMT_CH4_TX_END_INT_ST_S 12 1918 /* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 1919 /*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw 1920 when rmt_ch3_err_int_ena is set to 1.*/ 1921 #define RMT_CH3_ERR_INT_ST (BIT(11)) 1922 #define RMT_CH3_ERR_INT_ST_M (BIT(11)) 1923 #define RMT_CH3_ERR_INT_ST_V 0x1 1924 #define RMT_CH3_ERR_INT_ST_S 11 1925 /* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 1926 /*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw 1927 when rmt_ch3_rx_end_int_ena is set to 1.*/ 1928 #define RMT_CH3_RX_END_INT_ST (BIT(10)) 1929 #define RMT_CH3_RX_END_INT_ST_M (BIT(10)) 1930 #define RMT_CH3_RX_END_INT_ST_V 0x1 1931 #define RMT_CH3_RX_END_INT_ST_S 10 1932 /* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 1933 /*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw 1934 when mt_ch3_tx_end_int_ena is set to 1.*/ 1935 #define RMT_CH3_TX_END_INT_ST (BIT(9)) 1936 #define RMT_CH3_TX_END_INT_ST_M (BIT(9)) 1937 #define RMT_CH3_TX_END_INT_ST_V 0x1 1938 #define RMT_CH3_TX_END_INT_ST_S 9 1939 /* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 1940 /*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw 1941 when rmt_ch2_err_int_ena is set to 1.*/ 1942 #define RMT_CH2_ERR_INT_ST (BIT(8)) 1943 #define RMT_CH2_ERR_INT_ST_M (BIT(8)) 1944 #define RMT_CH2_ERR_INT_ST_V 0x1 1945 #define RMT_CH2_ERR_INT_ST_S 8 1946 /* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 1947 /*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw 1948 when rmt_ch2_rx_end_int_ena is set to 1.*/ 1949 #define RMT_CH2_RX_END_INT_ST (BIT(7)) 1950 #define RMT_CH2_RX_END_INT_ST_M (BIT(7)) 1951 #define RMT_CH2_RX_END_INT_ST_V 0x1 1952 #define RMT_CH2_RX_END_INT_ST_S 7 1953 /* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 1954 /*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw 1955 when mt_ch2_tx_end_int_ena is set to 1.*/ 1956 #define RMT_CH2_TX_END_INT_ST (BIT(6)) 1957 #define RMT_CH2_TX_END_INT_ST_M (BIT(6)) 1958 #define RMT_CH2_TX_END_INT_ST_V 0x1 1959 #define RMT_CH2_TX_END_INT_ST_S 6 1960 /* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 1961 /*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw 1962 when rmt_ch1_err_int_ena is set to 1.*/ 1963 #define RMT_CH1_ERR_INT_ST (BIT(5)) 1964 #define RMT_CH1_ERR_INT_ST_M (BIT(5)) 1965 #define RMT_CH1_ERR_INT_ST_V 0x1 1966 #define RMT_CH1_ERR_INT_ST_S 5 1967 /* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 1968 /*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw 1969 when rmt_ch1_rx_end_int_ena is set to 1.*/ 1970 #define RMT_CH1_RX_END_INT_ST (BIT(4)) 1971 #define RMT_CH1_RX_END_INT_ST_M (BIT(4)) 1972 #define RMT_CH1_RX_END_INT_ST_V 0x1 1973 #define RMT_CH1_RX_END_INT_ST_S 4 1974 /* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1975 /*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw 1976 when mt_ch1_tx_end_int_ena is set to 1.*/ 1977 #define RMT_CH1_TX_END_INT_ST (BIT(3)) 1978 #define RMT_CH1_TX_END_INT_ST_M (BIT(3)) 1979 #define RMT_CH1_TX_END_INT_ST_V 0x1 1980 #define RMT_CH1_TX_END_INT_ST_S 3 1981 /* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 1982 /*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw 1983 when rmt_ch0_err_int_ena is set to 0.*/ 1984 #define RMT_CH0_ERR_INT_ST (BIT(2)) 1985 #define RMT_CH0_ERR_INT_ST_M (BIT(2)) 1986 #define RMT_CH0_ERR_INT_ST_V 0x1 1987 #define RMT_CH0_ERR_INT_ST_S 2 1988 /* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1989 /*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw 1990 when rmt_ch0_rx_end_int_ena is set to 0.*/ 1991 #define RMT_CH0_RX_END_INT_ST (BIT(1)) 1992 #define RMT_CH0_RX_END_INT_ST_M (BIT(1)) 1993 #define RMT_CH0_RX_END_INT_ST_V 0x1 1994 #define RMT_CH0_RX_END_INT_ST_S 1 1995 /* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1996 /*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw 1997 when mt_ch0_tx_end_int_ena is set to 0.*/ 1998 #define RMT_CH0_TX_END_INT_ST (BIT(0)) 1999 #define RMT_CH0_TX_END_INT_ST_M (BIT(0)) 2000 #define RMT_CH0_TX_END_INT_ST_V 0x1 2001 #define RMT_CH0_TX_END_INT_ST_S 0 2002 2003 #define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8) 2004 /* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2005 /*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ 2006 #define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31)) 2007 #define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31)) 2008 #define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1 2009 #define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31 2010 /* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2011 /*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ 2012 #define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30)) 2013 #define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30)) 2014 #define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1 2015 #define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30 2016 /* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ 2017 /*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ 2018 #define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29)) 2019 #define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29)) 2020 #define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1 2021 #define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29 2022 /* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ 2023 /*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ 2024 #define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28)) 2025 #define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28)) 2026 #define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1 2027 #define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28 2028 /* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ 2029 /*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ 2030 #define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27)) 2031 #define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27)) 2032 #define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 2033 #define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27 2034 /* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2035 /*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ 2036 #define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26)) 2037 #define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26)) 2038 #define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 2039 #define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26 2040 /* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ 2041 /*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ 2042 #define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25)) 2043 #define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25)) 2044 #define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 2045 #define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25 2046 /* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ 2047 /*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ 2048 #define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24)) 2049 #define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24)) 2050 #define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 2051 #define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24 2052 /* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ 2053 /*description: Set this bit to enable rmt_ch7_err_int_st.*/ 2054 #define RMT_CH7_ERR_INT_ENA (BIT(23)) 2055 #define RMT_CH7_ERR_INT_ENA_M (BIT(23)) 2056 #define RMT_CH7_ERR_INT_ENA_V 0x1 2057 #define RMT_CH7_ERR_INT_ENA_S 23 2058 /* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ 2059 /*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/ 2060 #define RMT_CH7_RX_END_INT_ENA (BIT(22)) 2061 #define RMT_CH7_RX_END_INT_ENA_M (BIT(22)) 2062 #define RMT_CH7_RX_END_INT_ENA_V 0x1 2063 #define RMT_CH7_RX_END_INT_ENA_S 22 2064 /* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ 2065 /*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/ 2066 #define RMT_CH7_TX_END_INT_ENA (BIT(21)) 2067 #define RMT_CH7_TX_END_INT_ENA_M (BIT(21)) 2068 #define RMT_CH7_TX_END_INT_ENA_V 0x1 2069 #define RMT_CH7_TX_END_INT_ENA_S 21 2070 /* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ 2071 /*description: Set this bit to enable rmt_ch6_err_int_st.*/ 2072 #define RMT_CH6_ERR_INT_ENA (BIT(20)) 2073 #define RMT_CH6_ERR_INT_ENA_M (BIT(20)) 2074 #define RMT_CH6_ERR_INT_ENA_V 0x1 2075 #define RMT_CH6_ERR_INT_ENA_S 20 2076 /* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ 2077 /*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/ 2078 #define RMT_CH6_RX_END_INT_ENA (BIT(19)) 2079 #define RMT_CH6_RX_END_INT_ENA_M (BIT(19)) 2080 #define RMT_CH6_RX_END_INT_ENA_V 0x1 2081 #define RMT_CH6_RX_END_INT_ENA_S 19 2082 /* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ 2083 /*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/ 2084 #define RMT_CH6_TX_END_INT_ENA (BIT(18)) 2085 #define RMT_CH6_TX_END_INT_ENA_M (BIT(18)) 2086 #define RMT_CH6_TX_END_INT_ENA_V 0x1 2087 #define RMT_CH6_TX_END_INT_ENA_S 18 2088 /* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ 2089 /*description: Set this bit to enable rmt_ch5_err_int_st.*/ 2090 #define RMT_CH5_ERR_INT_ENA (BIT(17)) 2091 #define RMT_CH5_ERR_INT_ENA_M (BIT(17)) 2092 #define RMT_CH5_ERR_INT_ENA_V 0x1 2093 #define RMT_CH5_ERR_INT_ENA_S 17 2094 /* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 2095 /*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/ 2096 #define RMT_CH5_RX_END_INT_ENA (BIT(16)) 2097 #define RMT_CH5_RX_END_INT_ENA_M (BIT(16)) 2098 #define RMT_CH5_RX_END_INT_ENA_V 0x1 2099 #define RMT_CH5_RX_END_INT_ENA_S 16 2100 /* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2101 /*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/ 2102 #define RMT_CH5_TX_END_INT_ENA (BIT(15)) 2103 #define RMT_CH5_TX_END_INT_ENA_M (BIT(15)) 2104 #define RMT_CH5_TX_END_INT_ENA_V 0x1 2105 #define RMT_CH5_TX_END_INT_ENA_S 15 2106 /* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2107 /*description: Set this bit to enable rmt_ch4_err_int_st.*/ 2108 #define RMT_CH4_ERR_INT_ENA (BIT(14)) 2109 #define RMT_CH4_ERR_INT_ENA_M (BIT(14)) 2110 #define RMT_CH4_ERR_INT_ENA_V 0x1 2111 #define RMT_CH4_ERR_INT_ENA_S 14 2112 /* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 2113 /*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/ 2114 #define RMT_CH4_RX_END_INT_ENA (BIT(13)) 2115 #define RMT_CH4_RX_END_INT_ENA_M (BIT(13)) 2116 #define RMT_CH4_RX_END_INT_ENA_V 0x1 2117 #define RMT_CH4_RX_END_INT_ENA_S 13 2118 /* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 2119 /*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/ 2120 #define RMT_CH4_TX_END_INT_ENA (BIT(12)) 2121 #define RMT_CH4_TX_END_INT_ENA_M (BIT(12)) 2122 #define RMT_CH4_TX_END_INT_ENA_V 0x1 2123 #define RMT_CH4_TX_END_INT_ENA_S 12 2124 /* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 2125 /*description: Set this bit to enable rmt_ch3_err_int_st.*/ 2126 #define RMT_CH3_ERR_INT_ENA (BIT(11)) 2127 #define RMT_CH3_ERR_INT_ENA_M (BIT(11)) 2128 #define RMT_CH3_ERR_INT_ENA_V 0x1 2129 #define RMT_CH3_ERR_INT_ENA_S 11 2130 /* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 2131 /*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/ 2132 #define RMT_CH3_RX_END_INT_ENA (BIT(10)) 2133 #define RMT_CH3_RX_END_INT_ENA_M (BIT(10)) 2134 #define RMT_CH3_RX_END_INT_ENA_V 0x1 2135 #define RMT_CH3_RX_END_INT_ENA_S 10 2136 /* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 2137 /*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/ 2138 #define RMT_CH3_TX_END_INT_ENA (BIT(9)) 2139 #define RMT_CH3_TX_END_INT_ENA_M (BIT(9)) 2140 #define RMT_CH3_TX_END_INT_ENA_V 0x1 2141 #define RMT_CH3_TX_END_INT_ENA_S 9 2142 /* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 2143 /*description: Set this bit to enable rmt_ch2_err_int_st.*/ 2144 #define RMT_CH2_ERR_INT_ENA (BIT(8)) 2145 #define RMT_CH2_ERR_INT_ENA_M (BIT(8)) 2146 #define RMT_CH2_ERR_INT_ENA_V 0x1 2147 #define RMT_CH2_ERR_INT_ENA_S 8 2148 /* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 2149 /*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/ 2150 #define RMT_CH2_RX_END_INT_ENA (BIT(7)) 2151 #define RMT_CH2_RX_END_INT_ENA_M (BIT(7)) 2152 #define RMT_CH2_RX_END_INT_ENA_V 0x1 2153 #define RMT_CH2_RX_END_INT_ENA_S 7 2154 /* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 2155 /*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/ 2156 #define RMT_CH2_TX_END_INT_ENA (BIT(6)) 2157 #define RMT_CH2_TX_END_INT_ENA_M (BIT(6)) 2158 #define RMT_CH2_TX_END_INT_ENA_V 0x1 2159 #define RMT_CH2_TX_END_INT_ENA_S 6 2160 /* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 2161 /*description: Set this bit to enable rmt_ch1_err_int_st.*/ 2162 #define RMT_CH1_ERR_INT_ENA (BIT(5)) 2163 #define RMT_CH1_ERR_INT_ENA_M (BIT(5)) 2164 #define RMT_CH1_ERR_INT_ENA_V 0x1 2165 #define RMT_CH1_ERR_INT_ENA_S 5 2166 /* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 2167 /*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/ 2168 #define RMT_CH1_RX_END_INT_ENA (BIT(4)) 2169 #define RMT_CH1_RX_END_INT_ENA_M (BIT(4)) 2170 #define RMT_CH1_RX_END_INT_ENA_V 0x1 2171 #define RMT_CH1_RX_END_INT_ENA_S 4 2172 /* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 2173 /*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/ 2174 #define RMT_CH1_TX_END_INT_ENA (BIT(3)) 2175 #define RMT_CH1_TX_END_INT_ENA_M (BIT(3)) 2176 #define RMT_CH1_TX_END_INT_ENA_V 0x1 2177 #define RMT_CH1_TX_END_INT_ENA_S 3 2178 /* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2179 /*description: Set this bit to enable rmt_ch0_err_int_st.*/ 2180 #define RMT_CH0_ERR_INT_ENA (BIT(2)) 2181 #define RMT_CH0_ERR_INT_ENA_M (BIT(2)) 2182 #define RMT_CH0_ERR_INT_ENA_V 0x1 2183 #define RMT_CH0_ERR_INT_ENA_S 2 2184 /* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2185 /*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/ 2186 #define RMT_CH0_RX_END_INT_ENA (BIT(1)) 2187 #define RMT_CH0_RX_END_INT_ENA_M (BIT(1)) 2188 #define RMT_CH0_RX_END_INT_ENA_V 0x1 2189 #define RMT_CH0_RX_END_INT_ENA_S 1 2190 /* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2191 /*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/ 2192 #define RMT_CH0_TX_END_INT_ENA (BIT(0)) 2193 #define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) 2194 #define RMT_CH0_TX_END_INT_ENA_V 0x1 2195 #define RMT_CH0_TX_END_INT_ENA_S 0 2196 2197 #define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac) 2198 /* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ 2199 /*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ 2200 #define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31)) 2201 #define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31)) 2202 #define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1 2203 #define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31 2204 /* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ 2205 /*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ 2206 #define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30)) 2207 #define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30)) 2208 #define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1 2209 #define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30 2210 /* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ 2211 /*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ 2212 #define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29)) 2213 #define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29)) 2214 #define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1 2215 #define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29 2216 /* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ 2217 /*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ 2218 #define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28)) 2219 #define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28)) 2220 #define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1 2221 #define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28 2222 /* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ 2223 /*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ 2224 #define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27)) 2225 #define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27)) 2226 #define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 2227 #define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27 2228 /* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ 2229 /*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ 2230 #define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26)) 2231 #define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26)) 2232 #define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 2233 #define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26 2234 /* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ 2235 /*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ 2236 #define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25)) 2237 #define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25)) 2238 #define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 2239 #define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25 2240 /* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ 2241 /*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ 2242 #define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24)) 2243 #define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24)) 2244 #define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 2245 #define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24 2246 /* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ 2247 /*description: Set this bit to clear the rmt_ch7_err_int_raw.*/ 2248 #define RMT_CH7_ERR_INT_CLR (BIT(23)) 2249 #define RMT_CH7_ERR_INT_CLR_M (BIT(23)) 2250 #define RMT_CH7_ERR_INT_CLR_V 0x1 2251 #define RMT_CH7_ERR_INT_CLR_S 23 2252 /* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ 2253 /*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ 2254 #define RMT_CH7_RX_END_INT_CLR (BIT(22)) 2255 #define RMT_CH7_RX_END_INT_CLR_M (BIT(22)) 2256 #define RMT_CH7_RX_END_INT_CLR_V 0x1 2257 #define RMT_CH7_RX_END_INT_CLR_S 22 2258 /* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ 2259 /*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ 2260 #define RMT_CH7_TX_END_INT_CLR (BIT(21)) 2261 #define RMT_CH7_TX_END_INT_CLR_M (BIT(21)) 2262 #define RMT_CH7_TX_END_INT_CLR_V 0x1 2263 #define RMT_CH7_TX_END_INT_CLR_S 21 2264 /* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ 2265 /*description: Set this bit to clear the rmt_ch6_err_int_raw.*/ 2266 #define RMT_CH6_ERR_INT_CLR (BIT(20)) 2267 #define RMT_CH6_ERR_INT_CLR_M (BIT(20)) 2268 #define RMT_CH6_ERR_INT_CLR_V 0x1 2269 #define RMT_CH6_ERR_INT_CLR_S 20 2270 /* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ 2271 /*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ 2272 #define RMT_CH6_RX_END_INT_CLR (BIT(19)) 2273 #define RMT_CH6_RX_END_INT_CLR_M (BIT(19)) 2274 #define RMT_CH6_RX_END_INT_CLR_V 0x1 2275 #define RMT_CH6_RX_END_INT_CLR_S 19 2276 /* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ 2277 /*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ 2278 #define RMT_CH6_TX_END_INT_CLR (BIT(18)) 2279 #define RMT_CH6_TX_END_INT_CLR_M (BIT(18)) 2280 #define RMT_CH6_TX_END_INT_CLR_V 0x1 2281 #define RMT_CH6_TX_END_INT_CLR_S 18 2282 /* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ 2283 /*description: Set this bit to clear the rmt_ch5_err_int_raw.*/ 2284 #define RMT_CH5_ERR_INT_CLR (BIT(17)) 2285 #define RMT_CH5_ERR_INT_CLR_M (BIT(17)) 2286 #define RMT_CH5_ERR_INT_CLR_V 0x1 2287 #define RMT_CH5_ERR_INT_CLR_S 17 2288 /* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 2289 /*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ 2290 #define RMT_CH5_RX_END_INT_CLR (BIT(16)) 2291 #define RMT_CH5_RX_END_INT_CLR_M (BIT(16)) 2292 #define RMT_CH5_RX_END_INT_CLR_V 0x1 2293 #define RMT_CH5_RX_END_INT_CLR_S 16 2294 /* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 2295 /*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ 2296 #define RMT_CH5_TX_END_INT_CLR (BIT(15)) 2297 #define RMT_CH5_TX_END_INT_CLR_M (BIT(15)) 2298 #define RMT_CH5_TX_END_INT_CLR_V 0x1 2299 #define RMT_CH5_TX_END_INT_CLR_S 15 2300 /* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ 2301 /*description: Set this bit to clear the rmt_ch4_err_int_raw.*/ 2302 #define RMT_CH4_ERR_INT_CLR (BIT(14)) 2303 #define RMT_CH4_ERR_INT_CLR_M (BIT(14)) 2304 #define RMT_CH4_ERR_INT_CLR_V 0x1 2305 #define RMT_CH4_ERR_INT_CLR_S 14 2306 /* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ 2307 /*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ 2308 #define RMT_CH4_RX_END_INT_CLR (BIT(13)) 2309 #define RMT_CH4_RX_END_INT_CLR_M (BIT(13)) 2310 #define RMT_CH4_RX_END_INT_CLR_V 0x1 2311 #define RMT_CH4_RX_END_INT_CLR_S 13 2312 /* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ 2313 /*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ 2314 #define RMT_CH4_TX_END_INT_CLR (BIT(12)) 2315 #define RMT_CH4_TX_END_INT_CLR_M (BIT(12)) 2316 #define RMT_CH4_TX_END_INT_CLR_V 0x1 2317 #define RMT_CH4_TX_END_INT_CLR_S 12 2318 /* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 2319 /*description: Set this bit to clear the rmt_ch3_err_int_raw.*/ 2320 #define RMT_CH3_ERR_INT_CLR (BIT(11)) 2321 #define RMT_CH3_ERR_INT_CLR_M (BIT(11)) 2322 #define RMT_CH3_ERR_INT_CLR_V 0x1 2323 #define RMT_CH3_ERR_INT_CLR_S 11 2324 /* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 2325 /*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ 2326 #define RMT_CH3_RX_END_INT_CLR (BIT(10)) 2327 #define RMT_CH3_RX_END_INT_CLR_M (BIT(10)) 2328 #define RMT_CH3_RX_END_INT_CLR_V 0x1 2329 #define RMT_CH3_RX_END_INT_CLR_S 10 2330 /* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 2331 /*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ 2332 #define RMT_CH3_TX_END_INT_CLR (BIT(9)) 2333 #define RMT_CH3_TX_END_INT_CLR_M (BIT(9)) 2334 #define RMT_CH3_TX_END_INT_CLR_V 0x1 2335 #define RMT_CH3_TX_END_INT_CLR_S 9 2336 /* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 2337 /*description: Set this bit to clear the rmt_ch2_err_int_raw.*/ 2338 #define RMT_CH2_ERR_INT_CLR (BIT(8)) 2339 #define RMT_CH2_ERR_INT_CLR_M (BIT(8)) 2340 #define RMT_CH2_ERR_INT_CLR_V 0x1 2341 #define RMT_CH2_ERR_INT_CLR_S 8 2342 /* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 2343 /*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ 2344 #define RMT_CH2_RX_END_INT_CLR (BIT(7)) 2345 #define RMT_CH2_RX_END_INT_CLR_M (BIT(7)) 2346 #define RMT_CH2_RX_END_INT_CLR_V 0x1 2347 #define RMT_CH2_RX_END_INT_CLR_S 7 2348 /* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 2349 /*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ 2350 #define RMT_CH2_TX_END_INT_CLR (BIT(6)) 2351 #define RMT_CH2_TX_END_INT_CLR_M (BIT(6)) 2352 #define RMT_CH2_TX_END_INT_CLR_V 0x1 2353 #define RMT_CH2_TX_END_INT_CLR_S 6 2354 /* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 2355 /*description: Set this bit to clear the rmt_ch1_err_int_raw.*/ 2356 #define RMT_CH1_ERR_INT_CLR (BIT(5)) 2357 #define RMT_CH1_ERR_INT_CLR_M (BIT(5)) 2358 #define RMT_CH1_ERR_INT_CLR_V 0x1 2359 #define RMT_CH1_ERR_INT_CLR_S 5 2360 /* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 2361 /*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ 2362 #define RMT_CH1_RX_END_INT_CLR (BIT(4)) 2363 #define RMT_CH1_RX_END_INT_CLR_M (BIT(4)) 2364 #define RMT_CH1_RX_END_INT_CLR_V 0x1 2365 #define RMT_CH1_RX_END_INT_CLR_S 4 2366 /* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 2367 /*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ 2368 #define RMT_CH1_TX_END_INT_CLR (BIT(3)) 2369 #define RMT_CH1_TX_END_INT_CLR_M (BIT(3)) 2370 #define RMT_CH1_TX_END_INT_CLR_V 0x1 2371 #define RMT_CH1_TX_END_INT_CLR_S 3 2372 /* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 2373 /*description: Set this bit to clear the rmt_ch0_err_int_raw.*/ 2374 #define RMT_CH0_ERR_INT_CLR (BIT(2)) 2375 #define RMT_CH0_ERR_INT_CLR_M (BIT(2)) 2376 #define RMT_CH0_ERR_INT_CLR_V 0x1 2377 #define RMT_CH0_ERR_INT_CLR_S 2 2378 /* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 2379 /*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ 2380 #define RMT_CH0_RX_END_INT_CLR (BIT(1)) 2381 #define RMT_CH0_RX_END_INT_CLR_M (BIT(1)) 2382 #define RMT_CH0_RX_END_INT_CLR_V 0x1 2383 #define RMT_CH0_RX_END_INT_CLR_S 1 2384 /* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 2385 /*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ 2386 #define RMT_CH0_TX_END_INT_CLR (BIT(0)) 2387 #define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) 2388 #define RMT_CH0_TX_END_INT_CLR_V 0x1 2389 #define RMT_CH0_TX_END_INT_CLR_S 0 2390 2391 #define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0) 2392 /* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ 2393 /*description: This register is used to configure carrier wave's high level value for channel0.*/ 2394 #define RMT_CARRIER_HIGH_CH0 0x0000FFFF 2395 #define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) 2396 #define RMT_CARRIER_HIGH_CH0_V 0xFFFF 2397 #define RMT_CARRIER_HIGH_CH0_S 16 2398 /* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ 2399 /*description: This register is used to configure carrier wave's low level value for channel0.*/ 2400 #define RMT_CARRIER_LOW_CH0 0x0000FFFF 2401 #define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) 2402 #define RMT_CARRIER_LOW_CH0_V 0xFFFF 2403 #define RMT_CARRIER_LOW_CH0_S 0 2404 2405 #define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4) 2406 /* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ 2407 /*description: This register is used to configure carrier wave's high level value for channel1.*/ 2408 #define RMT_CARRIER_HIGH_CH1 0x0000FFFF 2409 #define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) 2410 #define RMT_CARRIER_HIGH_CH1_V 0xFFFF 2411 #define RMT_CARRIER_HIGH_CH1_S 16 2412 /* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ 2413 /*description: This register is used to configure carrier wave's low level value for channel1.*/ 2414 #define RMT_CARRIER_LOW_CH1 0x0000FFFF 2415 #define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) 2416 #define RMT_CARRIER_LOW_CH1_V 0xFFFF 2417 #define RMT_CARRIER_LOW_CH1_S 0 2418 2419 #define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8) 2420 /* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ 2421 /*description: This register is used to configure carrier wave's high level value for channel2.*/ 2422 #define RMT_CARRIER_HIGH_CH2 0x0000FFFF 2423 #define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) 2424 #define RMT_CARRIER_HIGH_CH2_V 0xFFFF 2425 #define RMT_CARRIER_HIGH_CH2_S 16 2426 /* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ 2427 /*description: This register is used to configure carrier wave's low level value for channel2.*/ 2428 #define RMT_CARRIER_LOW_CH2 0x0000FFFF 2429 #define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) 2430 #define RMT_CARRIER_LOW_CH2_V 0xFFFF 2431 #define RMT_CARRIER_LOW_CH2_S 0 2432 2433 #define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc) 2434 /* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ 2435 /*description: This register is used to configure carrier wave's high level value for channel3.*/ 2436 #define RMT_CARRIER_HIGH_CH3 0x0000FFFF 2437 #define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) 2438 #define RMT_CARRIER_HIGH_CH3_V 0xFFFF 2439 #define RMT_CARRIER_HIGH_CH3_S 16 2440 /* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ 2441 /*description: This register is used to configure carrier wave's low level value for channel3.*/ 2442 #define RMT_CARRIER_LOW_CH3 0x0000FFFF 2443 #define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) 2444 #define RMT_CARRIER_LOW_CH3_V 0xFFFF 2445 #define RMT_CARRIER_LOW_CH3_S 0 2446 2447 #define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0) 2448 /* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ 2449 /*description: This register is used to configure carrier wave's high level value for channel4.*/ 2450 #define RMT_CARRIER_HIGH_CH4 0x0000FFFF 2451 #define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S)) 2452 #define RMT_CARRIER_HIGH_CH4_V 0xFFFF 2453 #define RMT_CARRIER_HIGH_CH4_S 16 2454 /* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ 2455 /*description: This register is used to configure carrier wave's low level value for channel4.*/ 2456 #define RMT_CARRIER_LOW_CH4 0x0000FFFF 2457 #define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S)) 2458 #define RMT_CARRIER_LOW_CH4_V 0xFFFF 2459 #define RMT_CARRIER_LOW_CH4_S 0 2460 2461 #define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4) 2462 /* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ 2463 /*description: This register is used to configure carrier wave's high level value for channel5.*/ 2464 #define RMT_CARRIER_HIGH_CH5 0x0000FFFF 2465 #define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S)) 2466 #define RMT_CARRIER_HIGH_CH5_V 0xFFFF 2467 #define RMT_CARRIER_HIGH_CH5_S 16 2468 /* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ 2469 /*description: This register is used to configure carrier wave's low level value for channel5.*/ 2470 #define RMT_CARRIER_LOW_CH5 0x0000FFFF 2471 #define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S)) 2472 #define RMT_CARRIER_LOW_CH5_V 0xFFFF 2473 #define RMT_CARRIER_LOW_CH5_S 0 2474 2475 #define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8) 2476 /* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ 2477 /*description: This register is used to configure carrier wave's high level value for channel6.*/ 2478 #define RMT_CARRIER_HIGH_CH6 0x0000FFFF 2479 #define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S)) 2480 #define RMT_CARRIER_HIGH_CH6_V 0xFFFF 2481 #define RMT_CARRIER_HIGH_CH6_S 16 2482 /* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ 2483 /*description: This register is used to configure carrier wave's low level value for channel6.*/ 2484 #define RMT_CARRIER_LOW_CH6 0x0000FFFF 2485 #define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S)) 2486 #define RMT_CARRIER_LOW_CH6_V 0xFFFF 2487 #define RMT_CARRIER_LOW_CH6_S 0 2488 2489 #define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc) 2490 /* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ 2491 /*description: This register is used to configure carrier wave's high level value for channel7.*/ 2492 #define RMT_CARRIER_HIGH_CH7 0x0000FFFF 2493 #define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S)) 2494 #define RMT_CARRIER_HIGH_CH7_V 0xFFFF 2495 #define RMT_CARRIER_HIGH_CH7_S 16 2496 /* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ 2497 /*description: This register is used to configure carrier wave's low level value for channel7.*/ 2498 #define RMT_CARRIER_LOW_CH7 0x0000FFFF 2499 #define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S)) 2500 #define RMT_CARRIER_LOW_CH7_V 0xFFFF 2501 #define RMT_CARRIER_LOW_CH7_S 0 2502 2503 #define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0) 2504 /* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ 2505 /*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 2506 produce the relative interrupt.*/ 2507 #define RMT_TX_LIM_CH0 0x000001FF 2508 #define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) 2509 #define RMT_TX_LIM_CH0_V 0x1FF 2510 #define RMT_TX_LIM_CH0_S 0 2511 2512 #define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4) 2513 /* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ 2514 /*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1 2515 produce the relative interrupt.*/ 2516 #define RMT_TX_LIM_CH1 0x000001FF 2517 #define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) 2518 #define RMT_TX_LIM_CH1_V 0x1FF 2519 #define RMT_TX_LIM_CH1_S 0 2520 2521 #define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8) 2522 /* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ 2523 /*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2 2524 produce the relative interrupt.*/ 2525 #define RMT_TX_LIM_CH2 0x000001FF 2526 #define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) 2527 #define RMT_TX_LIM_CH2_V 0x1FF 2528 #define RMT_TX_LIM_CH2_S 0 2529 2530 #define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc) 2531 /* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ 2532 /*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3 2533 produce the relative interrupt.*/ 2534 #define RMT_TX_LIM_CH3 0x000001FF 2535 #define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) 2536 #define RMT_TX_LIM_CH3_V 0x1FF 2537 #define RMT_TX_LIM_CH3_S 0 2538 2539 #define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0) 2540 /* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ 2541 /*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4 2542 produce the relative interrupt.*/ 2543 #define RMT_TX_LIM_CH4 0x000001FF 2544 #define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S)) 2545 #define RMT_TX_LIM_CH4_V 0x1FF 2546 #define RMT_TX_LIM_CH4_S 0 2547 2548 #define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4) 2549 /* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ 2550 /*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5 2551 produce the relative interrupt.*/ 2552 #define RMT_TX_LIM_CH5 0x000001FF 2553 #define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S)) 2554 #define RMT_TX_LIM_CH5_V 0x1FF 2555 #define RMT_TX_LIM_CH5_S 0 2556 2557 #define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8) 2558 /* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ 2559 /*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6 2560 produce the relative interrupt.*/ 2561 #define RMT_TX_LIM_CH6 0x000001FF 2562 #define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S)) 2563 #define RMT_TX_LIM_CH6_V 0x1FF 2564 #define RMT_TX_LIM_CH6_S 0 2565 2566 #define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec) 2567 /* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ 2568 /*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7 2569 produce the relative interrupt.*/ 2570 #define RMT_TX_LIM_CH7 0x000001FF 2571 #define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S)) 2572 #define RMT_TX_LIM_CH7_V 0x1FF 2573 #define RMT_TX_LIM_CH7_S 0 2574 2575 #define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0) 2576 /* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2577 /*description: when datas need to be send is more than channel's mem can store 2578 then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/ 2579 #define RMT_MEM_TX_WRAP_EN (BIT(1)) 2580 #define RMT_MEM_TX_WRAP_EN_M (BIT(1)) 2581 #define RMT_MEM_TX_WRAP_EN_V 0x1 2582 #define RMT_MEM_TX_WRAP_EN_S 1 2583 /* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ 2584 /*description: Set this bit to disable apb fifo access*/ 2585 #define RMT_APB_FIFO_MASK (BIT(0)) 2586 #define RMT_APB_FIFO_MASK_M (BIT(0)) 2587 #define RMT_APB_FIFO_MASK_V 0x1 2588 #define RMT_APB_FIFO_MASK_S 0 2589 2590 #define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc) 2591 /* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */ 2592 /*description: This is the version register.*/ 2593 #define RMT_DATE 0xFFFFFFFF 2594 #define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) 2595 #define RMT_DATE_V 0xFFFFFFFF 2596 #define RMT_DATE_S 0 2597 2598 /* RMT memory block address */ 2599 #define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i)) 2600 2601 2602 #endif /*_SOC_RMT_REG_H_ */ 2603