1root { 2 platform { 3 spi_i2s_config { 4 template stm32mp1_spi_i2s_device { 5 match_attr = ""; 6 busModeSel = 1; // 0: Disabled; 1: SPI mode; 2: I2S mode. 7 regPBase = 0x44004000; 8 regSize = 0x400; 9 busNum = 0; 10 fifoSize = 4; // no more than 8. 11 spi_transferMode = 0; 12 spi_bitsPerWord = 8; 13 spi_mode = 19; 14 spi_clkRate = 200000000; 15 spi_speed = 10000000; 16 spi_numCs = 1; 17 /* 18 NSS SCK MISO MOSI 19 pins[port, pin, funcNum, ...] 20 <port> 0:GPIOA 1:GPIOB 2:GPIOC ...... 10:GPIOK 25:GPIOZ 21 <pin> 0:PIN0 1:PIN1 2:PIN2 ...... 22 <funcNum> 0-15: AF0-AF15 23 */ 24 pins = [0, 4, 5, 0, 5, 5, 0, 6, 5, 0, 7, 5]; 25 irqNum = 67; 26 } 27 controller_0x44004000 :: stm32mp1_spi_i2s_device { 28 match_attr = "st_stm32mp157_spi_1"; 29 busNum = 1; 30 pins = [0, 0, 15, 25, 0, 5, 25, 1, 5, 25, 2, 5]; 31 irqNum = 67; 32 } 33 controller_0x4000B000 :: stm32mp1_spi_i2s_device { 34 match_attr = "st_stm32mp157_spi_2"; 35 regPBase = 0x4000B000; 36 busModeSel = 0; 37 busNum = 2; 38 pins = [1, 12, 5, 1, 13, 5, 1, 14, 5, 1, 15, 5]; 39 irqNum = 68; 40 } 41 controller_0x4000C000 :: stm32mp1_spi_i2s_device { 42 match_attr = "st_stm32mp157_spi_3"; 43 regPBase = 0x4000C000; 44 busModeSel = 0; 45 busNum = 3; 46 pins = [0, 15, 6, 2, 10, 6, 2, 11, 6, 2, 12, 6]; 47 irqNum = 83; 48 } 49 controller_0x44005000 :: stm32mp1_spi_i2s_device { 50 match_attr = "st_stm32mp157_spi_4"; 51 regPBase = 0x44005000; 52 busModeSel = 0; 53 busNum = 4; 54 pins = [4, 11, 5, 4, 12, 5, 4, 13, 5, 4, 14, 5]; 55 irqNum = 116; 56 } 57 controller_0x44009000 :: stm32mp1_spi_i2s_device { 58 match_attr = "st_stm32mp157_spi_5"; 59 regPBase = 0x44009000; 60 busModeSel = 0; 61 busNum = 5; 62 pins = [5, 6, 5, 5, 7, 5, 5, 8, 5, 5, 9, 5]; 63 irqNum = 117; 64 } 65 controller_0x5C001000 :: stm32mp1_spi_i2s_device { 66 match_attr = "st_stm32mp157_spi_6"; 67 regPBase = 0x5C001000; 68 busModeSel = 0; 69 busNum = 6; 70 pins = [6, 8, 5, 6, 13, 5, 6, 12, 5, 6, 14, 5]; 71 irqNum = 118; 72 } 73 } 74 } 75}