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1 /**
2   ******************************************************************************
3   * @file    stm32f4x7_eth_conf_template.h
4   * @author  MCD Application Team
5   * @version V1.1.0
6   * @date    31-July-2013
7   * @brief   Configuration file for the STM32F4x7xx Ethernet driver.
8   *          This file should be copied to the application folder and renamed to
9   *          stm32f4x7_eth_conf.h
10   ******************************************************************************
11   * @attention
12   *
13   * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
14   *
15   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
16   * You may not use this file except in compliance with the License.
17   * You may obtain a copy of the License at:
18   *
19   *        http://www.st.com/software_license_agreement_liberty_v2
20   *
21   * Unless required by applicable law or agreed to in writing, software
22   * distributed under the License is distributed on an "AS IS" BASIS,
23   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24   * See the License for the specific language governing permissions and
25   * limitations under the License.
26   *
27   ******************************************************************************
28   */
29 
30 #ifndef __STM32F4x7_ETH_CONF_H
31 #define __STM32F4x7_ETH_CONF_H
32 #include "stm32f4xx.h"
33 
34 #define USE_ENHANCED_DMA_DESCRIPTORS
35 
36 #ifdef USE_Delay
37 #define _eth_delay_         Delay
38 #else
39 #define _eth_delay_         ETH_Delay
40 #endif
41 
42 #ifdef  CUSTOM_DRIVER_BUFFERS_CONFIG
43 #define ETH_RX_BUF_SIZE     ETH_MAX_PACKET_SIZE
44 #define ETH_TX_BUF_SIZE     ETH_MAX_PACKET_SIZE
45 #define ETH_RXBUFNB         20
46 #define ETH_TXBUFNB         5
47 #endif
48 
49 #ifdef USE_Delay
50 #define PHY_RESET_DELAY     ((uint32_t)0x000000FF)
51 #define PHY_CONFIG_DELAY    ((uint32_t)0x00000FFF)
52 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
53 #else
54 #define PHY_RESET_DELAY     ((uint32_t)0x000FFFFF)
55 #define PHY_CONFIG_DELAY    ((uint32_t)0x00FFFFFF)
56 #define ETH_REG_WRITE_DELAY ((uint32_t)0x0000FFFF)
57 #endif
58 
59 #define PHY_SR              ((uint16_t)31)
60 #define PHY_SPEED_STATUS    ((uint16_t)0x0004)
61 #define PHY_DUPLEX_STATUS   ((uint16_t)0x00010)
62 
63 #endif
64