1 /**
2 ******************************************************************************
3 * @file stm32f4xx_fmc.c
4 * @author MCD Application Team
5 * @version V1.4.0
6 * @date 04-August-2014
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the FMC peripheral:
9 * + Interface with SRAM, PSRAM, NOR and OneNAND memories
10 * + Interface with NAND memories
11 * + Interface with 16-bit PC Card compatible memories
12 * + Interface with SDRAM memories
13 * + Interrupts and flags management
14 *
15 ******************************************************************************
16 * @attention
17 *
18 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
19 *
20 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
21 * You may not use this file except in compliance with the License.
22 * You may obtain a copy of the License at:
23 *
24 * http://www.st.com/software_license_agreement_liberty_v2
25 *
26 * Unless required by applicable law or agreed to in writing, software
27 * distributed under the License is distributed on an "AS IS" BASIS,
28 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
29 * See the License for the specific language governing permissions and
30 * limitations under the License.
31 *
32 ******************************************************************************
33 */
34
35 /* Includes ------------------------------------------------------------------*/
36 #include "stm32f4xx_fmc.h"
37 #include "stm32f4xx_rcc.h"
38
39 /** @addtogroup STM32F4xx_StdPeriph_Driver
40 * @{
41 */
42
43 /** @defgroup FMC
44 * @brief FMC driver modules
45 * @{
46 */
47
48 /* Private typedef -----------------------------------------------------------*/
49 const FMC_NORSRAMTimingInitTypeDef FMC_DefaultTimingStruct = {0x0F, /* FMC_AddressSetupTime */
50 0x0F, /* FMC_AddressHoldTime */
51 0xFF, /* FMC_DataSetupTime */
52 0x0F, /* FMC_BusTurnAroundDuration */
53 0x0F, /* FMC_CLKDivision */
54 0x0F, /* FMC_DataLatency */
55 FMC_AccessMode_A /* FMC_AccessMode */
56 };
57 /* --------------------- FMC registers bit mask ---------------------------- */
58 /* FMC BCRx Mask */
59 #define BCR_MBKEN_SET ((uint32_t)0x00000001)
60 #define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
61 #define BCR_FACCEN_SET ((uint32_t)0x00000040)
62
63 /* FMC PCRx Mask */
64 #define PCR_PBKEN_SET ((uint32_t)0x00000004)
65 #define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
66 #define PCR_ECCEN_SET ((uint32_t)0x00000040)
67 #define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
68 #define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
69
70 /* FMC SDCRx write protection Mask*/
71 #define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF)
72
73 /* FMC SDCMR Mask*/
74 #define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF)
75 #define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7)
76 #define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7)
77
78 /* Private macro -------------------------------------------------------------*/
79 /* Private variables ---------------------------------------------------------*/
80 /* Private function prototypes -----------------------------------------------*/
81 /* Private functions ---------------------------------------------------------*/
82
83 /** @defgroup FMC_Private_Functions
84 * @{
85 */
86
87 /** @defgroup FMC_Group1 NOR/SRAM Controller functions
88 * @brief NOR/SRAM Controller functions
89 *
90 @verbatim
91 ===============================================================================
92 ##### NOR and SRAM Controller functions #####
93 ===============================================================================
94
95 [..] The following sequence should be followed to configure the FMC to interface
96 with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
97
98 (#) Enable the clock for the FMC and associated GPIOs using the following functions:
99 RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
100 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
101
102 (#) FMC pins configuration
103 (++) Connect the involved FMC pins to AF12 using the following function
104 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
105 (++) Configure these FMC pins in alternate function mode by calling the function
106 GPIO_Init();
107
108 (#) Declare a FMC_NORSRAMInitTypeDef structure, for example:
109 FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure;
110 and fill the FMC_NORSRAMInitStructure variable with the allowed values of
111 the structure member.
112
113 (#) Initialize the NOR/SRAM Controller by calling the function
114 FMC_NORSRAMInit(&FMC_NORSRAMInitStructure);
115
116 (#) Then enable the NOR/SRAM Bank, for example:
117 FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE);
118
119 (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
120
121 @endverbatim
122 * @{
123 */
124
125 /**
126 * @brief De-initializes the FMC NOR/SRAM Banks registers to their default
127 * reset values.
128 * @param FMC_Bank: specifies the FMC Bank to be used
129 * This parameter can be one of the following values:
130 * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
131 * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
132 * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
133 * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
134 * @retval None
135 */
FMC_NORSRAMDeInit(uint32_t FMC_Bank)136 void FMC_NORSRAMDeInit(uint32_t FMC_Bank)
137 {
138 /* Check the parameter */
139 assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
140
141 /* FMC_Bank1_NORSRAM1 */
142 if(FMC_Bank == FMC_Bank1_NORSRAM1)
143 {
144 FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB;
145 }
146 /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */
147 else
148 {
149 FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2;
150 }
151 FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF;
152 FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF;
153 }
154
155 /**
156 * @brief Initializes the FMC NOR/SRAM Banks according to the specified
157 * parameters in the FMC_NORSRAMInitStruct.
158 * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure
159 * that contains the configuration information for the FMC NOR/SRAM
160 * specified Banks.
161 * @retval None
162 */
FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef * FMC_NORSRAMInitStruct)163 void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
164 {
165 uint32_t tmpr = 0;
166
167 /* Check the parameters */
168 assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank));
169 assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux));
170 assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType));
171 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth));
172 assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode));
173 assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity));
174 assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode));
175 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive));
176 assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation));
177 assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal));
178 assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode));
179 assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait));
180 assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst));
181 assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock));
182 assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime));
183 assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime));
184 assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime));
185 assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration));
186 assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision));
187 assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency));
188 assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode));
189
190 /* NOR/SRAM Bank control register configuration */
191 FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] =
192 (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
193 FMC_NORSRAMInitStruct->FMC_MemoryType |
194 FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
195 FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
196 FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity |
197 FMC_NORSRAMInitStruct->FMC_WrapMode |
198 FMC_NORSRAMInitStruct->FMC_WaitSignalActive |
199 FMC_NORSRAMInitStruct->FMC_WriteOperation |
200 FMC_NORSRAMInitStruct->FMC_WaitSignal |
201 FMC_NORSRAMInitStruct->FMC_ExtendedMode |
202 FMC_NORSRAMInitStruct->FMC_AsynchronousWait |
203 FMC_NORSRAMInitStruct->FMC_WriteBurst |
204 FMC_NORSRAMInitStruct->FMC_ContinousClock;
205
206
207 if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR)
208 {
209 FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
210 }
211
212 /* Configure Continuous clock feature when bank2..4 is used */
213 if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1))
214 {
215 tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20));
216
217 FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock;
218 FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable;
219 FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
220 }
221
222 /* NOR/SRAM Bank timing register configuration */
223 FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
224 (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
225 (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
226 (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
227 (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
228 ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) |
229 ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) |
230 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode;
231
232 /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */
233 if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable)
234 {
235 assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime));
236 assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime));
237 assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime));
238 assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision));
239 assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency));
240 assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
241
242 FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] =
243 (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
244 (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )|
245 (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
246 ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) |
247 ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) |
248 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode;
249 }
250 else
251 {
252 FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF;
253 }
254
255 }
256
257 /**
258 * @brief Fills each FMC_NORSRAMInitStruct member with its default value.
259 * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure
260 * which will be initialized.
261 * @retval None
262 */
FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef * FMC_NORSRAMInitStruct)263 void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
264 {
265 /* Reset NOR/SRAM Init structure parameters values */
266 FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1;
267 FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable;
268 FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM;
269 FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b;
270 FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
271 FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
272 FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
273 FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable;
274 FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
275 FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable;
276 FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable;
277 FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable;
278 FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable;
279 FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly;
280
281 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)&FMC_DefaultTimingStruct;
282 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)&FMC_DefaultTimingStruct;
283 }
284
285 /**
286 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
287 * @param FMC_Bank: specifies the FMC Bank to be used
288 * This parameter can be one of the following values:
289 * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
290 * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
291 * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
292 * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
293 * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
294 * @retval None
295 */
FMC_NORSRAMCmd(uint32_t FMC_Bank,FunctionalState NewState)296 void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState)
297 {
298 assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
299 assert_param(IS_FUNCTIONAL_STATE(NewState));
300
301 if (NewState != DISABLE)
302 {
303 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
304 FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET;
305 }
306 else
307 {
308 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
309 FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET;
310 }
311 }
312 /**
313 * @}
314 */
315
316 /** @defgroup FMC_Group2 NAND Controller functions
317 * @brief NAND Controller functions
318 *
319 @verbatim
320 ===============================================================================
321 ##### NAND Controller functions #####
322 ===============================================================================
323
324 [..] The following sequence should be followed to configure the FMC to interface
325 with 8-bit or 16-bit NAND memory connected to the NAND Bank:
326
327 (#) Enable the clock for the FMC and associated GPIOs using the following functions:
328 (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
329 (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
330
331 (#) FMC pins configuration
332 (++) Connect the involved FMC pins to AF12 using the following function
333 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
334 (++) Configure these FMC pins in alternate function mode by calling the function
335 GPIO_Init();
336
337 (#) Declare a FMC_NANDInitTypeDef structure, for example:
338 FMC_NANDInitTypeDef FMC_NANDInitStructure;
339 and fill the FMC_NANDInitStructure variable with the allowed values of
340 the structure member.
341
342 (#) Initialize the NAND Controller by calling the function
343 FMC_NANDInit(&FMC_NANDInitStructure);
344
345 (#) Then enable the NAND Bank, for example:
346 FMC_NANDCmd(FMC_Bank3_NAND, ENABLE);
347
348 (#) At this stage you can read/write from/to the memory connected to the NAND Bank.
349
350 [..]
351 (@) To enable the Error Correction Code (ECC), you have to use the function
352 FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE);
353 [..]
354 (@) and to get the current ECC value you have to use the function
355 ECCval = FMC_GetECC(FMC_Bank3_NAND);
356
357 @endverbatim
358 * @{
359 */
360
361 /**
362 * @brief De-initializes the FMC NAND Banks registers to their default reset values.
363 * @param FMC_Bank: specifies the FMC Bank to be used
364 * This parameter can be one of the following values:
365 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
366 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
367 * @retval None
368 */
FMC_NANDDeInit(uint32_t FMC_Bank)369 void FMC_NANDDeInit(uint32_t FMC_Bank)
370 {
371 /* Check the parameter */
372 assert_param(IS_FMC_NAND_BANK(FMC_Bank));
373
374 if(FMC_Bank == FMC_Bank2_NAND)
375 {
376 /* Set the FMC_Bank2 registers to their reset values */
377 FMC_Bank2->PCR2 = 0x00000018;
378 FMC_Bank2->SR2 = 0x00000040;
379 FMC_Bank2->PMEM2 = 0xFCFCFCFC;
380 FMC_Bank2->PATT2 = 0xFCFCFCFC;
381 }
382 /* FMC_Bank3_NAND */
383 else
384 {
385 /* Set the FMC_Bank3 registers to their reset values */
386 FMC_Bank3->PCR3 = 0x00000018;
387 FMC_Bank3->SR3 = 0x00000040;
388 FMC_Bank3->PMEM3 = 0xFCFCFCFC;
389 FMC_Bank3->PATT3 = 0xFCFCFCFC;
390 }
391 }
392
393 /**
394 * @brief Initializes the FMC NAND Banks according to the specified parameters
395 * in the FMC_NANDInitStruct.
396 * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that
397 * contains the configuration information for the FMC NAND specified Banks.
398 * @retval None
399 */
FMC_NANDInit(FMC_NANDInitTypeDef * FMC_NANDInitStruct)400 void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
401 {
402 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
403
404 /* Check the parameters */
405 assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank));
406 assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature));
407 assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth));
408 assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC));
409 assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize));
410 assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime));
411 assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime));
412 assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
413 assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
414 assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
415 assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
416 assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
417 assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
418 assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
419 assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
420
421 /* Set the tmppcr value according to FMC_NANDInitStruct parameters */
422 tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature |
423 PCR_MEMORYTYPE_NAND |
424 FMC_NANDInitStruct->FMC_MemoryDataWidth |
425 FMC_NANDInitStruct->FMC_ECC |
426 FMC_NANDInitStruct->FMC_ECCPageSize |
427 (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )|
428 (FMC_NANDInitStruct->FMC_TARSetupTime << 13);
429
430 /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
431 tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
432 (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
433 (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
434 (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
435
436 /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
437 tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
438 (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
439 (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
440 (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
441
442 if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
443 {
444 /* FMC_Bank2_NAND registers configuration */
445 FMC_Bank2->PCR2 = tmppcr;
446 FMC_Bank2->PMEM2 = tmppmem;
447 FMC_Bank2->PATT2 = tmppatt;
448 }
449 else
450 {
451 /* FMC_Bank3_NAND registers configuration */
452 FMC_Bank3->PCR3 = tmppcr;
453 FMC_Bank3->PMEM3 = tmppmem;
454 FMC_Bank3->PATT3 = tmppatt;
455 }
456 }
457
458
459 /**
460 * @brief Fills each FMC_NANDInitStruct member with its default value.
461 * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which
462 * will be initialized.
463 * @retval None
464 */
FMC_NANDStructInit(FMC_NANDInitTypeDef * FMC_NANDInitStruct)465 void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
466 {
467 /* Reset NAND Init structure parameters values */
468 FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND;
469 FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
470 FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b;
471 FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable;
472 FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes;
473 FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0;
474 FMC_NANDInitStruct->FMC_TARSetupTime = 0x0;
475 FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
476 FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
477 FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
478 FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
479 FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
480 FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
481 FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
482 FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
483 }
484
485 /**
486 * @brief Enables or disables the specified NAND Memory Bank.
487 * @param FMC_Bank: specifies the FMC Bank to be used
488 * This parameter can be one of the following values:
489 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
490 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
491 * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
492 * @retval None
493 */
FMC_NANDCmd(uint32_t FMC_Bank,FunctionalState NewState)494 void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState)
495 {
496 assert_param(IS_FMC_NAND_BANK(FMC_Bank));
497 assert_param(IS_FUNCTIONAL_STATE(NewState));
498
499 if (NewState != DISABLE)
500 {
501 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
502 if(FMC_Bank == FMC_Bank2_NAND)
503 {
504 FMC_Bank2->PCR2 |= PCR_PBKEN_SET;
505 }
506 else
507 {
508 FMC_Bank3->PCR3 |= PCR_PBKEN_SET;
509 }
510 }
511 else
512 {
513 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
514 if(FMC_Bank == FMC_Bank2_NAND)
515 {
516 FMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
517 }
518 else
519 {
520 FMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
521 }
522 }
523 }
524 /**
525 * @brief Enables or disables the FMC NAND ECC feature.
526 * @param FMC_Bank: specifies the FMC Bank to be used
527 * This parameter can be one of the following values:
528 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
529 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
530 * @param NewState: new state of the FMC NAND ECC feature.
531 * This parameter can be: ENABLE or DISABLE.
532 * @retval None
533 */
FMC_NANDECCCmd(uint32_t FMC_Bank,FunctionalState NewState)534 void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState)
535 {
536 assert_param(IS_FMC_NAND_BANK(FMC_Bank));
537 assert_param(IS_FUNCTIONAL_STATE(NewState));
538
539 if (NewState != DISABLE)
540 {
541 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
542 if(FMC_Bank == FMC_Bank2_NAND)
543 {
544 FMC_Bank2->PCR2 |= PCR_ECCEN_SET;
545 }
546 else
547 {
548 FMC_Bank3->PCR3 |= PCR_ECCEN_SET;
549 }
550 }
551 else
552 {
553 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
554 if(FMC_Bank == FMC_Bank2_NAND)
555 {
556 FMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
557 }
558 else
559 {
560 FMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
561 }
562 }
563 }
564
565 /**
566 * @brief Returns the error correction code register value.
567 * @param FMC_Bank: specifies the FMC Bank to be used
568 * This parameter can be one of the following values:
569 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
570 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
571 * @retval The Error Correction Code (ECC) value.
572 */
FMC_GetECC(uint32_t FMC_Bank)573 uint32_t FMC_GetECC(uint32_t FMC_Bank)
574 {
575 uint32_t eccval = 0x00000000;
576
577 if(FMC_Bank == FMC_Bank2_NAND)
578 {
579 /* Get the ECCR2 register value */
580 eccval = FMC_Bank2->ECCR2;
581 }
582 else
583 {
584 /* Get the ECCR3 register value */
585 eccval = FMC_Bank3->ECCR3;
586 }
587 /* Return the error correction code value */
588 return(eccval);
589 }
590 /**
591 * @}
592 */
593
594 /** @defgroup FMC_Group3 PCCARD Controller functions
595 * @brief PCCARD Controller functions
596 *
597 @verbatim
598 ===============================================================================
599 ##### PCCARD Controller functions #####
600 ===============================================================================
601
602 [..] he following sequence should be followed to configure the FMC to interface
603 with 16-bit PC Card compatible memory connected to the PCCARD Bank:
604
605 (#) Enable the clock for the FMC and associated GPIOs using the following functions:
606 (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
607 (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
608
609 (#) FMC pins configuration
610 (++) Connect the involved FMC pins to AF12 using the following function
611 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
612 (++) Configure these FMC pins in alternate function mode by calling the function
613 GPIO_Init();
614
615 (#) Declare a FMC_PCCARDInitTypeDef structure, for example:
616 FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure;
617 and fill the FMC_PCCARDInitStructure variable with the allowed values of
618 the structure member.
619
620 (#) Initialize the PCCARD Controller by calling the function
621 FMC_PCCARDInit(&FMC_PCCARDInitStructure);
622
623 (#) Then enable the PCCARD Bank:
624 FMC_PCCARDCmd(ENABLE);
625
626 (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.
627
628 @endverbatim
629 * @{
630 */
631
632 /**
633 * @brief De-initializes the FMC PCCARD Bank registers to their default reset values.
634 * @param None
635 * @retval None
636 */
FMC_PCCARDDeInit(void)637 void FMC_PCCARDDeInit(void)
638 {
639 /* Set the FMC_Bank4 registers to their reset values */
640 FMC_Bank4->PCR4 = 0x00000018;
641 FMC_Bank4->SR4 = 0x00000000;
642 FMC_Bank4->PMEM4 = 0xFCFCFCFC;
643 FMC_Bank4->PATT4 = 0xFCFCFCFC;
644 FMC_Bank4->PIO4 = 0xFCFCFCFC;
645 }
646
647 /**
648 * @brief Initializes the FMC PCCARD Bank according to the specified parameters
649 * in the FMC_PCCARDInitStruct.
650 * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure
651 * that contains the configuration information for the FMC PCCARD Bank.
652 * @retval None
653 */
FMC_PCCARDInit(FMC_PCCARDInitTypeDef * FMC_PCCARDInitStruct)654 void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
655 {
656 /* Check the parameters */
657 assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature));
658 assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime));
659 assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime));
660
661 assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
662 assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
663 assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
664 assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
665
666 assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
667 assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
668 assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
669 assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
670 assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime));
671 assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime));
672 assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime));
673 assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime));
674
675 /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */
676 FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature |
677 FMC_NAND_MemoryDataWidth_16b |
678 (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
679 (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
680
681 /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */
682 FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
683 (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
684 (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
685 (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
686
687 /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */
688 FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
689 (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
690 (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
691 (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
692
693 /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */
694 FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
695 (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
696 (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
697 (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
698 }
699
700 /**
701 * @brief Fills each FMC_PCCARDInitStruct member with its default value.
702 * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure
703 * which will be initialized.
704 * @retval None
705 */
FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef * FMC_PCCARDInitStruct)706 void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
707 {
708 /* Reset PCCARD Init structure parameters values */
709 FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
710 FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0;
711 FMC_PCCARDInitStruct->FMC_TARSetupTime = 0;
712 FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
713 FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
714 FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
715 FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
716 FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
717 FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
718 FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
719 FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
720 FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252;
721 FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252;
722 FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252;
723 FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252;
724 }
725
726 /**
727 * @brief Enables or disables the PCCARD Memory Bank.
728 * @param NewState: new state of the PCCARD Memory Bank.
729 * This parameter can be: ENABLE or DISABLE.
730 * @retval None
731 */
FMC_PCCARDCmd(FunctionalState NewState)732 void FMC_PCCARDCmd(FunctionalState NewState)
733 {
734 assert_param(IS_FUNCTIONAL_STATE(NewState));
735
736 if (NewState != DISABLE)
737 {
738 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
739 FMC_Bank4->PCR4 |= PCR_PBKEN_SET;
740 }
741 else
742 {
743 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
744 FMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
745 }
746 }
747
748 /**
749 * @}
750 */
751
752 /** @defgroup FMC_Group4 SDRAM Controller functions
753 * @brief SDRAM Controller functions
754 *
755 @verbatim
756 ===============================================================================
757 ##### SDRAM Controller functions #####
758 ===============================================================================
759
760 [..] The following sequence should be followed to configure the FMC to interface
761 with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2:
762
763 (#) Enable the clock for the FMC and associated GPIOs using the following functions:
764 (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
765 (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
766
767 (#) FMC pins configuration
768 (++) Connect the involved FMC pins to AF12 using the following function
769 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
770 (++) Configure these FMC pins in alternate function mode by calling the function
771 GPIO_Init();
772
773 (#) Declare a FMC_SDRAMInitTypeDef structure, for example:
774 FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
775 and fill the FMC_SDRAMInitStructure variable with the allowed values of
776 the structure member.
777
778 (#) Initialize the SDRAM Controller by calling the function
779 FMC_SDRAMInit(&FMC_SDRAMInitStructure);
780
781 (#) Declare a FMC_SDRAMCommandTypeDef structure, for example:
782 FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
783 and fill the FMC_SDRAMCommandStructure variable with the allowed values of
784 the structure member.
785
786 (#) Configure the SDCMR register with the desired command parameters by calling
787 the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
788
789 (#) At this stage, the SDRAM memory is ready for any valid command.
790
791 @endverbatim
792 * @{
793 */
794
795 /**
796 * @brief De-initializes the FMC SDRAM Banks registers to their default
797 * reset values.
798 * @param FMC_Bank: specifies the FMC Bank to be used
799 * This parameter can be one of the following values:
800 * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
801 * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
802 * @retval None
803 */
FMC_SDRAMDeInit(uint32_t FMC_Bank)804 void FMC_SDRAMDeInit(uint32_t FMC_Bank)
805 {
806 /* Check the parameter */
807 assert_param(IS_FMC_SDRAM_BANK(FMC_Bank));
808
809 FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0;
810 FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF;
811 FMC_Bank5_6->SDCMR = 0x00000000;
812 FMC_Bank5_6->SDRTR = 0x00000000;
813 FMC_Bank5_6->SDSR = 0x00000000;
814 }
815
816 /**
817 * @brief Initializes the FMC SDRAM Banks according to the specified
818 * parameters in the FMC_SDRAMInitStruct.
819 * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure
820 * that contains the configuration information for the FMC SDRAM
821 * specified Banks.
822 * @retval None
823 */
FMC_SDRAMInit(FMC_SDRAMInitTypeDef * FMC_SDRAMInitStruct)824 void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
825 {
826 /* temporary registers */
827 uint32_t tmpr1 = 0;
828 uint32_t tmpr2 = 0;
829 uint32_t tmpr3 = 0;
830 uint32_t tmpr4 = 0;
831
832 /* Check the parameters */
833
834 /* Control parameters */
835 assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank));
836 assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber));
837 assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber));
838 assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth));
839 assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber));
840 assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency));
841 assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection));
842 assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod));
843 assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst));
844 assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay));
845
846 /* Timing parameters */
847 assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay));
848 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay));
849 assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime));
850 assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay));
851 assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime));
852 assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay));
853 assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay));
854
855 /* SDRAM bank control register configuration */
856 tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
857 FMC_SDRAMInitStruct->FMC_RowBitsNumber |
858 FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
859 FMC_SDRAMInitStruct->FMC_InternalBankNumber |
860 FMC_SDRAMInitStruct->FMC_CASLatency |
861 FMC_SDRAMInitStruct->FMC_WriteProtection |
862 FMC_SDRAMInitStruct->FMC_SDClockPeriod |
863 FMC_SDRAMInitStruct->FMC_ReadBurst |
864 FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
865
866 if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
867 {
868 FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
869 }
870 else /* SDCR2 "don't care" bits configuration */
871 {
872 tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
873 FMC_SDRAMInitStruct->FMC_ReadBurst |
874 FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
875
876 FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3;
877 FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
878 }
879 /* SDRAM bank timing register configuration */
880 if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
881 {
882 tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
883 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
884 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
885 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
886 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |
887 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |
888 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);
889
890 FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
891 }
892 else /* SDTR "don't care bits configuration */
893 {
894 tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
895 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
896 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
897 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
898
899 tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
900 (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
901
902 FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;
903 FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
904 }
905
906 }
907
908 /**
909 * @brief Fills each FMC_SDRAMInitStruct member with its default value.
910 * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure
911 * which will be initialized.
912 * @retval None
913 */
FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef * FMC_SDRAMInitStruct)914 void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
915 {
916 /* Reset SDRAM Init structure parameters values */
917 FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM;
918 FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
919 FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b;
920 FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
921 FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4;
922 FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1;
923 FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable;
924 FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable;
925 FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable;
926 FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0;
927
928 FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16;
929 FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16;
930 FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16;
931 FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16;
932 FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16;
933 FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16;
934 FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16;
935
936 }
937
938 /**
939 * @brief Configures the SDRAM memory command issued when the device is accessed.
940 * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure
941 * which will be configured.
942 * @retval None
943 */
FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef * FMC_SDRAMCommandStruct)944 void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
945 {
946 uint32_t tmpr = 0x0;
947
948 /* check parameters */
949 assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode));
950 assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget));
951 assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber));
952 assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition));
953
954 tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode |
955 FMC_SDRAMCommandStruct->FMC_CommandTarget |
956 (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) |
957 ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9));
958
959 FMC_Bank5_6->SDCMR = tmpr;
960
961 }
962
963
964 /**
965 * @brief Returns the indicated FMC SDRAM bank mode status.
966 * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
967 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
968 * @retval The FMC SDRAM bank mode status
969 */
FMC_GetModeStatus(uint32_t SDRAM_Bank)970 uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
971 {
972 uint32_t tmpreg = 0;
973
974 /* Check the parameter */
975 assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
976
977 /* Get the busy flag status */
978 if(SDRAM_Bank == FMC_Bank1_SDRAM)
979 {
980 tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
981 }
982 else
983 {
984 tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
985 }
986
987 /* Return the mode status */
988 return tmpreg;
989 }
990
991 /**
992 * @brief defines the SDRAM Memory Refresh rate.
993 * @param FMC_Count: specifies the Refresh timer count.
994 * @retval None
995 */
FMC_SetRefreshCount(uint32_t FMC_Count)996 void FMC_SetRefreshCount(uint32_t FMC_Count)
997 {
998 /* check the parameters */
999 assert_param(IS_FMC_REFRESH_COUNT(FMC_Count));
1000
1001 FMC_Bank5_6->SDRTR |= (FMC_Count<<1);
1002
1003 }
1004
1005 /**
1006 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1007 * @param FMC_Number: specifies the auto Refresh number.
1008 * @retval None
1009 */
FMC_SetAutoRefresh_Number(uint32_t FMC_Number)1010 void FMC_SetAutoRefresh_Number(uint32_t FMC_Number)
1011 {
1012 /* check the parameters */
1013 assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number));
1014
1015 FMC_Bank5_6->SDCMR |= (FMC_Number << 5);
1016 }
1017
1018 /**
1019 * @brief Enables or disables write protection to the specified FMC SDRAM Bank.
1020 * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
1021 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1022 * @param NewState: new state of the write protection flag.
1023 * This parameter can be: ENABLE or DISABLE.
1024 * @retval None
1025 */
FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank,FunctionalState NewState)1026 void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState)
1027 {
1028 /* Check the parameter */
1029 assert_param(IS_FUNCTIONAL_STATE(NewState));
1030 assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
1031
1032 if (NewState != DISABLE)
1033 {
1034 FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable;
1035 }
1036 else
1037 {
1038 FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET;
1039 }
1040
1041 }
1042
1043 /**
1044 * @}
1045 */
1046
1047 /** @defgroup FMC_Group5 Interrupts and flags management functions
1048 * @brief Interrupts and flags management functions
1049 *
1050 @verbatim
1051 ===============================================================================
1052 ##### Interrupts and flags management functions #####
1053 ===============================================================================
1054
1055 @endverbatim
1056 * @{
1057 */
1058
1059 /**
1060 * @brief Enables or disables the specified FMC interrupts.
1061 * @param FMC_Bank: specifies the FMC Bank to be used
1062 * This parameter can be one of the following values:
1063 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
1064 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
1065 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
1066 * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
1067 * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
1068 * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled.
1069 * This parameter can be any combination of the following values:
1070 * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
1071 * @arg FMC_IT_Level: Level edge detection interrupt.
1072 * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
1073 * @arg FMC_IT_Refresh: Refresh error detection interrupt.
1074 * @param NewState: new state of the specified FMC interrupts.
1075 * This parameter can be: ENABLE or DISABLE.
1076 * @retval None
1077 */
FMC_ITConfig(uint32_t FMC_Bank,uint32_t FMC_IT,FunctionalState NewState)1078 void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
1079 {
1080 assert_param(IS_FMC_IT_BANK(FMC_Bank));
1081 assert_param(IS_FMC_IT(FMC_IT));
1082 assert_param(IS_FUNCTIONAL_STATE(NewState));
1083
1084 if (NewState != DISABLE)
1085 {
1086 /* Enable the selected FMC_Bank2 interrupts */
1087 if(FMC_Bank == FMC_Bank2_NAND)
1088 {
1089 FMC_Bank2->SR2 |= FMC_IT;
1090 }
1091 /* Enable the selected FMC_Bank3 interrupts */
1092 else if (FMC_Bank == FMC_Bank3_NAND)
1093 {
1094 FMC_Bank3->SR3 |= FMC_IT;
1095 }
1096 /* Enable the selected FMC_Bank4 interrupts */
1097 else if (FMC_Bank == FMC_Bank4_PCCARD)
1098 {
1099 FMC_Bank4->SR4 |= FMC_IT;
1100 }
1101 /* Enable the selected FMC_Bank5_6 interrupt */
1102 else
1103 {
1104 /* Enables the interrupt if the refresh error flag is set */
1105 FMC_Bank5_6->SDRTR |= FMC_IT;
1106 }
1107 }
1108 else
1109 {
1110 /* Disable the selected FMC_Bank2 interrupts */
1111 if(FMC_Bank == FMC_Bank2_NAND)
1112 {
1113
1114 FMC_Bank2->SR2 &= (uint32_t)~FMC_IT;
1115 }
1116 /* Disable the selected FMC_Bank3 interrupts */
1117 else if (FMC_Bank == FMC_Bank3_NAND)
1118 {
1119 FMC_Bank3->SR3 &= (uint32_t)~FMC_IT;
1120 }
1121 /* Disable the selected FMC_Bank4 interrupts */
1122 else if(FMC_Bank == FMC_Bank4_PCCARD)
1123 {
1124 FMC_Bank4->SR4 &= (uint32_t)~FMC_IT;
1125 }
1126 /* Disable the selected FMC_Bank5_6 interrupt */
1127 else
1128 {
1129 /* Disables the interrupt if the refresh error flag is not set */
1130 FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT;
1131 }
1132 }
1133 }
1134
1135 /**
1136 * @brief Checks whether the specified FMC flag is set or not.
1137 * @param FMC_Bank: specifies the FMC Bank to be used
1138 * This parameter can be one of the following values:
1139 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
1140 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
1141 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
1142 * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
1143 * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
1144 * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM
1145 * @param FMC_FLAG: specifies the flag to check.
1146 * This parameter can be one of the following values:
1147 * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
1148 * @arg FMC_FLAG_Level: Level detection Flag.
1149 * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
1150 * @arg FMC_FLAG_FEMPT: Fifo empty Flag.
1151 * @arg FMC_FLAG_Refresh: Refresh error Flag.
1152 * @arg FMC_FLAG_Busy: Busy status Flag.
1153 * @retval The new state of FMC_FLAG (SET or RESET).
1154 */
FMC_GetFlagStatus(uint32_t FMC_Bank,uint32_t FMC_FLAG)1155 FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG)
1156 {
1157 FlagStatus bitstatus = RESET;
1158 uint32_t tmpsr = 0x00000000;
1159
1160 /* Check the parameters */
1161 assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
1162 assert_param(IS_FMC_GET_FLAG(FMC_FLAG));
1163
1164 if(FMC_Bank == FMC_Bank2_NAND)
1165 {
1166 tmpsr = FMC_Bank2->SR2;
1167 }
1168 else if(FMC_Bank == FMC_Bank3_NAND)
1169 {
1170 tmpsr = FMC_Bank3->SR3;
1171 }
1172 else if(FMC_Bank == FMC_Bank4_PCCARD)
1173 {
1174 tmpsr = FMC_Bank4->SR4;
1175 }
1176 else
1177 {
1178 tmpsr = FMC_Bank5_6->SDSR;
1179 }
1180
1181 /* Get the flag status */
1182 if ((tmpsr & FMC_FLAG) != FMC_FLAG )
1183 {
1184 bitstatus = RESET;
1185 }
1186 else
1187 {
1188 bitstatus = SET;
1189 }
1190 /* Return the flag status */
1191 return bitstatus;
1192 }
1193
1194 /**
1195 * @brief Clears the FMC's pending flags.
1196 * @param FMC_Bank: specifies the FMC Bank to be used
1197 * This parameter can be one of the following values:
1198 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
1199 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
1200 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
1201 * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
1202 * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
1203 * @param FMC_FLAG: specifies the flag to clear.
1204 * This parameter can be any combination of the following values:
1205 * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
1206 * @arg FMC_FLAG_Level: Level detection Flag.
1207 * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
1208 * @arg FMC_FLAG_Refresh: Refresh error Flag.
1209 * @retval None
1210 */
FMC_ClearFlag(uint32_t FMC_Bank,uint32_t FMC_FLAG)1211 void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG)
1212 {
1213 /* Check the parameters */
1214 assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
1215 assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ;
1216
1217 if(FMC_Bank == FMC_Bank2_NAND)
1218 {
1219 FMC_Bank2->SR2 &= (~FMC_FLAG);
1220 }
1221 else if(FMC_Bank == FMC_Bank3_NAND)
1222 {
1223 FMC_Bank3->SR3 &= (~FMC_FLAG);
1224 }
1225 else if(FMC_Bank == FMC_Bank4_PCCARD)
1226 {
1227 FMC_Bank4->SR4 &= (~FMC_FLAG);
1228 }
1229 /* FMC_Bank5_6 SDRAM*/
1230 else
1231 {
1232 FMC_Bank5_6->SDRTR &= (~FMC_FLAG);
1233 }
1234
1235 }
1236
1237 /**
1238 * @brief Checks whether the specified FMC interrupt has occurred or not.
1239 * @param FMC_Bank: specifies the FMC Bank to be used
1240 * This parameter can be one of the following values:
1241 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
1242 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
1243 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
1244 * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
1245 * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
1246 * @param FMC_IT: specifies the FMC interrupt source to check.
1247 * This parameter can be one of the following values:
1248 * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
1249 * @arg FMC_IT_Level: Level edge detection interrupt.
1250 * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
1251 * @arg FMC_IT_Refresh: Refresh error detection interrupt.
1252 * @retval The new state of FMC_IT (SET or RESET).
1253 */
FMC_GetITStatus(uint32_t FMC_Bank,uint32_t FMC_IT)1254 ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
1255 {
1256 ITStatus bitstatus = RESET;
1257 uint32_t tmpsr = 0x0;
1258 uint32_t tmpsr2 = 0x0;
1259 uint32_t itstatus = 0x0;
1260 uint32_t itenable = 0x0;
1261
1262 /* Check the parameters */
1263 assert_param(IS_FMC_IT_BANK(FMC_Bank));
1264 assert_param(IS_FMC_GET_IT(FMC_IT));
1265
1266 if(FMC_Bank == FMC_Bank2_NAND)
1267 {
1268 tmpsr = FMC_Bank2->SR2;
1269 }
1270 else if(FMC_Bank == FMC_Bank3_NAND)
1271 {
1272 tmpsr = FMC_Bank3->SR3;
1273 }
1274 else if(FMC_Bank == FMC_Bank4_PCCARD)
1275 {
1276 tmpsr = FMC_Bank4->SR4;
1277 }
1278 /* FMC_Bank5_6 SDRAM*/
1279 else
1280 {
1281 tmpsr = FMC_Bank5_6->SDRTR;
1282 tmpsr2 = FMC_Bank5_6->SDSR;
1283 }
1284
1285 /* get the IT enable bit status*/
1286 itenable = tmpsr & FMC_IT;
1287
1288 /* get the corresponding IT Flag status*/
1289 if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM))
1290 {
1291 itstatus = tmpsr2 & FMC_SDSR_RE;
1292 }
1293 else
1294 {
1295 itstatus = tmpsr & (FMC_IT >> 3);
1296 }
1297
1298 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
1299 {
1300 bitstatus = SET;
1301 }
1302 else
1303 {
1304 bitstatus = RESET;
1305 }
1306 return bitstatus;
1307 }
1308
1309 /**
1310 * @brief Clears the FMC's interrupt pending bits.
1311 * @param FMC_Bank: specifies the FMC Bank to be used
1312 * This parameter can be one of the following values:
1313 * @arg FMC_Bank2_NAND: FMC Bank2 NAND
1314 * @arg FMC_Bank3_NAND: FMC Bank3 NAND
1315 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
1316 * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
1317 * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
1318 * @param FMC_IT: specifies the interrupt pending bit to clear.
1319 * This parameter can be any combination of the following values:
1320 * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
1321 * @arg FMC_IT_Level: Level edge detection interrupt.
1322 * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
1323 * @arg FMC_IT_Refresh: Refresh error detection interrupt.
1324 * @retval None
1325 */
FMC_ClearITPendingBit(uint32_t FMC_Bank,uint32_t FMC_IT)1326 void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT)
1327 {
1328 /* Check the parameters */
1329 assert_param(IS_FMC_IT_BANK(FMC_Bank));
1330 assert_param(IS_FMC_IT(FMC_IT));
1331
1332 if(FMC_Bank == FMC_Bank2_NAND)
1333 {
1334 FMC_Bank2->SR2 &= ~(FMC_IT >> 3);
1335 }
1336 else if(FMC_Bank == FMC_Bank3_NAND)
1337 {
1338 FMC_Bank3->SR3 &= ~(FMC_IT >> 3);
1339 }
1340 else if(FMC_Bank == FMC_Bank4_PCCARD)
1341 {
1342 FMC_Bank4->SR4 &= ~(FMC_IT >> 3);
1343 }
1344 /* FMC_Bank5_6 SDRAM*/
1345 else
1346 {
1347 FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE;
1348 }
1349 }
1350
1351 /**
1352 * @}
1353 */
1354
1355 /**
1356 * @}
1357 */
1358
1359 /**
1360 * @}
1361 */
1362
1363 /**
1364 * @}
1365 */
1366
1367 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1368