1 /**
2 ******************************************************************************
3 * @file stm32f4xx_fsmc.c
4 * @author MCD Application Team
5 * @version V1.4.0
6 * @date 04-August-2014
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the FSMC peripheral:
9 * + Interface with SRAM, PSRAM, NOR and OneNAND memories
10 * + Interface with NAND memories
11 * + Interface with 16-bit PC Card compatible memories
12 * + Interrupts and flags management
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
18 *
19 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
20 * You may not use this file except in compliance with the License.
21 * You may obtain a copy of the License at:
22 *
23 * http://www.st.com/software_license_agreement_liberty_v2
24 *
25 * Unless required by applicable law or agreed to in writing, software
26 * distributed under the License is distributed on an "AS IS" BASIS,
27 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
28 * See the License for the specific language governing permissions and
29 * limitations under the License.
30 *
31 ******************************************************************************
32 */
33
34 /* Includes ------------------------------------------------------------------*/
35 #include "stm32f4xx_fsmc.h"
36 #include "stm32f4xx_rcc.h"
37 // #include "stm32f4xx.h"
38
39 /** @addtogroup STM32F4xx_StdPeriph_Driver
40 * @{
41 */
42
43 /** @defgroup FSMC
44 * @brief FSMC driver modules
45 * @{
46 */
47
48 /* Private typedef -----------------------------------------------------------*/
49 const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct = {0x0F, /* FSMC_AddressSetupTime */
50 0x0F, /* FSMC_AddressHoldTime */
51 0xFF, /* FSMC_DataSetupTime */
52 0x0F, /* FSMC_BusTurnAroundDuration */
53 0x0F, /* FSMC_CLKDivision */
54 0x0F, /* FSMC_DataLatency */
55 FSMC_AccessMode_A /* FSMC_AccessMode */
56 };
57 /* Private define ------------------------------------------------------------*/
58
59 /* --------------------- FSMC registers bit mask ---------------------------- */
60 /* FSMC BCRx Mask */
61 #define BCR_MBKEN_SET ((uint32_t)0x00000001)
62 #define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
63 #define BCR_FACCEN_SET ((uint32_t)0x00000040)
64
65 /* FSMC PCRx Mask */
66 #define PCR_PBKEN_SET ((uint32_t)0x00000004)
67 #define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
68 #define PCR_ECCEN_SET ((uint32_t)0x00000040)
69 #define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
70 #define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
71
72 /* Private macro -------------------------------------------------------------*/
73 /* Private variables ---------------------------------------------------------*/
74 /* Private function prototypes -----------------------------------------------*/
75 /* Private functions ---------------------------------------------------------*/
76
77 /** @defgroup FSMC_Private_Functions
78 * @{
79 */
80
81 /** @defgroup FSMC_Group1 NOR/SRAM Controller functions
82 * @brief NOR/SRAM Controller functions
83 *
84 @verbatim
85 ===============================================================================
86 ##### NOR and SRAM Controller functions #####
87 ===============================================================================
88
89 [..] The following sequence should be followed to configure the FSMC to interface
90 with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
91
92 (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
93 RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
94 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
95
96 (#) FSMC pins configuration
97 (++) Connect the involved FSMC pins to AF12 using the following function
98 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
99 (++) Configure these FSMC pins in alternate function mode by calling the function
100 GPIO_Init();
101
102 (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
103 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
104 and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
105 the structure member.
106
107 (#) Initialize the NOR/SRAM Controller by calling the function
108 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
109
110 (#) Then enable the NOR/SRAM Bank, for example:
111 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
112
113 (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
114
115 @endverbatim
116 * @{
117 */
118
119 /**
120 * @brief De-initializes the FSMC NOR/SRAM Banks registers to their default
121 * reset values.
122 * @param FSMC_Bank: specifies the FSMC Bank to be used
123 * This parameter can be one of the following values:
124 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
125 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
126 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
127 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
128 * @retval None
129 */
FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)130 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
131 {
132 /* Check the parameter */
133 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
134
135 /* FSMC_Bank1_NORSRAM1 */
136 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
137 {
138 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
139 }
140 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
141 else
142 {
143 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
144 }
145 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
146 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
147 }
148
149 /**
150 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
151 * parameters in the FSMC_NORSRAMInitStruct.
152 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
153 * that contains the configuration information for the FSMC NOR/SRAM
154 * specified Banks.
155 * @retval None
156 */
FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct)157 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
158 {
159 /* Check the parameters */
160 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
161 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
162 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
163 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
164 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
165 assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
166 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
167 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
168 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
169 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
170 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
171 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
172 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
173 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
174 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
175 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
176 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
177 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
178 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
179 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
180
181 /* Bank1 NOR/SRAM control register configuration */
182 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
183 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
184 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
185 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
186 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
187 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
188 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
189 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
190 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
191 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
192 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
193 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
194 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
195 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
196 {
197 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
198 }
199 /* Bank1 NOR/SRAM timing register configuration */
200 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
201 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
202 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
203 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
204 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
205 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
206 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
207 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
208
209
210 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
211 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
212 {
213 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
214 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
215 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
216 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
217 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
218 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
219 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
220 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
221 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
222 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
223 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
224 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
225 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
226 }
227 else
228 {
229 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
230 }
231 }
232
233 /**
234 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
235 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure
236 * which will be initialized.
237 * @retval None
238 */
FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct)239 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
240 {
241 /* Reset NOR/SRAM Init structure parameters values */
242 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
243 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
244 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
245 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
246 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
247 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
248 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
249 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
250 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
251 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
252 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
253 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
254 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
255 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct;
256 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct;
257 }
258
259 /**
260 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
261 * @param FSMC_Bank: specifies the FSMC Bank to be used
262 * This parameter can be one of the following values:
263 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
264 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
265 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
266 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
267 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
268 * @retval None
269 */
FSMC_NORSRAMCmd(uint32_t FSMC_Bank,FunctionalState NewState)270 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
271 {
272 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
273 assert_param(IS_FUNCTIONAL_STATE(NewState));
274
275 if (NewState != DISABLE)
276 {
277 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
278 FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
279 }
280 else
281 {
282 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
283 FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
284 }
285 }
286 /**
287 * @}
288 */
289
290 /** @defgroup FSMC_Group2 NAND Controller functions
291 * @brief NAND Controller functions
292 *
293 @verbatim
294 ===============================================================================
295 ##### NAND Controller functions #####
296 ===============================================================================
297
298 [..] The following sequence should be followed to configure the FSMC to interface
299 with 8-bit or 16-bit NAND memory connected to the NAND Bank:
300
301 (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
302 (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
303 (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
304
305 (#) FSMC pins configuration
306 (++) Connect the involved FSMC pins to AF12 using the following function
307 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
308 (++) Configure these FSMC pins in alternate function mode by calling the function
309 GPIO_Init();
310
311 (#) Declare a FSMC_NANDInitTypeDef structure, for example:
312 FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
313 and fill the FSMC_NANDInitStructure variable with the allowed values of
314 the structure member.
315
316 (#) Initialize the NAND Controller by calling the function
317 FSMC_NANDInit(&FSMC_NANDInitStructure);
318
319 (#) Then enable the NAND Bank, for example:
320 FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);
321
322 (#) At this stage you can read/write from/to the memory connected to the NAND Bank.
323
324 [..]
325 (@) To enable the Error Correction Code (ECC), you have to use the function
326 FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);
327 [..]
328 (@) and to get the current ECC value you have to use the function
329 ECCval = FSMC_GetECC(FSMC_Bank3_NAND);
330
331 @endverbatim
332 * @{
333 */
334
335 /**
336 * @brief De-initializes the FSMC NAND Banks registers to their default reset values.
337 * @param FSMC_Bank: specifies the FSMC Bank to be used
338 * This parameter can be one of the following values:
339 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
340 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
341 * @retval None
342 */
FSMC_NANDDeInit(uint32_t FSMC_Bank)343 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
344 {
345 /* Check the parameter */
346 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
347
348 if(FSMC_Bank == FSMC_Bank2_NAND)
349 {
350 /* Set the FSMC_Bank2 registers to their reset values */
351 FSMC_Bank2->PCR2 = 0x00000018;
352 FSMC_Bank2->SR2 = 0x00000040;
353 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
354 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
355 }
356 /* FSMC_Bank3_NAND */
357 else
358 {
359 /* Set the FSMC_Bank3 registers to their reset values */
360 FSMC_Bank3->PCR3 = 0x00000018;
361 FSMC_Bank3->SR3 = 0x00000040;
362 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
363 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
364 }
365 }
366
367 /**
368 * @brief Initializes the FSMC NAND Banks according to the specified parameters
369 * in the FSMC_NANDInitStruct.
370 * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
371 * contains the configuration information for the FSMC NAND specified Banks.
372 * @retval None
373 */
FSMC_NANDInit(FSMC_NANDInitTypeDef * FSMC_NANDInitStruct)374 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
375 {
376 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
377
378 /* Check the parameters */
379 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
380 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
381 assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
382 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
383 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
384 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
385 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
386 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
387 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
388 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
389 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
390 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
391 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
392 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
393 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
394
395 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
396 tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
397 PCR_MEMORYTYPE_NAND |
398 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
399 FSMC_NANDInitStruct->FSMC_ECC |
400 FSMC_NANDInitStruct->FSMC_ECCPageSize |
401 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
402 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
403
404 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
405 tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
406 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
407 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
408 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
409
410 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
411 tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
412 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
413 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
414 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
415
416 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
417 {
418 /* FSMC_Bank2_NAND registers configuration */
419 FSMC_Bank2->PCR2 = tmppcr;
420 FSMC_Bank2->PMEM2 = tmppmem;
421 FSMC_Bank2->PATT2 = tmppatt;
422 }
423 else
424 {
425 /* FSMC_Bank3_NAND registers configuration */
426 FSMC_Bank3->PCR3 = tmppcr;
427 FSMC_Bank3->PMEM3 = tmppmem;
428 FSMC_Bank3->PATT3 = tmppatt;
429 }
430 }
431
432
433 /**
434 * @brief Fills each FSMC_NANDInitStruct member with its default value.
435 * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
436 * will be initialized.
437 * @retval None
438 */
FSMC_NANDStructInit(FSMC_NANDInitTypeDef * FSMC_NANDInitStruct)439 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
440 {
441 /* Reset NAND Init structure parameters values */
442 FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
443 FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
444 FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
445 FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
446 FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
447 FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
448 FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
449 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
450 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
451 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
452 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
453 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
454 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
455 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
456 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
457 }
458
459 /**
460 * @brief Enables or disables the specified NAND Memory Bank.
461 * @param FSMC_Bank: specifies the FSMC Bank to be used
462 * This parameter can be one of the following values:
463 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
464 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
465 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
466 * @retval None
467 */
FSMC_NANDCmd(uint32_t FSMC_Bank,FunctionalState NewState)468 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
469 {
470 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
471 assert_param(IS_FUNCTIONAL_STATE(NewState));
472
473 if (NewState != DISABLE)
474 {
475 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
476 if(FSMC_Bank == FSMC_Bank2_NAND)
477 {
478 FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
479 }
480 else
481 {
482 FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
483 }
484 }
485 else
486 {
487 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
488 if(FSMC_Bank == FSMC_Bank2_NAND)
489 {
490 FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
491 }
492 else
493 {
494 FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
495 }
496 }
497 }
498 /**
499 * @brief Enables or disables the FSMC NAND ECC feature.
500 * @param FSMC_Bank: specifies the FSMC Bank to be used
501 * This parameter can be one of the following values:
502 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
503 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
504 * @param NewState: new state of the FSMC NAND ECC feature.
505 * This parameter can be: ENABLE or DISABLE.
506 * @retval None
507 */
FSMC_NANDECCCmd(uint32_t FSMC_Bank,FunctionalState NewState)508 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
509 {
510 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
511 assert_param(IS_FUNCTIONAL_STATE(NewState));
512
513 if (NewState != DISABLE)
514 {
515 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
516 if(FSMC_Bank == FSMC_Bank2_NAND)
517 {
518 FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
519 }
520 else
521 {
522 FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
523 }
524 }
525 else
526 {
527 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
528 if(FSMC_Bank == FSMC_Bank2_NAND)
529 {
530 FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
531 }
532 else
533 {
534 FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
535 }
536 }
537 }
538
539 /**
540 * @brief Returns the error correction code register value.
541 * @param FSMC_Bank: specifies the FSMC Bank to be used
542 * This parameter can be one of the following values:
543 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
544 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
545 * @retval The Error Correction Code (ECC) value.
546 */
FSMC_GetECC(uint32_t FSMC_Bank)547 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
548 {
549 uint32_t eccval = 0x00000000;
550
551 if(FSMC_Bank == FSMC_Bank2_NAND)
552 {
553 /* Get the ECCR2 register value */
554 eccval = FSMC_Bank2->ECCR2;
555 }
556 else
557 {
558 /* Get the ECCR3 register value */
559 eccval = FSMC_Bank3->ECCR3;
560 }
561 /* Return the error correction code value */
562 return(eccval);
563 }
564 /**
565 * @}
566 */
567
568 /** @defgroup FSMC_Group3 PCCARD Controller functions
569 * @brief PCCARD Controller functions
570 *
571 @verbatim
572 ===============================================================================
573 ##### PCCARD Controller functions #####
574 ===============================================================================
575
576 [..] he following sequence should be followed to configure the FSMC to interface
577 with 16-bit PC Card compatible memory connected to the PCCARD Bank:
578
579 (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
580 (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
581 (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
582
583 (#) FSMC pins configuration
584 (++) Connect the involved FSMC pins to AF12 using the following function
585 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
586 (++) Configure these FSMC pins in alternate function mode by calling the function
587 GPIO_Init();
588
589 (#) Declare a FSMC_PCCARDInitTypeDef structure, for example:
590 FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure;
591 and fill the FSMC_PCCARDInitStructure variable with the allowed values of
592 the structure member.
593
594 (#) Initialize the PCCARD Controller by calling the function
595 FSMC_PCCARDInit(&FSMC_PCCARDInitStructure);
596
597 (#) Then enable the PCCARD Bank:
598 FSMC_PCCARDCmd(ENABLE);
599
600 (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.
601
602 @endverbatim
603 * @{
604 */
605
606 /**
607 * @brief De-initializes the FSMC PCCARD Bank registers to their default reset values.
608 * @param None
609 * @retval None
610 */
FSMC_PCCARDDeInit(void)611 void FSMC_PCCARDDeInit(void)
612 {
613 /* Set the FSMC_Bank4 registers to their reset values */
614 FSMC_Bank4->PCR4 = 0x00000018;
615 FSMC_Bank4->SR4 = 0x00000000;
616 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
617 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
618 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
619 }
620
621 /**
622 * @brief Initializes the FSMC PCCARD Bank according to the specified parameters
623 * in the FSMC_PCCARDInitStruct.
624 * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
625 * that contains the configuration information for the FSMC PCCARD Bank.
626 * @retval None
627 */
FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct)628 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
629 {
630 /* Check the parameters */
631 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
632 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
633 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
634
635 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
636 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
637 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
638 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
639
640 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
641 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
642 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
643 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
644 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
645 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
646 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
647 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
648
649 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
650 FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
651 FSMC_MemoryDataWidth_16b |
652 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
653 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
654
655 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
656 FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
657 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
658 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
659 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
660
661 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
662 FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
663 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
664 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
665 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
666
667 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
668 FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
669 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
670 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
671 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
672 }
673
674 /**
675 * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
676 * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
677 * which will be initialized.
678 * @retval None
679 */
FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct)680 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
681 {
682 /* Reset PCCARD Init structure parameters values */
683 FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
684 FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
685 FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
686 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
687 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
688 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
689 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
690 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
691 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
692 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
693 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
694 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
695 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
696 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
697 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
698 }
699
700 /**
701 * @brief Enables or disables the PCCARD Memory Bank.
702 * @param NewState: new state of the PCCARD Memory Bank.
703 * This parameter can be: ENABLE or DISABLE.
704 * @retval None
705 */
FSMC_PCCARDCmd(FunctionalState NewState)706 void FSMC_PCCARDCmd(FunctionalState NewState)
707 {
708 assert_param(IS_FUNCTIONAL_STATE(NewState));
709
710 if (NewState != DISABLE)
711 {
712 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
713 FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
714 }
715 else
716 {
717 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
718 FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
719 }
720 }
721 /**
722 * @}
723 */
724
725 /** @defgroup FSMC_Group4 Interrupts and flags management functions
726 * @brief Interrupts and flags management functions
727 *
728 @verbatim
729 ===============================================================================
730 ##### Interrupts and flags management functions #####
731 ===============================================================================
732
733 @endverbatim
734 * @{
735 */
736
737 /**
738 * @brief Enables or disables the specified FSMC interrupts.
739 * @param FSMC_Bank: specifies the FSMC Bank to be used
740 * This parameter can be one of the following values:
741 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
742 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
743 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
744 * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
745 * This parameter can be any combination of the following values:
746 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
747 * @arg FSMC_IT_Level: Level edge detection interrupt.
748 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
749 * @param NewState: new state of the specified FSMC interrupts.
750 * This parameter can be: ENABLE or DISABLE.
751 * @retval None
752 */
FSMC_ITConfig(uint32_t FSMC_Bank,uint32_t FSMC_IT,FunctionalState NewState)753 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
754 {
755 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
756 assert_param(IS_FSMC_IT(FSMC_IT));
757 assert_param(IS_FUNCTIONAL_STATE(NewState));
758
759 if (NewState != DISABLE)
760 {
761 /* Enable the selected FSMC_Bank2 interrupts */
762 if(FSMC_Bank == FSMC_Bank2_NAND)
763 {
764 FSMC_Bank2->SR2 |= FSMC_IT;
765 }
766 /* Enable the selected FSMC_Bank3 interrupts */
767 else if (FSMC_Bank == FSMC_Bank3_NAND)
768 {
769 FSMC_Bank3->SR3 |= FSMC_IT;
770 }
771 /* Enable the selected FSMC_Bank4 interrupts */
772 else
773 {
774 FSMC_Bank4->SR4 |= FSMC_IT;
775 }
776 }
777 else
778 {
779 /* Disable the selected FSMC_Bank2 interrupts */
780 if(FSMC_Bank == FSMC_Bank2_NAND)
781 {
782
783 FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
784 }
785 /* Disable the selected FSMC_Bank3 interrupts */
786 else if (FSMC_Bank == FSMC_Bank3_NAND)
787 {
788 FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
789 }
790 /* Disable the selected FSMC_Bank4 interrupts */
791 else
792 {
793 FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
794 }
795 }
796 }
797
798 /**
799 * @brief Checks whether the specified FSMC flag is set or not.
800 * @param FSMC_Bank: specifies the FSMC Bank to be used
801 * This parameter can be one of the following values:
802 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
803 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
804 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
805 * @param FSMC_FLAG: specifies the flag to check.
806 * This parameter can be one of the following values:
807 * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
808 * @arg FSMC_FLAG_Level: Level detection Flag.
809 * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
810 * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
811 * @retval The new state of FSMC_FLAG (SET or RESET).
812 */
FSMC_GetFlagStatus(uint32_t FSMC_Bank,uint32_t FSMC_FLAG)813 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
814 {
815 FlagStatus bitstatus = RESET;
816 uint32_t tmpsr = 0x00000000;
817
818 /* Check the parameters */
819 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
820 assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
821
822 if(FSMC_Bank == FSMC_Bank2_NAND)
823 {
824 tmpsr = FSMC_Bank2->SR2;
825 }
826 else if(FSMC_Bank == FSMC_Bank3_NAND)
827 {
828 tmpsr = FSMC_Bank3->SR3;
829 }
830 /* FSMC_Bank4_PCCARD*/
831 else
832 {
833 tmpsr = FSMC_Bank4->SR4;
834 }
835
836 /* Get the flag status */
837 if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
838 {
839 bitstatus = SET;
840 }
841 else
842 {
843 bitstatus = RESET;
844 }
845 /* Return the flag status */
846 return bitstatus;
847 }
848
849 /**
850 * @brief Clears the FSMC's pending flags.
851 * @param FSMC_Bank: specifies the FSMC Bank to be used
852 * This parameter can be one of the following values:
853 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
854 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
855 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
856 * @param FSMC_FLAG: specifies the flag to clear.
857 * This parameter can be any combination of the following values:
858 * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
859 * @arg FSMC_FLAG_Level: Level detection Flag.
860 * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
861 * @retval None
862 */
FSMC_ClearFlag(uint32_t FSMC_Bank,uint32_t FSMC_FLAG)863 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
864 {
865 /* Check the parameters */
866 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
867 assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
868
869 if(FSMC_Bank == FSMC_Bank2_NAND)
870 {
871 FSMC_Bank2->SR2 &= ~FSMC_FLAG;
872 }
873 else if(FSMC_Bank == FSMC_Bank3_NAND)
874 {
875 FSMC_Bank3->SR3 &= ~FSMC_FLAG;
876 }
877 /* FSMC_Bank4_PCCARD*/
878 else
879 {
880 FSMC_Bank4->SR4 &= ~FSMC_FLAG;
881 }
882 }
883
884 /**
885 * @brief Checks whether the specified FSMC interrupt has occurred or not.
886 * @param FSMC_Bank: specifies the FSMC Bank to be used
887 * This parameter can be one of the following values:
888 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
889 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
890 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
891 * @param FSMC_IT: specifies the FSMC interrupt source to check.
892 * This parameter can be one of the following values:
893 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
894 * @arg FSMC_IT_Level: Level edge detection interrupt.
895 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
896 * @retval The new state of FSMC_IT (SET or RESET).
897 */
FSMC_GetITStatus(uint32_t FSMC_Bank,uint32_t FSMC_IT)898 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
899 {
900 ITStatus bitstatus = RESET;
901 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
902
903 /* Check the parameters */
904 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
905 assert_param(IS_FSMC_GET_IT(FSMC_IT));
906
907 if(FSMC_Bank == FSMC_Bank2_NAND)
908 {
909 tmpsr = FSMC_Bank2->SR2;
910 }
911 else if(FSMC_Bank == FSMC_Bank3_NAND)
912 {
913 tmpsr = FSMC_Bank3->SR3;
914 }
915 /* FSMC_Bank4_PCCARD*/
916 else
917 {
918 tmpsr = FSMC_Bank4->SR4;
919 }
920
921 itstatus = tmpsr & FSMC_IT;
922
923 itenable = tmpsr & (FSMC_IT >> 3);
924 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
925 {
926 bitstatus = SET;
927 }
928 else
929 {
930 bitstatus = RESET;
931 }
932 return bitstatus;
933 }
934
935 /**
936 * @brief Clears the FSMC's interrupt pending bits.
937 * @param FSMC_Bank: specifies the FSMC Bank to be used
938 * This parameter can be one of the following values:
939 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
940 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
941 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
942 * @param FSMC_IT: specifies the interrupt pending bit to clear.
943 * This parameter can be any combination of the following values:
944 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
945 * @arg FSMC_IT_Level: Level edge detection interrupt.
946 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
947 * @retval None
948 */
FSMC_ClearITPendingBit(uint32_t FSMC_Bank,uint32_t FSMC_IT)949 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
950 {
951 /* Check the parameters */
952 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
953 assert_param(IS_FSMC_IT(FSMC_IT));
954
955 if(FSMC_Bank == FSMC_Bank2_NAND)
956 {
957 FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
958 }
959 else if(FSMC_Bank == FSMC_Bank3_NAND)
960 {
961 FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
962 }
963 /* FSMC_Bank4_PCCARD*/
964 else
965 {
966 FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
967 }
968 }
969
970 /**
971 * @}
972 */
973
974 /**
975 * @}
976 */
977
978 /**
979 * @}
980 */
981
982 /**
983 * @}
984 */
985
986 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
987