1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file containing functions prototypes of ADC HAL library. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F4xx_ADC_H 22 #define __STM32F4xx_ADC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx_hal_def.h" 30 31 /* Include low level driver */ 32 #include "stm32f4xx_ll_adc.h" 33 34 /** @addtogroup STM32F4xx_HAL_Driver 35 * @{ 36 */ 37 38 /** @addtogroup ADC 39 * @{ 40 */ 41 42 /* Exported types ------------------------------------------------------------*/ 43 /** @defgroup ADC_Exported_Types ADC Exported Types 44 * @{ 45 */ 46 47 /** 48 * @brief Structure definition of ADC and regular group initialization 49 * @note Parameters of this structure are shared within 2 scopes: 50 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. 51 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 52 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 53 * ADC state can be either: 54 * - For all parameters: ADC disabled 55 * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. 56 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. 57 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 58 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 59 */ 60 typedef struct 61 { 62 uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for 63 all the ADCs. 64 This parameter can be a value of @ref ADC_ClockPrescaler */ 65 uint32_t Resolution; /*!< Configures the ADC resolution. 66 This parameter can be a value of @ref ADC_Resolution */ 67 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 68 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 69 This parameter can be a value of @ref ADC_Data_align */ 70 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 71 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 72 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 73 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 74 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 75 Scan direction is upward: from rank1 to rank 'n'. 76 This parameter can be set to ENABLE or DISABLE */ 77 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 78 This parameter can be a value of @ref ADC_EOCSelection. 79 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. 80 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) 81 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. 82 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). 83 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ 84 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 85 after the selected trigger occurred (software start or external trigger). 86 This parameter can be set to ENABLE or DISABLE. */ 87 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 88 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 89 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ 90 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 91 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 92 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 93 This parameter can be set to ENABLE or DISABLE. */ 94 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 95 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 96 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 97 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 98 If set to ADC_SOFTWARE_START, external triggers are disabled. 99 If set to external trigger source, triggering is on event rising edge by default. 100 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ 101 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 102 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 103 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 104 FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 105 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 106 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 107 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 108 This parameter can be set to ENABLE or DISABLE. */ 109 }ADC_InitTypeDef; 110 111 112 113 /** 114 * @brief Structure definition of ADC channel for regular group 115 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 116 * ADC can be either disabled or enabled without conversion on going on regular group. 117 */ 118 typedef struct 119 { 120 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 121 This parameter can be a value of @ref ADC_channels */ 122 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 123 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 124 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 125 Unit: ADC clock cycles 126 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 127 This parameter can be a value of @ref ADC_sampling_times 128 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 129 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 130 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 131 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 132 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 133 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ 134 }ADC_ChannelConfTypeDef; 135 136 /** 137 * @brief ADC Configuration multi-mode structure definition 138 */ 139 typedef struct 140 { 141 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. 142 This parameter can be a value of @ref ADC_analog_watchdog_selection */ 143 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 144 This parameter must be a 12-bit value. */ 145 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 146 This parameter must be a 12-bit value. */ 147 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. 148 This parameter has an effect only if watchdog mode is configured on single channel 149 This parameter can be a value of @ref ADC_channels */ 150 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured 151 is interrupt mode or in polling mode. 152 This parameter can be set to ENABLE or DISABLE */ 153 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 154 }ADC_AnalogWDGConfTypeDef; 155 156 /** 157 * @brief HAL ADC state machine: ADC states definition (bitfields) 158 */ 159 /* States of ADC global scope */ 160 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ 161 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ 162 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ 163 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ 164 165 /* States of ADC errors */ 166 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ 167 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ 168 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ 169 170 /* States of ADC group regular */ 171 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 172 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 173 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ 174 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */ 175 176 /* States of ADC group injected */ 177 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 178 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 179 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ 180 181 /* States of ADC analog watchdogs */ 182 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ 183 #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */ 184 #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */ 185 186 /* States of ADC multi-mode */ 187 #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */ 188 189 190 /** 191 * @brief ADC handle Structure definition 192 */ 193 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 194 typedef struct __ADC_HandleTypeDef 195 #else 196 typedef struct 197 #endif 198 { 199 ADC_TypeDef *Instance; /*!< Register base address */ 200 201 ADC_InitTypeDef Init; /*!< ADC required parameters */ 202 203 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ 204 205 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 206 207 HAL_LockTypeDef Lock; /*!< ADC locking object */ 208 209 __IO uint32_t State; /*!< ADC communication state */ 210 211 __IO uint32_t ErrorCode; /*!< ADC Error code */ 212 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 213 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 214 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 215 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 216 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 217 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 218 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 219 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 220 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 221 }ADC_HandleTypeDef; 222 223 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 224 /** 225 * @brief HAL ADC Callback ID enumeration definition 226 */ 227 typedef enum 228 { 229 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 230 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 231 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 232 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 233 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 234 HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ 235 HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ 236 } HAL_ADC_CallbackIDTypeDef; 237 238 /** 239 * @brief HAL ADC Callback pointer definition 240 */ 241 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 242 243 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 244 245 /** 246 * @} 247 */ 248 249 /* Exported constants --------------------------------------------------------*/ 250 /** @defgroup ADC_Exported_Constants ADC Exported Constants 251 * @{ 252 */ 253 254 /** @defgroup ADC_Error_Code ADC Error Code 255 * @{ 256 */ 257 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ 258 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, 259 enable/disable, erroneous state */ 260 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ 261 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ 262 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 263 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 264 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 265 /** 266 * @} 267 */ 268 269 270 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler 271 * @{ 272 */ 273 #define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U 274 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) 275 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) 276 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) 277 /** 278 * @} 279 */ 280 281 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases 282 * @{ 283 */ 284 #define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U 285 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) 286 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) 287 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 288 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) 289 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 290 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 291 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 292 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) 293 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) 294 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) 295 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 296 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) 297 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 298 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 299 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) 300 /** 301 * @} 302 */ 303 304 /** @defgroup ADC_Resolution ADC Resolution 305 * @{ 306 */ 307 #define ADC_RESOLUTION_12B 0x00000000U 308 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) 309 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) 310 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) 311 /** 312 * @} 313 */ 314 315 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular 316 * @{ 317 */ 318 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U 319 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) 320 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) 321 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) 322 /** 323 * @} 324 */ 325 326 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular 327 * @{ 328 */ 329 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ 330 /* compatibility with other STM32 devices. */ 331 #define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U 332 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) 333 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) 334 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 335 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) 336 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 337 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 338 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 339 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) 340 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) 341 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) 342 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 343 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) 344 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 345 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 346 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) 347 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U) 348 /** 349 * @} 350 */ 351 352 /** @defgroup ADC_Data_align ADC Data Align 353 * @{ 354 */ 355 #define ADC_DATAALIGN_RIGHT 0x00000000U 356 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 357 /** 358 * @} 359 */ 360 361 /** @defgroup ADC_channels ADC Common Channels 362 * @{ 363 */ 364 #define ADC_CHANNEL_0 0x00000000U 365 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) 366 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) 367 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 368 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) 369 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 370 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 371 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 372 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) 373 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) 374 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) 375 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 376 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) 377 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 378 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 379 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 380 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) 381 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) 382 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) 383 384 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) 385 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) 386 /** 387 * @} 388 */ 389 390 /** @defgroup ADC_sampling_times ADC Sampling Times 391 * @{ 392 */ 393 #define ADC_SAMPLETIME_3CYCLES 0x00000000U 394 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) 395 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) 396 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) 397 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) 398 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) 399 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) 400 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) 401 /** 402 * @} 403 */ 404 405 /** @defgroup ADC_EOCSelection ADC EOC Selection 406 * @{ 407 */ 408 #define ADC_EOC_SEQ_CONV 0x00000000U 409 #define ADC_EOC_SINGLE_CONV 0x00000001U 410 #define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */ 411 /** 412 * @} 413 */ 414 415 /** @defgroup ADC_Event_type ADC Event Type 416 * @{ 417 */ 418 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) 419 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) 420 /** 421 * @} 422 */ 423 424 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection 425 * @{ 426 */ 427 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 428 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 429 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 430 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) 431 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) 432 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 433 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U 434 /** 435 * @} 436 */ 437 438 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition 439 * @{ 440 */ 441 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) 442 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) 443 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) 444 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) 445 /** 446 * @} 447 */ 448 449 /** @defgroup ADC_flags_definition ADC Flags Definition 450 * @{ 451 */ 452 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) 453 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) 454 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) 455 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) 456 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) 457 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) 458 /** 459 * @} 460 */ 461 462 /** @defgroup ADC_channels_type ADC Channels Type 463 * @{ 464 */ 465 #define ADC_ALL_CHANNELS 0x00000001U 466 #define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */ 467 #define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */ 468 /** 469 * @} 470 */ 471 472 /** 473 * @} 474 */ 475 476 /* Exported macro ------------------------------------------------------------*/ 477 /** @defgroup ADC_Exported_Macros ADC Exported Macros 478 * @{ 479 */ 480 481 /** @brief Reset ADC handle state 482 * @param __HANDLE__ ADC handle 483 * @retval None 484 */ 485 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 486 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 487 do{ \ 488 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 489 (__HANDLE__)->MspInitCallback = NULL; \ 490 (__HANDLE__)->MspDeInitCallback = NULL; \ 491 } while(0) 492 #else 493 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 494 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 495 #endif 496 497 /** 498 * @brief Enable the ADC peripheral. 499 * @param __HANDLE__ ADC handle 500 * @retval None 501 */ 502 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) 503 504 /** 505 * @brief Disable the ADC peripheral. 506 * @param __HANDLE__ ADC handle 507 * @retval None 508 */ 509 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) 510 511 /** 512 * @brief Enable the ADC end of conversion interrupt. 513 * @param __HANDLE__ specifies the ADC Handle. 514 * @param __INTERRUPT__ ADC Interrupt. 515 * @retval None 516 */ 517 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) 518 519 /** 520 * @brief Disable the ADC end of conversion interrupt. 521 * @param __HANDLE__ specifies the ADC Handle. 522 * @param __INTERRUPT__ ADC interrupt. 523 * @retval None 524 */ 525 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) 526 527 /** @brief Check if the specified ADC interrupt source is enabled or disabled. 528 * @param __HANDLE__ specifies the ADC Handle. 529 * @param __INTERRUPT__ specifies the ADC interrupt source to check. 530 * @retval The new state of __IT__ (TRUE or FALSE). 531 */ 532 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 533 534 /** 535 * @brief Clear the ADC's pending flags. 536 * @param __HANDLE__ specifies the ADC Handle. 537 * @param __FLAG__ ADC flag. 538 * @retval None 539 */ 540 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) 541 542 /** 543 * @brief Get the selected ADC's flag status. 544 * @param __HANDLE__ specifies the ADC Handle. 545 * @param __FLAG__ ADC flag. 546 * @retval None 547 */ 548 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 549 550 /** 551 * @} 552 */ 553 554 /* Include ADC HAL Extension module */ 555 #include "stm32f4xx_hal_adc_ex.h" 556 557 /* Exported functions --------------------------------------------------------*/ 558 /** @addtogroup ADC_Exported_Functions 559 * @{ 560 */ 561 562 /** @addtogroup ADC_Exported_Functions_Group1 563 * @{ 564 */ 565 /* Initialization/de-initialization functions ***********************************/ 566 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 567 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 568 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 569 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 570 571 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 572 /* Callbacks Register/UnRegister functions ***********************************/ 573 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 574 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 575 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 576 /** 577 * @} 578 */ 579 580 /** @addtogroup ADC_Exported_Functions_Group2 581 * @{ 582 */ 583 /* I/O operation functions ******************************************************/ 584 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 585 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 586 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 587 588 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 589 590 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 591 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 592 593 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 594 595 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 596 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 597 598 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 599 600 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 601 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 602 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 603 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 604 /** 605 * @} 606 */ 607 608 /** @addtogroup ADC_Exported_Functions_Group3 609 * @{ 610 */ 611 /* Peripheral Control functions *************************************************/ 612 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 613 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 614 /** 615 * @} 616 */ 617 618 /** @addtogroup ADC_Exported_Functions_Group4 619 * @{ 620 */ 621 /* Peripheral State functions ***************************************************/ 622 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 623 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 624 /** 625 * @} 626 */ 627 628 /** 629 * @} 630 */ 631 /* Private types -------------------------------------------------------------*/ 632 /* Private variables ---------------------------------------------------------*/ 633 /* Private constants ---------------------------------------------------------*/ 634 /** @defgroup ADC_Private_Constants ADC Private Constants 635 * @{ 636 */ 637 /* Delay for ADC stabilization time. */ 638 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ 639 /* Unit: us */ 640 #define ADC_STAB_DELAY_US 3U 641 /* Delay for temperature sensor stabilization time. */ 642 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ 643 /* Unit: us */ 644 #define ADC_TEMPSENSOR_DELAY_US 10U 645 /** 646 * @} 647 */ 648 649 /* Private macro ------------------------------------------------------------*/ 650 651 /** @defgroup ADC_Private_Macros ADC Private Macros 652 * @{ 653 */ 654 /* Macro reserved for internal HAL driver usage, not intended to be used in 655 code of final user */ 656 657 /** 658 * @brief Verification of ADC state: enabled or disabled 659 * @param __HANDLE__ ADC handle 660 * @retval SET (ADC enabled) or RESET (ADC disabled) 661 */ 662 #define ADC_IS_ENABLE(__HANDLE__) \ 663 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ 664 ) ? SET : RESET) 665 666 /** 667 * @brief Test if conversion trigger of regular group is software start 668 * or external trigger. 669 * @param __HANDLE__ ADC handle 670 * @retval SET (software start) or RESET (external trigger) 671 */ 672 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 673 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 674 675 /** 676 * @brief Test if conversion trigger of injected group is software start 677 * or external trigger. 678 * @param __HANDLE__ ADC handle 679 * @retval SET (software start) or RESET (external trigger) 680 */ 681 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 682 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) 683 684 /** 685 * @brief Simultaneously clears and sets specific bits of the handle State 686 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 687 * the first parameter is the ADC handle State, the second parameter is the 688 * bit field to clear, the third and last parameter is the bit field to set. 689 * @retval None 690 */ 691 #define ADC_STATE_CLR_SET MODIFY_REG 692 693 /** 694 * @brief Clear ADC error code (set it to error code: "no error") 695 * @param __HANDLE__ ADC handle 696 * @retval None 697 */ 698 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 699 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 700 701 702 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 703 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 704 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ 705 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8)) 706 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 707 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 708 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 709 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 710 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 711 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 712 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 713 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ 714 ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ 715 ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ 716 ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ 717 ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ 718 ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ 719 ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ 720 ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ 721 ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) 722 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 723 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 724 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 725 ((RESOLUTION) == ADC_RESOLUTION_6B)) 726 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 727 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 728 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 729 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) 730 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 731 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 732 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 733 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 734 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 735 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ 736 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 737 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 738 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 739 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 740 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ 741 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ 742 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ 743 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ 744 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ 745 ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \ 746 ((REGTRIG) == ADC_SOFTWARE_START)) 747 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 748 ((ALIGN) == ADC_DATAALIGN_LEFT)) 749 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ 750 ((TIME) == ADC_SAMPLETIME_15CYCLES) || \ 751 ((TIME) == ADC_SAMPLETIME_28CYCLES) || \ 752 ((TIME) == ADC_SAMPLETIME_56CYCLES) || \ 753 ((TIME) == ADC_SAMPLETIME_84CYCLES) || \ 754 ((TIME) == ADC_SAMPLETIME_112CYCLES) || \ 755 ((TIME) == ADC_SAMPLETIME_144CYCLES) || \ 756 ((TIME) == ADC_SAMPLETIME_480CYCLES)) 757 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ 758 ((EOCSelection) == ADC_EOC_SEQ_CONV) || \ 759 ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) 760 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 761 ((EVENT) == ADC_OVR_EVENT)) 762 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 763 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 764 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 765 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 766 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 767 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ 768 ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) 769 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ 770 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ 771 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) 772 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU) 773 774 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) 775 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U))) 776 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 777 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 778 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \ 779 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \ 780 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \ 781 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU))) 782 783 /** 784 * @brief Set ADC Regular channel sequence length. 785 * @param _NbrOfConversion_ Regular channel sequence length. 786 * @retval None 787 */ 788 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) 789 790 /** 791 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 792 * @param _SAMPLETIME_ Sample time parameter. 793 * @param _CHANNELNB_ Channel number. 794 * @retval None 795 */ 796 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) 797 798 /** 799 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 800 * @param _SAMPLETIME_ Sample time parameter. 801 * @param _CHANNELNB_ Channel number. 802 * @retval None 803 */ 804 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) 805 806 /** 807 * @brief Set the selected regular channel rank for rank between 1 and 6. 808 * @param _CHANNELNB_ Channel number. 809 * @param _RANKNB_ Rank number. 810 * @retval None 811 */ 812 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) 813 814 /** 815 * @brief Set the selected regular channel rank for rank between 7 and 12. 816 * @param _CHANNELNB_ Channel number. 817 * @param _RANKNB_ Rank number. 818 * @retval None 819 */ 820 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) 821 822 /** 823 * @brief Set the selected regular channel rank for rank between 13 and 16. 824 * @param _CHANNELNB_ Channel number. 825 * @param _RANKNB_ Rank number. 826 * @retval None 827 */ 828 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) 829 830 /** 831 * @brief Enable ADC continuous conversion mode. 832 * @param _CONTINUOUS_MODE_ Continuous mode. 833 * @retval None 834 */ 835 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) 836 837 /** 838 * @brief Configures the number of discontinuous conversions for the regular group channels. 839 * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. 840 * @retval None 841 */ 842 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) 843 844 /** 845 * @brief Enable ADC scan mode. 846 * @param _SCANCONV_MODE_ Scan conversion mode. 847 * @retval None 848 */ 849 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) 850 851 /** 852 * @brief Enable the ADC end of conversion selection. 853 * @param _EOCSelection_MODE_ End of conversion selection mode. 854 * @retval None 855 */ 856 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) 857 858 /** 859 * @brief Enable the ADC DMA continuous request. 860 * @param _DMAContReq_MODE_ DMA continuous request mode. 861 * @retval None 862 */ 863 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) 864 865 /** 866 * @brief Return resolution bits in CR1 register. 867 * @param __HANDLE__ ADC handle 868 * @retval None 869 */ 870 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) 871 872 /** 873 * @} 874 */ 875 876 /* Private functions ---------------------------------------------------------*/ 877 /** @defgroup ADC_Private_Functions ADC Private Functions 878 * @{ 879 */ 880 881 /** 882 * @} 883 */ 884 885 /** 886 * @} 887 */ 888 889 /** 890 * @} 891 */ 892 893 #ifdef __cplusplus 894 } 895 #endif 896 897 #endif /*__STM32F4xx_ADC_H */ 898 899 900 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 901