1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_eth.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F4xx_HAL_ETH_H 22 #define __STM32F4xx_HAL_ETH_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #include "stm32f4xx_hal_def.h" 29 30 /** @addtogroup STM32F4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ETH 35 * @{ 36 */ 37 38 /** @addtogroup ETH_Private_Macros 39 * @{ 40 */ 41 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) 42 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ 43 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 44 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ 45 ((SPEED) == ETH_SPEED_100M)) 46 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ 47 ((MODE) == ETH_MODE_HALFDUPLEX)) 48 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 49 ((MODE) == ETH_RXINTERRUPT_MODE)) 50 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ 51 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 52 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ 53 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 54 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ 55 ((CMD) == ETH_WATCHDOG_DISABLE)) 56 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ 57 ((CMD) == ETH_JABBER_DISABLE)) 58 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ 59 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ 60 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ 61 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ 62 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ 63 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ 64 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ 65 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 66 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ 67 ((CMD) == ETH_CARRIERSENCE_DISABLE)) 68 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ 69 ((CMD) == ETH_RECEIVEOWN_DISABLE)) 70 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ 71 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 72 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ 73 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 74 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ 75 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 76 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ 77 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 78 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ 79 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ 80 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ 81 ((LIMIT) == ETH_BACKOFFLIMIT_1)) 82 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ 83 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 84 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ 85 ((CMD) == ETH_RECEIVEAll_DISABLE)) 86 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ 87 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ 88 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 89 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ 90 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ 91 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 92 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ 93 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 94 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ 95 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 96 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ 97 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 98 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 99 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ 100 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ 101 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 102 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 103 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ 104 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 105 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) 106 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ 107 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 108 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ 109 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ 110 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ 111 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 112 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ 113 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 114 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ 115 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 116 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ 117 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 118 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ 119 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 120 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) 121 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ 122 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ 123 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 124 ((ADDRESS) == ETH_MAC_ADDRESS3)) 125 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ 126 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 127 ((ADDRESS) == ETH_MAC_ADDRESS3)) 128 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ 129 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 130 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ 131 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ 132 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ 133 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ 134 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ 135 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 136 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ 137 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 138 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ 139 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 140 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ 141 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 142 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ 143 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 144 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ 145 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ 146 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ 147 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ 148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ 149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ 150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ 151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 152 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ 153 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 154 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ 155 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 156 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ 157 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ 158 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ 159 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 160 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ 161 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 162 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ 163 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 164 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ 165 ((CMD) == ETH_FIXEDBURST_DISABLE)) 166 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ 167 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ 168 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ 169 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ 170 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ 171 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ 172 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ 173 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ 174 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ 175 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ 176 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ 177 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 178 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ 179 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ 180 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ 181 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ 182 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ 183 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ 184 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ 185 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ 186 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ 187 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ 188 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ 189 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 190 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) 191 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ 192 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ 193 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ 194 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ 195 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 196 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ 197 ((FLAG) == ETH_DMATXDESC_IC) || \ 198 ((FLAG) == ETH_DMATXDESC_LS) || \ 199 ((FLAG) == ETH_DMATXDESC_FS) || \ 200 ((FLAG) == ETH_DMATXDESC_DC) || \ 201 ((FLAG) == ETH_DMATXDESC_DP) || \ 202 ((FLAG) == ETH_DMATXDESC_TTSE) || \ 203 ((FLAG) == ETH_DMATXDESC_TER) || \ 204 ((FLAG) == ETH_DMATXDESC_TCH) || \ 205 ((FLAG) == ETH_DMATXDESC_TTSS) || \ 206 ((FLAG) == ETH_DMATXDESC_IHE) || \ 207 ((FLAG) == ETH_DMATXDESC_ES) || \ 208 ((FLAG) == ETH_DMATXDESC_JT) || \ 209 ((FLAG) == ETH_DMATXDESC_FF) || \ 210 ((FLAG) == ETH_DMATXDESC_PCE) || \ 211 ((FLAG) == ETH_DMATXDESC_LCA) || \ 212 ((FLAG) == ETH_DMATXDESC_NC) || \ 213 ((FLAG) == ETH_DMATXDESC_LCO) || \ 214 ((FLAG) == ETH_DMATXDESC_EC) || \ 215 ((FLAG) == ETH_DMATXDESC_VF) || \ 216 ((FLAG) == ETH_DMATXDESC_CC) || \ 217 ((FLAG) == ETH_DMATXDESC_ED) || \ 218 ((FLAG) == ETH_DMATXDESC_UF) || \ 219 ((FLAG) == ETH_DMATXDESC_DB)) 220 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ 221 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 222 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ 223 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ 224 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ 225 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 226 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) 227 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ 228 ((FLAG) == ETH_DMARXDESC_AFM) || \ 229 ((FLAG) == ETH_DMARXDESC_ES) || \ 230 ((FLAG) == ETH_DMARXDESC_DE) || \ 231 ((FLAG) == ETH_DMARXDESC_SAF) || \ 232 ((FLAG) == ETH_DMARXDESC_LE) || \ 233 ((FLAG) == ETH_DMARXDESC_OE) || \ 234 ((FLAG) == ETH_DMARXDESC_VLAN) || \ 235 ((FLAG) == ETH_DMARXDESC_FS) || \ 236 ((FLAG) == ETH_DMARXDESC_LS) || \ 237 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ 238 ((FLAG) == ETH_DMARXDESC_LC) || \ 239 ((FLAG) == ETH_DMARXDESC_FT) || \ 240 ((FLAG) == ETH_DMARXDESC_RWT) || \ 241 ((FLAG) == ETH_DMARXDESC_RE) || \ 242 ((FLAG) == ETH_DMARXDESC_DBE) || \ 243 ((FLAG) == ETH_DMARXDESC_CE) || \ 244 ((FLAG) == ETH_DMARXDESC_MAMPCE)) 245 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ 246 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 247 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 248 ((FLAG) == ETH_PMT_FLAG_MPR)) 249 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) 250 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 251 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ 252 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ 253 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 254 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 255 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 256 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 257 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 258 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 259 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 260 ((FLAG) == ETH_DMA_FLAG_T)) 261 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) 262 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 263 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 264 ((IT) == ETH_MAC_IT_PMT)) 265 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 266 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 267 ((FLAG) == ETH_MAC_FLAG_PMT)) 268 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) 269 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 270 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 271 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 272 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 273 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 274 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 275 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 276 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 277 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 278 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ 279 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 280 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ 281 ((IT) != 0x00U)) 282 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 283 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 284 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 285 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ 286 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 287 288 /** 289 * @} 290 */ 291 292 /** @addtogroup ETH_Private_Defines 293 * @{ 294 */ 295 /* Delay to wait when writing to some Ethernet registers */ 296 #define ETH_REG_WRITE_DELAY 0x00000001U 297 298 /* ETHERNET Errors */ 299 #define ETH_SUCCESS 0U 300 #define ETH_ERROR 1U 301 302 /* ETHERNET DMA Tx descriptors Collision Count Shift */ 303 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U 304 305 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ 306 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U 307 308 /* ETHERNET DMA Rx descriptors Frame Length Shift */ 309 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U 310 311 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ 312 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U 313 314 /* ETHERNET DMA Rx descriptors Frame length Shift */ 315 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U 316 317 /* ETHERNET MAC address offsets */ 318 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ 319 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ 320 321 /* ETHERNET MACMIIAR register Mask */ 322 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U 323 324 /* ETHERNET MACCR register Mask */ 325 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU 326 327 /* ETHERNET MACFCR register Mask */ 328 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U 329 330 /* ETHERNET DMAOMR register Mask */ 331 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U 332 333 /* ETHERNET Remote Wake-up frame register length */ 334 #define ETH_WAKEUP_REGISTER_LENGTH 8U 335 336 /* ETHERNET Missed frames counter Shift */ 337 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U 338 /** 339 * @} 340 */ 341 342 /* Exported types ------------------------------------------------------------*/ 343 /** @defgroup ETH_Exported_Types ETH Exported Types 344 * @{ 345 */ 346 347 /** 348 * @brief HAL State structures definition 349 */ 350 typedef enum 351 { 352 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ 353 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 354 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 355 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ 356 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 357 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ 358 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ 359 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ 360 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 361 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 362 }HAL_ETH_StateTypeDef; 363 364 /** 365 * @brief ETH Init Structure definition 366 */ 367 368 typedef struct 369 { 370 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 371 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 372 and the mode (half/full-duplex). 373 This parameter can be a value of @ref ETH_AutoNegotiation */ 374 375 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 376 This parameter can be a value of @ref ETH_Speed */ 377 378 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 379 This parameter can be a value of @ref ETH_Duplex_Mode */ 380 381 uint16_t PhyAddress; /*!< Ethernet PHY address. 382 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 383 384 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 385 386 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. 387 This parameter can be a value of @ref ETH_Rx_Mode */ 388 389 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. 390 This parameter can be a value of @ref ETH_Checksum_Mode */ 391 392 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. 393 This parameter can be a value of @ref ETH_Media_Interface */ 394 395 } ETH_InitTypeDef; 396 397 398 /** 399 * @brief ETH MAC Configuration Structure definition 400 */ 401 402 typedef struct 403 { 404 uint32_t Watchdog; /*!< Selects or not the Watchdog timer 405 When enabled, the MAC allows no more then 2048 bytes to be received. 406 When disabled, the MAC can receive up to 16384 bytes. 407 This parameter can be a value of @ref ETH_Watchdog */ 408 409 uint32_t Jabber; /*!< Selects or not Jabber timer 410 When enabled, the MAC allows no more then 2048 bytes to be sent. 411 When disabled, the MAC can send up to 16384 bytes. 412 This parameter can be a value of @ref ETH_Jabber */ 413 414 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. 415 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 416 417 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. 418 This parameter can be a value of @ref ETH_Carrier_Sense */ 419 420 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, 421 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 422 in Half-Duplex mode. 423 This parameter can be a value of @ref ETH_Receive_Own */ 424 425 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. 426 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 427 428 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 429 This parameter can be a value of @ref ETH_Checksum_Offload */ 430 431 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 432 when a collision occurs (Half-Duplex mode). 433 This parameter can be a value of @ref ETH_Retry_Transmission */ 434 435 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. 436 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 437 438 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 439 This parameter can be a value of @ref ETH_Back_Off_Limit */ 440 441 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). 442 This parameter can be a value of @ref ETH_Deferral_Check */ 443 444 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). 445 This parameter can be a value of @ref ETH_Receive_All */ 446 447 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. 448 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 449 450 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 451 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 452 453 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. 454 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 455 456 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. 457 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 458 459 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode 460 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 461 462 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. 463 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 464 465 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. 466 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 467 468 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. 469 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 470 471 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. 472 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 473 474 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 475 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ 476 477 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. 478 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 479 480 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 481 automatic retransmission of PAUSE Frame. 482 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 483 484 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 485 unicast address and unique multicast address). 486 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 487 488 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 489 disable its transmitter for a specified time (Pause Time) 490 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 491 492 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 493 or the MAC back-pressure operation (Half-Duplex mode) 494 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 495 496 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 497 comparison and filtering. 498 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 499 500 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 501 502 } ETH_MACInitTypeDef; 503 504 /** 505 * @brief ETH DMA Configuration Structure definition 506 */ 507 508 typedef struct 509 { 510 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. 511 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 512 513 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. 514 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 515 516 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. 517 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 518 519 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. 520 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 521 522 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 523 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 524 525 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. 526 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 527 528 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 529 and length less than 64 bytes) including pad-bytes and CRC) 530 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 531 532 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 533 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 534 535 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 536 frame of Transmit data even before obtaining the status for the first frame. 537 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 538 539 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. 540 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 541 542 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. 543 This parameter can be a value of @ref ETH_Fixed_Burst */ 544 545 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 546 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 547 548 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 549 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 550 551 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. 552 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ 553 554 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 555 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 556 557 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. 558 This parameter can be a value of @ref ETH_DMA_Arbitration */ 559 } ETH_DMAInitTypeDef; 560 561 562 /** 563 * @brief ETH DMA Descriptors data structure definition 564 */ 565 566 typedef struct 567 { 568 __IO uint32_t Status; /*!< Status */ 569 570 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 571 572 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 573 574 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 575 576 /*!< Enhanced ETHERNET DMA PTP Descriptors */ 577 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ 578 579 uint32_t Reserved1; /*!< Reserved */ 580 581 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ 582 583 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ 584 585 } ETH_DMADescTypeDef; 586 587 /** 588 * @brief Received Frame Informations structure definition 589 */ 590 typedef struct 591 { 592 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ 593 594 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ 595 596 uint32_t SegCount; /*!< Segment count */ 597 598 uint32_t length; /*!< Frame length */ 599 600 uint32_t buffer; /*!< Frame buffer */ 601 602 } ETH_DMARxFrameInfos; 603 604 /** 605 * @brief ETH Handle Structure definition 606 */ 607 608 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 609 typedef struct __ETH_HandleTypeDef 610 #else 611 typedef struct 612 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 613 { 614 ETH_TypeDef *Instance; /*!< Register base address */ 615 616 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 617 618 uint32_t LinkStatus; /*!< Ethernet link status */ 619 620 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ 621 622 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ 623 624 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ 625 626 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ 627 628 HAL_LockTypeDef Lock; /*!< ETH Lock */ 629 630 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 631 632 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ 633 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ 634 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */ 635 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ 636 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ 637 638 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 639 640 } ETH_HandleTypeDef; 641 642 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 643 /** 644 * @brief HAL ETH Callback ID enumeration definition 645 */ 646 typedef enum 647 { 648 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 649 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 650 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 651 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 652 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 653 654 }HAL_ETH_CallbackIDTypeDef; 655 656 /** 657 * @brief HAL ETH Callback pointer definition 658 */ 659 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ 660 661 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 662 663 /** 664 * @} 665 */ 666 667 /* Exported constants --------------------------------------------------------*/ 668 /** @defgroup ETH_Exported_Constants ETH Exported Constants 669 * @{ 670 */ 671 672 /** @defgroup ETH_Buffers_setting ETH Buffers setting 673 * @{ 674 */ 675 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ 676 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 677 #define ETH_CRC 4U /*!< Ethernet CRC */ 678 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ 679 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 680 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 681 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 682 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 683 684 /* Ethernet driver receive buffers are organized in a chained linked-list, when 685 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 686 to the driver receive buffers memory. 687 688 Depending on the size of the received ethernet packet and the size of 689 each ethernet driver receive buffer, the received packet can take one or more 690 ethernet driver receive buffer. 691 692 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 693 and the total count of the driver receive buffers ETH_RXBUFNB. 694 695 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 696 example, they can be reconfigured in the application layer to fit the application 697 needs */ 698 699 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 700 packet */ 701 #ifndef ETH_RX_BUF_SIZE 702 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 703 #endif 704 705 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 706 #ifndef ETH_RXBUFNB 707 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 708 #endif 709 710 711 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 712 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 713 driver transmit buffers memory to the TxFIFO. 714 715 Depending on the size of the Ethernet packet to be transmitted and the size of 716 each ethernet driver transmit buffer, the packet to be transmitted can take 717 one or more ethernet driver transmit buffer. 718 719 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 720 and the total count of the driver transmit buffers ETH_TXBUFNB. 721 722 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 723 example, they can be reconfigured in the application layer to fit the application 724 needs */ 725 726 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 727 packet */ 728 #ifndef ETH_TX_BUF_SIZE 729 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 730 #endif 731 732 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 733 #ifndef ETH_TXBUFNB 734 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 735 #endif 736 737 /** 738 * @} 739 */ 740 741 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor 742 * @{ 743 */ 744 745 /* 746 DMA Tx Descriptor 747 ----------------------------------------------------------------------------------------------- 748 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 749 ----------------------------------------------------------------------------------------------- 750 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 751 ----------------------------------------------------------------------------------------------- 752 TDES2 | Buffer1 Address [31:0] | 753 ----------------------------------------------------------------------------------------------- 754 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 755 ----------------------------------------------------------------------------------------------- 756 */ 757 758 /** 759 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 760 */ 761 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 762 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ 763 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ 764 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ 765 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ 766 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ 767 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ 768 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ 769 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ 770 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ 771 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 772 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 773 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ 774 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ 775 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ 776 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ 777 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 778 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ 779 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 780 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ 781 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 782 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 783 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 784 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 785 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ 786 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ 787 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ 788 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ 789 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ 790 791 /** 792 * @brief Bit definition of TDES1 register 793 */ 794 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ 795 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ 796 797 /** 798 * @brief Bit definition of TDES2 register 799 */ 800 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 801 802 /** 803 * @brief Bit definition of TDES3 register 804 */ 805 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 806 807 /*--------------------------------------------------------------------------------------------- 808 TDES6 | Transmit Time Stamp Low [31:0] | 809 ----------------------------------------------------------------------------------------------- 810 TDES7 | Transmit Time Stamp High [31:0] | 811 ----------------------------------------------------------------------------------------------*/ 812 813 /* Bit definition of TDES6 register */ 814 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ 815 816 /* Bit definition of TDES7 register */ 817 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ 818 819 /** 820 * @} 821 */ 822 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 823 * @{ 824 */ 825 826 /* 827 DMA Rx Descriptor 828 -------------------------------------------------------------------------------------------------------------------- 829 RDES0 | OWN(31) | Status [30:0] | 830 --------------------------------------------------------------------------------------------------------------------- 831 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 832 --------------------------------------------------------------------------------------------------------------------- 833 RDES2 | Buffer1 Address [31:0] | 834 --------------------------------------------------------------------------------------------------------------------- 835 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 836 --------------------------------------------------------------------------------------------------------------------- 837 */ 838 839 /** 840 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 841 */ 842 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 843 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ 844 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ 845 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 846 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ 847 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ 848 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ 849 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ 850 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ 851 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ 852 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ 853 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 854 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ 855 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ 856 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 857 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ 858 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 859 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ 860 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 861 862 /** 863 * @brief Bit definition of RDES1 register 864 */ 865 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ 866 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ 867 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ 868 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ 869 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ 870 871 /** 872 * @brief Bit definition of RDES2 register 873 */ 874 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 875 876 /** 877 * @brief Bit definition of RDES3 register 878 */ 879 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 880 881 /*--------------------------------------------------------------------------------------------------------------------- 882 RDES4 | Reserved[31:15] | Extended Status [14:0] | 883 --------------------------------------------------------------------------------------------------------------------- 884 RDES5 | Reserved[31:0] | 885 --------------------------------------------------------------------------------------------------------------------- 886 RDES6 | Receive Time Stamp Low [31:0] | 887 --------------------------------------------------------------------------------------------------------------------- 888 RDES7 | Receive Time Stamp High [31:0] | 889 --------------------------------------------------------------------------------------------------------------------*/ 890 891 /* Bit definition of RDES4 register */ 892 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ 893 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ 894 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ 895 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ 896 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ 897 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ 898 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ 899 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 900 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ 901 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ 902 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ 903 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ 904 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ 905 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ 906 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ 907 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ 908 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ 909 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ 910 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ 911 912 /* Bit definition of RDES6 register */ 913 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ 914 915 /* Bit definition of RDES7 register */ 916 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ 917 /** 918 * @} 919 */ 920 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 921 * @{ 922 */ 923 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U 924 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U 925 926 /** 927 * @} 928 */ 929 /** @defgroup ETH_Speed ETH Speed 930 * @{ 931 */ 932 #define ETH_SPEED_10M 0x00000000U 933 #define ETH_SPEED_100M 0x00004000U 934 935 /** 936 * @} 937 */ 938 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 939 * @{ 940 */ 941 #define ETH_MODE_FULLDUPLEX 0x00000800U 942 #define ETH_MODE_HALFDUPLEX 0x00000000U 943 /** 944 * @} 945 */ 946 /** @defgroup ETH_Rx_Mode ETH Rx Mode 947 * @{ 948 */ 949 #define ETH_RXPOLLING_MODE 0x00000000U 950 #define ETH_RXINTERRUPT_MODE 0x00000001U 951 /** 952 * @} 953 */ 954 955 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 956 * @{ 957 */ 958 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U 959 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U 960 /** 961 * @} 962 */ 963 964 /** @defgroup ETH_Media_Interface ETH Media Interface 965 * @{ 966 */ 967 #define ETH_MEDIA_INTERFACE_MII 0x00000000U 968 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) 969 /** 970 * @} 971 */ 972 973 /** @defgroup ETH_Watchdog ETH Watchdog 974 * @{ 975 */ 976 #define ETH_WATCHDOG_ENABLE 0x00000000U 977 #define ETH_WATCHDOG_DISABLE 0x00800000U 978 /** 979 * @} 980 */ 981 982 /** @defgroup ETH_Jabber ETH Jabber 983 * @{ 984 */ 985 #define ETH_JABBER_ENABLE 0x00000000U 986 #define ETH_JABBER_DISABLE 0x00400000U 987 /** 988 * @} 989 */ 990 991 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 992 * @{ 993 */ 994 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ 995 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ 996 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ 997 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ 998 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ 999 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ 1000 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ 1001 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ 1002 /** 1003 * @} 1004 */ 1005 1006 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 1007 * @{ 1008 */ 1009 #define ETH_CARRIERSENCE_ENABLE 0x00000000U 1010 #define ETH_CARRIERSENCE_DISABLE 0x00010000U 1011 /** 1012 * @} 1013 */ 1014 1015 /** @defgroup ETH_Receive_Own ETH Receive Own 1016 * @{ 1017 */ 1018 #define ETH_RECEIVEOWN_ENABLE 0x00000000U 1019 #define ETH_RECEIVEOWN_DISABLE 0x00002000U 1020 /** 1021 * @} 1022 */ 1023 1024 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 1025 * @{ 1026 */ 1027 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U 1028 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U 1029 /** 1030 * @} 1031 */ 1032 1033 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 1034 * @{ 1035 */ 1036 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U 1037 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U 1038 /** 1039 * @} 1040 */ 1041 1042 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 1043 * @{ 1044 */ 1045 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U 1046 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U 1047 /** 1048 * @} 1049 */ 1050 1051 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 1052 * @{ 1053 */ 1054 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U 1055 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U 1056 /** 1057 * @} 1058 */ 1059 1060 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1061 * @{ 1062 */ 1063 #define ETH_BACKOFFLIMIT_10 0x00000000U 1064 #define ETH_BACKOFFLIMIT_8 0x00000020U 1065 #define ETH_BACKOFFLIMIT_4 0x00000040U 1066 #define ETH_BACKOFFLIMIT_1 0x00000060U 1067 /** 1068 * @} 1069 */ 1070 1071 /** @defgroup ETH_Deferral_Check ETH Deferral Check 1072 * @{ 1073 */ 1074 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U 1075 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U 1076 /** 1077 * @} 1078 */ 1079 1080 /** @defgroup ETH_Receive_All ETH Receive All 1081 * @{ 1082 */ 1083 #define ETH_RECEIVEALL_ENABLE 0x80000000U 1084 #define ETH_RECEIVEAll_DISABLE 0x00000000U 1085 /** 1086 * @} 1087 */ 1088 1089 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 1090 * @{ 1091 */ 1092 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U 1093 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U 1094 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U 1095 /** 1096 * @} 1097 */ 1098 1099 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 1100 * @{ 1101 */ 1102 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ 1103 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 1104 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ 1105 /** 1106 * @} 1107 */ 1108 1109 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 1110 * @{ 1111 */ 1112 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U 1113 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U 1114 /** 1115 * @} 1116 */ 1117 1118 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 1119 * @{ 1120 */ 1121 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U 1122 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U 1123 /** 1124 * @} 1125 */ 1126 1127 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 1128 * @{ 1129 */ 1130 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U 1131 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U 1132 /** 1133 * @} 1134 */ 1135 1136 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 1137 * @{ 1138 */ 1139 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U 1140 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U 1141 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U 1142 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U 1143 /** 1144 * @} 1145 */ 1146 1147 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 1148 * @{ 1149 */ 1150 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U 1151 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U 1152 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U 1153 /** 1154 * @} 1155 */ 1156 1157 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 1158 * @{ 1159 */ 1160 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U 1161 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U 1162 /** 1163 * @} 1164 */ 1165 1166 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1167 * @{ 1168 */ 1169 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ 1170 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ 1171 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ 1172 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ 1173 /** 1174 * @} 1175 */ 1176 1177 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 1178 * @{ 1179 */ 1180 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U 1181 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U 1182 /** 1183 * @} 1184 */ 1185 1186 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 1187 * @{ 1188 */ 1189 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U 1190 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U 1191 /** 1192 * @} 1193 */ 1194 1195 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 1196 * @{ 1197 */ 1198 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U 1199 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U 1200 /** 1201 * @} 1202 */ 1203 1204 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1205 * @{ 1206 */ 1207 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U 1208 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 1209 /** 1210 * @} 1211 */ 1212 1213 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1214 * @{ 1215 */ 1216 #define ETH_MAC_ADDRESS0 0x00000000U 1217 #define ETH_MAC_ADDRESS1 0x00000008U 1218 #define ETH_MAC_ADDRESS2 0x00000010U 1219 #define ETH_MAC_ADDRESS3 0x00000018U 1220 /** 1221 * @} 1222 */ 1223 1224 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 1225 * @{ 1226 */ 1227 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U 1228 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U 1229 /** 1230 * @} 1231 */ 1232 1233 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 1234 * @{ 1235 */ 1236 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ 1237 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ 1238 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ 1239 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ 1240 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ 1241 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ 1242 /** 1243 * @} 1244 */ 1245 1246 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame 1247 * @{ 1248 */ 1249 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U 1250 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U 1251 /** 1252 * @} 1253 */ 1254 1255 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 1256 * @{ 1257 */ 1258 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U 1259 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U 1260 /** 1261 * @} 1262 */ 1263 1264 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame 1265 * @{ 1266 */ 1267 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U 1268 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U 1269 /** 1270 * @} 1271 */ 1272 1273 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward 1274 * @{ 1275 */ 1276 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U 1277 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U 1278 /** 1279 * @} 1280 */ 1281 1282 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 1283 * @{ 1284 */ 1285 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 1286 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 1287 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 1288 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 1289 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 1290 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 1291 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 1292 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 1293 /** 1294 * @} 1295 */ 1296 1297 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames 1298 * @{ 1299 */ 1300 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U 1301 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U 1302 /** 1303 * @} 1304 */ 1305 1306 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames 1307 * @{ 1308 */ 1309 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U 1310 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U 1311 /** 1312 * @} 1313 */ 1314 1315 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 1316 * @{ 1317 */ 1318 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 1319 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 1320 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 1321 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 1322 /** 1323 * @} 1324 */ 1325 1326 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate 1327 * @{ 1328 */ 1329 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U 1330 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U 1331 /** 1332 * @} 1333 */ 1334 1335 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 1336 * @{ 1337 */ 1338 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U 1339 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U 1340 /** 1341 * @} 1342 */ 1343 1344 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst 1345 * @{ 1346 */ 1347 #define ETH_FIXEDBURST_ENABLE 0x00010000U 1348 #define ETH_FIXEDBURST_DISABLE 0x00000000U 1349 /** 1350 * @} 1351 */ 1352 1353 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1354 * @{ 1355 */ 1356 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 1357 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 1358 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1359 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1360 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1361 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1362 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1363 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1364 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1365 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1366 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 1367 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 1368 /** 1369 * @} 1370 */ 1371 1372 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1373 * @{ 1374 */ 1375 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 1376 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 1377 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1378 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1379 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1380 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1381 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1382 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1383 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1384 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1385 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 1386 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 1387 /** 1388 * @} 1389 */ 1390 1391 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format 1392 * @{ 1393 */ 1394 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U 1395 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U 1396 /** 1397 * @} 1398 */ 1399 1400 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1401 * @{ 1402 */ 1403 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U 1404 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U 1405 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U 1406 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U 1407 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U 1408 /** 1409 * @} 1410 */ 1411 1412 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 1413 * @{ 1414 */ 1415 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ 1416 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ 1417 /** 1418 * @} 1419 */ 1420 1421 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 1422 * @{ 1423 */ 1424 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ 1425 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ 1426 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 1427 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 1428 /** 1429 * @} 1430 */ 1431 1432 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 1433 * @{ 1434 */ 1435 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ 1436 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ 1437 /** 1438 * @} 1439 */ 1440 1441 /** @defgroup ETH_PMT_Flags ETH PMT Flags 1442 * @{ 1443 */ 1444 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ 1445 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ 1446 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ 1447 /** 1448 * @} 1449 */ 1450 1451 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 1452 * @{ 1453 */ 1454 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ 1455 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ 1456 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ 1457 /** 1458 * @} 1459 */ 1460 1461 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 1462 * @{ 1463 */ 1464 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ 1465 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ 1466 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ 1467 /** 1468 * @} 1469 */ 1470 1471 /** @defgroup ETH_MAC_Flags ETH MAC Flags 1472 * @{ 1473 */ 1474 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ 1475 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ 1476 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ 1477 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ 1478 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ 1479 /** 1480 * @} 1481 */ 1482 1483 /** @defgroup ETH_DMA_Flags ETH DMA Flags 1484 * @{ 1485 */ 1486 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1487 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1488 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1489 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 1490 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ 1491 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ 1492 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ 1493 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ 1494 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ 1495 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ 1496 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ 1497 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ 1498 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ 1499 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ 1500 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ 1501 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ 1502 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ 1503 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ 1504 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ 1505 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ 1506 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ 1507 /** 1508 * @} 1509 */ 1510 1511 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1512 * @{ 1513 */ 1514 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ 1515 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ 1516 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ 1517 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ 1518 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ 1519 /** 1520 * @} 1521 */ 1522 1523 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1524 * @{ 1525 */ 1526 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1527 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1528 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1529 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ 1530 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ 1531 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ 1532 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ 1533 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ 1534 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ 1535 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ 1536 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ 1537 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ 1538 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ 1539 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ 1540 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ 1541 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ 1542 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ 1543 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ 1544 /** 1545 * @} 1546 */ 1547 1548 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 1549 * @{ 1550 */ 1551 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ 1552 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ 1553 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ 1554 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ 1555 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ 1556 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ 1557 1558 /** 1559 * @} 1560 */ 1561 1562 1563 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 1564 * @{ 1565 */ 1566 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ 1567 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ 1568 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ 1569 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ 1570 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ 1571 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ 1572 1573 /** 1574 * @} 1575 */ 1576 1577 /** @defgroup ETH_DMA_overflow ETH DMA overflow 1578 * @{ 1579 */ 1580 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ 1581 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ 1582 /** 1583 * @} 1584 */ 1585 1586 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP 1587 * @{ 1588 */ 1589 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ 1590 1591 /** 1592 * @} 1593 */ 1594 1595 /** 1596 * @} 1597 */ 1598 1599 /* Exported macro ------------------------------------------------------------*/ 1600 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1601 * @brief macros to handle interrupts and specific clock configurations 1602 * @{ 1603 */ 1604 1605 /** @brief Reset ETH handle state 1606 * @param __HANDLE__ specifies the ETH handle. 1607 * @retval None 1608 */ 1609 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1610 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1611 (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ 1612 (__HANDLE__)->MspInitCallback = NULL; \ 1613 (__HANDLE__)->MspDeInitCallback = NULL; \ 1614 } while(0) 1615 #else 1616 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 1617 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1618 1619 /** 1620 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. 1621 * @param __HANDLE__ ETH Handle 1622 * @param __FLAG__ specifies the flag of TDES0 to check. 1623 * @retval the ETH_DMATxDescFlag (SET or RESET). 1624 */ 1625 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 1626 1627 /** 1628 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. 1629 * @param __HANDLE__ ETH Handle 1630 * @param __FLAG__ specifies the flag of RDES0 to check. 1631 * @retval the ETH_DMATxDescFlag (SET or RESET). 1632 */ 1633 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 1634 1635 /** 1636 * @brief Enables the specified DMA Rx Desc receive interrupt. 1637 * @param __HANDLE__ ETH Handle 1638 * @retval None 1639 */ 1640 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 1641 1642 /** 1643 * @brief Disables the specified DMA Rx Desc receive interrupt. 1644 * @param __HANDLE__ ETH Handle 1645 * @retval None 1646 */ 1647 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 1648 1649 /** 1650 * @brief Set the specified DMA Rx Desc Own bit. 1651 * @param __HANDLE__ ETH Handle 1652 * @retval None 1653 */ 1654 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 1655 1656 /** 1657 * @brief Returns the specified ETHERNET DMA Tx Desc collision count. 1658 * @param __HANDLE__ ETH Handle 1659 * @retval The Transmit descriptor collision counter value. 1660 */ 1661 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 1662 1663 /** 1664 * @brief Set the specified DMA Tx Desc Own bit. 1665 * @param __HANDLE__ ETH Handle 1666 * @retval None 1667 */ 1668 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 1669 1670 /** 1671 * @brief Enables the specified DMA Tx Desc Transmit interrupt. 1672 * @param __HANDLE__ ETH Handle 1673 * @retval None 1674 */ 1675 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 1676 1677 /** 1678 * @brief Disables the specified DMA Tx Desc Transmit interrupt. 1679 * @param __HANDLE__ ETH Handle 1680 * @retval None 1681 */ 1682 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 1683 1684 /** 1685 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. 1686 * @param __HANDLE__ ETH Handle 1687 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. 1688 * This parameter can be one of the following values: 1689 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass 1690 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum 1691 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present 1692 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header 1693 * @retval None 1694 */ 1695 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 1696 1697 /** 1698 * @brief Enables the DMA Tx Desc CRC. 1699 * @param __HANDLE__ ETH Handle 1700 * @retval None 1701 */ 1702 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 1703 1704 /** 1705 * @brief Disables the DMA Tx Desc CRC. 1706 * @param __HANDLE__ ETH Handle 1707 * @retval None 1708 */ 1709 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 1710 1711 /** 1712 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. 1713 * @param __HANDLE__ ETH Handle 1714 * @retval None 1715 */ 1716 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 1717 1718 /** 1719 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. 1720 * @param __HANDLE__ ETH Handle 1721 * @retval None 1722 */ 1723 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 1724 1725 /** 1726 * @brief Enables the specified ETHERNET MAC interrupts. 1727 * @param __HANDLE__ ETH Handle 1728 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 1729 * enabled or disabled. 1730 * This parameter can be any combination of the following values: 1731 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1732 * @arg ETH_MAC_IT_PMT : PMT interrupt 1733 * @retval None 1734 */ 1735 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 1736 1737 /** 1738 * @brief Disables the specified ETHERNET MAC interrupts. 1739 * @param __HANDLE__ ETH Handle 1740 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 1741 * enabled or disabled. 1742 * This parameter can be any combination of the following values: 1743 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1744 * @arg ETH_MAC_IT_PMT : PMT interrupt 1745 * @retval None 1746 */ 1747 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 1748 1749 /** 1750 * @brief Initiate a Pause Control Frame (Full-duplex only). 1751 * @param __HANDLE__ ETH Handle 1752 * @retval None 1753 */ 1754 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1755 1756 /** 1757 * @brief Checks whether the ETHERNET flow control busy bit is set or not. 1758 * @param __HANDLE__ ETH Handle 1759 * @retval The new state of flow control busy status bit (SET or RESET). 1760 */ 1761 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 1762 1763 /** 1764 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). 1765 * @param __HANDLE__ ETH Handle 1766 * @retval None 1767 */ 1768 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1769 1770 /** 1771 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). 1772 * @param __HANDLE__ ETH Handle 1773 * @retval None 1774 */ 1775 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 1776 1777 /** 1778 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1779 * @param __HANDLE__ ETH Handle 1780 * @param __FLAG__ specifies the flag to check. 1781 * This parameter can be one of the following values: 1782 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag 1783 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag 1784 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag 1785 * @arg ETH_MAC_FLAG_MMC : MMC flag 1786 * @arg ETH_MAC_FLAG_PMT : PMT flag 1787 * @retval The state of ETHERNET MAC flag. 1788 */ 1789 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 1790 1791 /** 1792 * @brief Enables the specified ETHERNET DMA interrupts. 1793 * @param __HANDLE__ ETH Handle 1794 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 1795 * enabled @ref ETH_DMA_Interrupts 1796 * @retval None 1797 */ 1798 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 1799 1800 /** 1801 * @brief Disables the specified ETHERNET DMA interrupts. 1802 * @param __HANDLE__ ETH Handle 1803 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 1804 * disabled. @ref ETH_DMA_Interrupts 1805 * @retval None 1806 */ 1807 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 1808 1809 /** 1810 * @brief Clears the ETHERNET DMA IT pending bit. 1811 * @param __HANDLE__ ETH Handle 1812 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1813 * @retval None 1814 */ 1815 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 1816 1817 /** 1818 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1819 * @param __HANDLE__ ETH Handle 1820 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags 1821 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1822 */ 1823 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 1824 1825 /** 1826 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1827 * @param __HANDLE__ ETH Handle 1828 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags 1829 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1830 */ 1831 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 1832 1833 /** 1834 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. 1835 * @param __HANDLE__ ETH Handle 1836 * @param __OVERFLOW__ specifies the DMA overflow flag to check. 1837 * This parameter can be one of the following values: 1838 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter 1839 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter 1840 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). 1841 */ 1842 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 1843 1844 /** 1845 * @brief Set the DMA Receive status watchdog timer register value 1846 * @param __HANDLE__ ETH Handle 1847 * @param __VALUE__ DMA Receive status watchdog timer register value 1848 * @retval None 1849 */ 1850 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 1851 1852 /** 1853 * @brief Enables any unicast packet filtered by the MAC address 1854 * recognition to be a wake-up frame. 1855 * @param __HANDLE__ ETH Handle. 1856 * @retval None 1857 */ 1858 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 1859 1860 /** 1861 * @brief Disables any unicast packet filtered by the MAC address 1862 * recognition to be a wake-up frame. 1863 * @param __HANDLE__ ETH Handle. 1864 * @retval None 1865 */ 1866 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 1867 1868 /** 1869 * @brief Enables the MAC Wake-Up Frame Detection. 1870 * @param __HANDLE__ ETH Handle. 1871 * @retval None 1872 */ 1873 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 1874 1875 /** 1876 * @brief Disables the MAC Wake-Up Frame Detection. 1877 * @param __HANDLE__ ETH Handle. 1878 * @retval None 1879 */ 1880 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1881 1882 /** 1883 * @brief Enables the MAC Magic Packet Detection. 1884 * @param __HANDLE__ ETH Handle. 1885 * @retval None 1886 */ 1887 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 1888 1889 /** 1890 * @brief Disables the MAC Magic Packet Detection. 1891 * @param __HANDLE__ ETH Handle. 1892 * @retval None 1893 */ 1894 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1895 1896 /** 1897 * @brief Enables the MAC Power Down. 1898 * @param __HANDLE__ ETH Handle 1899 * @retval None 1900 */ 1901 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 1902 1903 /** 1904 * @brief Disables the MAC Power Down. 1905 * @param __HANDLE__ ETH Handle 1906 * @retval None 1907 */ 1908 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 1909 1910 /** 1911 * @brief Checks whether the specified ETHERNET PMT flag is set or not. 1912 * @param __HANDLE__ ETH Handle. 1913 * @param __FLAG__ specifies the flag to check. 1914 * This parameter can be one of the following values: 1915 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 1916 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received 1917 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received 1918 * @retval The new state of ETHERNET PMT Flag (SET or RESET). 1919 */ 1920 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 1921 1922 /** 1923 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) 1924 * @param __HANDLE__ ETH Handle. 1925 * @retval None 1926 */ 1927 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 1928 1929 /** 1930 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) 1931 * @param __HANDLE__ ETH Handle. 1932 * @retval None 1933 */ 1934 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ 1935 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) 1936 1937 /** 1938 * @brief Enables the MMC Counter Freeze. 1939 * @param __HANDLE__ ETH Handle. 1940 * @retval None 1941 */ 1942 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 1943 1944 /** 1945 * @brief Disables the MMC Counter Freeze. 1946 * @param __HANDLE__ ETH Handle. 1947 * @retval None 1948 */ 1949 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 1950 1951 /** 1952 * @brief Enables the MMC Reset On Read. 1953 * @param __HANDLE__ ETH Handle. 1954 * @retval None 1955 */ 1956 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 1957 1958 /** 1959 * @brief Disables the MMC Reset On Read. 1960 * @param __HANDLE__ ETH Handle. 1961 * @retval None 1962 */ 1963 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 1964 1965 /** 1966 * @brief Enables the MMC Counter Stop Rollover. 1967 * @param __HANDLE__ ETH Handle. 1968 * @retval None 1969 */ 1970 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 1971 1972 /** 1973 * @brief Disables the MMC Counter Stop Rollover. 1974 * @param __HANDLE__ ETH Handle. 1975 * @retval None 1976 */ 1977 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 1978 1979 /** 1980 * @brief Resets the MMC Counters. 1981 * @param __HANDLE__ ETH Handle. 1982 * @retval None 1983 */ 1984 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 1985 1986 /** 1987 * @brief Enables the specified ETHERNET MMC Rx interrupts. 1988 * @param __HANDLE__ ETH Handle. 1989 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 1990 * This parameter can be one of the following values: 1991 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 1992 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 1993 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 1994 * @retval None 1995 */ 1996 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) 1997 /** 1998 * @brief Disables the specified ETHERNET MMC Rx interrupts. 1999 * @param __HANDLE__ ETH Handle. 2000 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2001 * This parameter can be one of the following values: 2002 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 2003 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 2004 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 2005 * @retval None 2006 */ 2007 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) 2008 /** 2009 * @brief Enables the specified ETHERNET MMC Tx interrupts. 2010 * @param __HANDLE__ ETH Handle. 2011 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2012 * This parameter can be one of the following values: 2013 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2014 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2015 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2016 * @retval None 2017 */ 2018 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 2019 2020 /** 2021 * @brief Disables the specified ETHERNET MMC Tx interrupts. 2022 * @param __HANDLE__ ETH Handle. 2023 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2024 * This parameter can be one of the following values: 2025 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2026 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2027 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2028 * @retval None 2029 */ 2030 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 2031 2032 /** 2033 * @brief Enables the ETH External interrupt line. 2034 * @retval None 2035 */ 2036 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 2037 2038 /** 2039 * @brief Disables the ETH External interrupt line. 2040 * @retval None 2041 */ 2042 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 2043 2044 /** 2045 * @brief Enable event on ETH External event line. 2046 * @retval None. 2047 */ 2048 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 2049 2050 /** 2051 * @brief Disable event on ETH External event line 2052 * @retval None. 2053 */ 2054 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 2055 2056 /** 2057 * @brief Get flag of the ETH External interrupt line. 2058 * @retval None 2059 */ 2060 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 2061 2062 /** 2063 * @brief Clear flag of the ETH External interrupt line. 2064 * @retval None 2065 */ 2066 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 2067 2068 /** 2069 * @brief Enables rising edge trigger to the ETH External interrupt line. 2070 * @retval None 2071 */ 2072 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 2073 2074 /** 2075 * @brief Disables the rising edge trigger to the ETH External interrupt line. 2076 * @retval None 2077 */ 2078 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2079 2080 /** 2081 * @brief Enables falling edge trigger to the ETH External interrupt line. 2082 * @retval None 2083 */ 2084 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 2085 2086 /** 2087 * @brief Disables falling edge trigger to the ETH External interrupt line. 2088 * @retval None 2089 */ 2090 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2091 2092 /** 2093 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. 2094 * @retval None 2095 */ 2096 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ 2097 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ 2098 }while(0U) 2099 2100 /** 2101 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. 2102 * @retval None 2103 */ 2104 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2105 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2106 }while(0U) 2107 2108 /** 2109 * @brief Generate a Software interrupt on selected EXTI line. 2110 * @retval None. 2111 */ 2112 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 2113 2114 /** 2115 * @} 2116 */ 2117 /* Exported functions --------------------------------------------------------*/ 2118 2119 /** @addtogroup ETH_Exported_Functions 2120 * @{ 2121 */ 2122 2123 /* Initialization and de-initialization functions ****************************/ 2124 2125 /** @addtogroup ETH_Exported_Functions_Group1 2126 * @{ 2127 */ 2128 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 2129 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 2130 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 2131 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 2132 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); 2133 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 2134 /* Callbacks Register/UnRegister functions ***********************************/ 2135 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 2136 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); 2137 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 2138 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 2139 2140 /** 2141 * @} 2142 */ 2143 /* IO operation functions ****************************************************/ 2144 2145 /** @addtogroup ETH_Exported_Functions_Group2 2146 * @{ 2147 */ 2148 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); 2149 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); 2150 /* Communication with PHY functions*/ 2151 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); 2152 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); 2153 /* Non-Blocking mode: Interrupt */ 2154 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); 2155 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 2156 /* Callback in non blocking modes (Interrupt) */ 2157 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 2158 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 2159 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 2160 /** 2161 * @} 2162 */ 2163 2164 /* Peripheral Control functions **********************************************/ 2165 2166 /** @addtogroup ETH_Exported_Functions_Group3 2167 * @{ 2168 */ 2169 2170 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 2171 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 2172 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); 2173 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); 2174 /** 2175 * @} 2176 */ 2177 2178 /* Peripheral State functions ************************************************/ 2179 2180 /** @addtogroup ETH_Exported_Functions_Group4 2181 * @{ 2182 */ 2183 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 2184 2185 2186 #ifdef __cplusplus 2187 } 2188 #endif 2189 2190 #endif /* __STM32F4xx_HAL_ETH_H */ 2191 2192 2193 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2194