1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_LL_ADC_H
22 #define __STM32F4xx_LL_ADC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx.h"
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @defgroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
46 * @{
47 */
48
49 /* Internal mask for ADC group regular sequencer: */
50 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
51 /* - sequencer register offset */
52 /* - sequencer rank bits position into the selected register */
53
54 /* Internal register offset for ADC group regular sequencer configuration */
55 /* (offset placed into a spare area of literal definition) */
56 #define ADC_SQR1_REGOFFSET 0x00000000UL
57 #define ADC_SQR2_REGOFFSET 0x00000100UL
58 #define ADC_SQR3_REGOFFSET 0x00000200UL
59 #define ADC_SQR4_REGOFFSET 0x00000300UL
60
61 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
63
64 /* Definition of ADC group regular sequencer bits information to be inserted */
65 /* into ADC group regular sequencer ranks literals definition. */
66 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
67 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
68 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
69 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
70 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
71 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
72 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
73 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
74 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
75 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
76 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
77 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
78 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
79 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
80 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
81 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
82
83 /* Internal mask for ADC group injected sequencer: */
84 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
85 /* - data register offset */
86 /* - offset register offset */
87 /* - sequencer rank bits position into the selected register */
88
89 /* Internal register offset for ADC group injected data register */
90 /* (offset placed into a spare area of literal definition) */
91 #define ADC_JDR1_REGOFFSET 0x00000000UL
92 #define ADC_JDR2_REGOFFSET 0x00000100UL
93 #define ADC_JDR3_REGOFFSET 0x00000200UL
94 #define ADC_JDR4_REGOFFSET 0x00000300UL
95
96 /* Internal register offset for ADC group injected offset configuration */
97 /* (offset placed into a spare area of literal definition) */
98 #define ADC_JOFR1_REGOFFSET 0x00000000UL
99 #define ADC_JOFR2_REGOFFSET 0x00001000UL
100 #define ADC_JOFR3_REGOFFSET 0x00002000UL
101 #define ADC_JOFR4_REGOFFSET 0x00003000UL
102
103 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
104 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
105 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
106
107 /* Internal mask for ADC group regular trigger: */
108 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
109 /* - regular trigger source */
110 /* - regular trigger edge */
111 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
112
113 /* Mask containing trigger source masks for each of possible */
114 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
115 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
116 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | \
117 ((ADC_CR2_EXTSEL) >> (4UL * 1UL)) | \
118 ((ADC_CR2_EXTSEL) >> (4UL * 2UL)) | \
119 ((ADC_CR2_EXTSEL) >> (4UL * 3UL)))
120
121 /* Mask containing trigger edge masks for each of possible */
122 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
123 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
124 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | \
125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
127 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
128
129 /* Definition of ADC group regular trigger bits information. */
130 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
131 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
132
133
134
135 /* Internal mask for ADC group injected trigger: */
136 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
137 /* - injected trigger source */
138 /* - injected trigger edge */
139 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
140
141 /* Mask containing trigger source masks for each of possible */
142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
144 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | \
145 ((ADC_CR2_JEXTSEL) >> (4UL * 1UL)) | \
146 ((ADC_CR2_JEXTSEL) >> (4UL * 2UL)) | \
147 ((ADC_CR2_JEXTSEL) >> (4UL * 3UL)))
148
149 /* Mask containing trigger edge masks for each of possible */
150 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
151 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
152 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | \
153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
155 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
156
157 /* Definition of ADC group injected trigger bits information. */
158 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
159 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
160
161 /* Internal mask for ADC channel: */
162 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
163 /* - channel identifier defined by number */
164 /* - channel differentiation between external channels (connected to */
165 /* GPIO pins) and internal channels (connected to internal paths) */
166 /* - channel sampling time defined by SMPRx register offset */
167 /* and SMPx bits positions into SMPRx register */
168 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
169 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
170 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
171 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
172 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
173
174 /* Channel differentiation between external and internal channels */
175 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL /* Marker of internal channel */
176 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
177 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
178 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
179
180 /* Internal register offset for ADC channel sampling time configuration */
181 /* (offset placed into a spare area of literal definition) */
182 #define ADC_SMPR1_REGOFFSET 0x00000000UL
183 #define ADC_SMPR2_REGOFFSET 0x02000000UL
184 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
185
186 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL
187 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
188
189 /* Definition of channels ID number information to be inserted into */
190 /* channels literals definition. */
191 #define ADC_CHANNEL_0_NUMBER 0x00000000UL
192 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
193 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
194 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
195 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
196 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
197 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
198 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
199 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
200 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
201 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
202 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
203 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
204 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
205 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
206 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
207 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
208 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
209 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
210
211 /* Definition of channels sampling time information to be inserted into */
212 /* channels literals definition. */
213 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
214 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
215 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
216 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
217 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
218 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
219 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
220 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
221 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
222 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
223 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
224 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
225 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
226 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
227 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
228 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
229 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
230 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
231 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
232
233 /* Internal mask for ADC analog watchdog: */
234 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
235 /* (concatenation of multiple bits used in different analog watchdogs, */
236 /* (feature of several watchdogs not available on all STM32 families)). */
237 /* - analog watchdog 1: monitored channel defined by number, */
238 /* selection of ADC group (ADC groups regular and-or injected). */
239
240 /* Internal register offset for ADC analog watchdog channel configuration */
241 #define ADC_AWD_CR1_REGOFFSET 0x00000000UL
242
243 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
244
245 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
246 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
247
248 /* Internal register offset for ADC analog watchdog threshold configuration */
249 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000UL
250 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001UL
251 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
252
253 /* ADC registers bits positions */
254 #define ADC_CR1_RES_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
255 #define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
256
257 /* ADC internal channels related definitions */
258 /* Internal voltage reference VrefInt */
259 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
260 #define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
261 /* Temperature sensor */
262 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
263 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
264 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
265 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
266 #define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
267
268 /**
269 * @}
270 */
271
272
273 /* Private macros ------------------------------------------------------------*/
274 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
275 * @{
276 */
277
278 /**
279 * @brief Driver macro reserved for internal use: isolate bits with the
280 * selected mask and shift them to the register LSB
281 * (shift mask on register position bit 0).
282 * @param __BITS__ Bits in register 32 bits
283 * @param __MASK__ Mask in register 32 bits
284 * @retval Bits in register 32 bits
285 */
286 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
287 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
288
289 /**
290 * @brief Driver macro reserved for internal use: set a pointer to
291 * a register from a register basis from which an offset
292 * is applied.
293 * @param __REG__ Register basis from which the offset is applied.
294 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
295 * @retval Pointer to register address
296 */
297 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
298 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
299
300 /**
301 * @}
302 */
303
304
305 /* Exported types ------------------------------------------------------------*/
306 #if defined(USE_FULL_LL_DRIVER)
307 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
308 * @{
309 */
310
311 /**
312 * @brief Structure definition of some features of ADC common parameters
313 * and multimode
314 * (all ADC instances belonging to the same ADC common instance).
315 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
316 * is conditioned to ADC instances state (all ADC instances
317 * sharing the same ADC common instance):
318 * All ADC instances sharing the same ADC common instance must be
319 * disabled.
320 */
321 typedef struct
322 {
323 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
324 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
325
326 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
327
328 #if defined(ADC_MULTIMODE_SUPPORT)
329 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
330 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
331
332 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
333
334 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
335 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
336
337 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
338
339 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
340 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
341
342 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
343 #endif /* ADC_MULTIMODE_SUPPORT */
344
345 } LL_ADC_CommonInitTypeDef;
346
347 /**
348 * @brief Structure definition of some features of ADC instance.
349 * @note These parameters have an impact on ADC scope: ADC instance.
350 * Affects both group regular and group injected (availability
351 * of ADC group injected depends on STM32 families).
352 * Refer to corresponding unitary functions into
353 * @ref ADC_LL_EF_Configuration_ADC_Instance .
354 * @note The setting of these parameters by function @ref LL_ADC_Init()
355 * is conditioned to ADC state:
356 * ADC instance must be disabled.
357 * This condition is applied to all ADC features, for efficiency
358 * and compatibility over all STM32 families. However, the different
359 * features can be set under different ADC state conditions
360 * (setting possible with ADC enabled without conversion on going,
361 * ADC enabled with conversion on going, ...)
362 * Each feature can be updated afterwards with a unitary function
363 * and potentially with ADC in a different state than disabled,
364 * refer to description of each function for setting
365 * conditioned to ADC state.
366 */
367 typedef struct
368 {
369 uint32_t Resolution; /*!< Set ADC resolution.
370 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
371
372 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
373
374 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
375 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
376
377 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
378
379 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
380 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
381
382 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
383
384 } LL_ADC_InitTypeDef;
385
386 /**
387 * @brief Structure definition of some features of ADC group regular.
388 * @note These parameters have an impact on ADC scope: ADC group regular.
389 * Refer to corresponding unitary functions into
390 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
391 * (functions with prefix "REG").
392 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
393 * is conditioned to ADC state:
394 * ADC instance must be disabled.
395 * This condition is applied to all ADC features, for efficiency
396 * and compatibility over all STM32 families. However, the different
397 * features can be set under different ADC state conditions
398 * (setting possible with ADC enabled without conversion on going,
399 * ADC enabled with conversion on going, ...)
400 * Each feature can be updated afterwards with a unitary function
401 * and potentially with ADC in a different state than disabled,
402 * refer to description of each function for setting
403 * conditioned to ADC state.
404 */
405 typedef struct
406 {
407 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
408 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
409 @note On this STM32 series, setting of external trigger edge is performed
410 using function @ref LL_ADC_REG_StartConversionExtTrig().
411
412 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
413
414 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
415 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
416 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
417
418 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
419
420 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
421 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
422 @note This parameter has an effect only if group regular sequencer is enabled
423 (scan length of 2 ranks or more).
424
425 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
426
427 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
428 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
429 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
430
431 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
432
433 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
434 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
435
436 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
437
438 } LL_ADC_REG_InitTypeDef;
439
440 /**
441 * @brief Structure definition of some features of ADC group injected.
442 * @note These parameters have an impact on ADC scope: ADC group injected.
443 * Refer to corresponding unitary functions into
444 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
445 * (functions with prefix "INJ").
446 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
447 * is conditioned to ADC state:
448 * ADC instance must be disabled.
449 * This condition is applied to all ADC features, for efficiency
450 * and compatibility over all STM32 families. However, the different
451 * features can be set under different ADC state conditions
452 * (setting possible with ADC enabled without conversion on going,
453 * ADC enabled with conversion on going, ...)
454 * Each feature can be updated afterwards with a unitary function
455 * and potentially with ADC in a different state than disabled,
456 * refer to description of each function for setting
457 * conditioned to ADC state.
458 */
459 typedef struct
460 {
461 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
462 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
463 @note On this STM32 series, setting of external trigger edge is performed
464 using function @ref LL_ADC_INJ_StartConversionExtTrig().
465
466 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
467
468 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
469 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
470 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
471
472 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
473
474 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
475 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
476 @note This parameter has an effect only if group injected sequencer is enabled
477 (scan length of 2 ranks or more).
478
479 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
480
481 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
482 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
483 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
484
485 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
486
487 } LL_ADC_INJ_InitTypeDef;
488
489 /**
490 * @}
491 */
492 #endif /* USE_FULL_LL_DRIVER */
493
494 /* Exported constants --------------------------------------------------------*/
495 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
496 * @{
497 */
498
499 /** @defgroup ADC_LL_EC_FLAG ADC flags
500 * @brief Flags defines which can be used with LL_ADC_ReadReg function
501 * @{
502 */
503 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
504 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
505 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
506 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
507 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
508 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
509 #if defined(ADC_MULTIMODE_SUPPORT)
510 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
511 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
512 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
513 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
514 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
515 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
516 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
517 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
518 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
519 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
520 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
521 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
522 #endif
523 /**
524 * @}
525 */
526
527 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
528 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
529 * @{
530 */
531 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
532 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
533 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
534 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
535 /**
536 * @}
537 */
538
539 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
540 * @{
541 */
542 /* List of ADC registers intended to be used (most commonly) with */
543 /* DMA transfer. */
544 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
545 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000UL /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
546 #if defined(ADC_MULTIMODE_SUPPORT)
547 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001UL /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
548 #endif
549 /**
550 * @}
551 */
552
553 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
554 * @{
555 */
556 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000UL /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
557 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
558 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
559 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
560 /**
561 * @}
562 */
563
564 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
565 * @{
566 */
567 /* Note: Other measurement paths to internal channels may be available */
568 /* (connections to other peripherals). */
569 /* If they are not listed below, they do not require any specific */
570 /* path enable. In this case, Access to measurement path is done */
571 /* only by selecting the corresponding ADC internal channel. */
572 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000UL /*!< ADC measurement paths all disabled */
573 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
574 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
575 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
576 /**
577 * @}
578 */
579
580 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
581 * @{
582 */
583 #define LL_ADC_RESOLUTION_12B 0x00000000UL /*!< ADC resolution 12 bits */
584 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
585 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
586 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
587 /**
588 * @}
589 */
590
591 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
592 * @{
593 */
594 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000UL /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
595 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
596 /**
597 * @}
598 */
599
600 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
601 * @{
602 */
603 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
604 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
605 /**
606 * @}
607 */
608
609 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
610 * @{
611 */
612 #define LL_ADC_GROUP_REGULAR 0x00000001UL /*!< ADC group regular (available on all STM32 devices) */
613 #define LL_ADC_GROUP_INJECTED 0x00000002UL /*!< ADC group injected (not available on all STM32 devices)*/
614 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003UL /*!< ADC both groups regular and injected */
615 /**
616 * @}
617 */
618
619 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
620 * @{
621 */
622 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
623 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
624 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
625 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
626 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
627 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
628 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
629 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
630 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
631 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
632 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
633 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
634 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
635 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
636 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
637 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
638 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
639 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
640 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
641 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */
642 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */
643 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
644 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */
645 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
646 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
647 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
648 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
649 /**
650 * @}
651 */
652
653 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
654 * @{
655 */
656 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000UL /*!< ADC group regular conversion trigger internal: SW start. */
657 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
658 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
659 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
660 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
661 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
662 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
663 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
664 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
665 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
666 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
667 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
668 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
669 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
670 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
671 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
672 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
673 /**
674 * @}
675 */
676
677 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
678 * @{
679 */
680 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
681 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
682 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
683 /**
684 * @}
685 */
686
687 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
688 * @{
689 */
690 #define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */
691 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
692 /**
693 * @}
694 */
695
696 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
697 * @{
698 */
699 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000UL /*!< ADC conversions are not transferred by DMA */
700 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
701 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
702 /**
703 * @}
704 */
705
706 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
707 * @{
708 */
709 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000UL /*!< ADC flag EOC (end of unitary conversion) selected */
710 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
711 /**
712 * @}
713 */
714
715 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
716 * @{
717 */
718 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
719 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
720 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
721 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
722 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
723 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
724 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
725 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
726 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
727 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
728 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
729 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
730 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
731 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
732 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
733 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
734 /**
735 * @}
736 */
737
738 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
739 * @{
740 */
741 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group regular sequencer discontinuous mode disable */
742 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
743 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
744 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
745 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
746 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
747 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
748 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
749 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
750 /**
751 * @}
752 */
753
754 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
755 * @{
756 */
757 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
758 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
759 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
760 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
761 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
762 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
763 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
764 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
765 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
766 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
767 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
768 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
769 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
770 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
771 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
772 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
773 /**
774 * @}
775 */
776
777 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
778 * @{
779 */
780 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000UL /*!< ADC group injected conversion trigger internal: SW start. */
781 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
782 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
783 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
784 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
785 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
786 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
787 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
788 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
789 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
790 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
791 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
792 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
793 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
794 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
795 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
796 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
797 /**
798 * @}
799 */
800
801 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
802 * @{
803 */
804 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
805 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
806 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
807 /**
808 * @}
809 */
810
811 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
812 * @{
813 */
814 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
815 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
816 /**
817 * @}
818 */
819
820
821 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
822 * @{
823 */
824 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
825 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
826 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
827 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
828 /**
829 * @}
830 */
831
832 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
833 * @{
834 */
835 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group injected sequencer discontinuous mode disable */
836 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
837 /**
838 * @}
839 */
840
841 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
842 * @{
843 */
844 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001UL) /*!< ADC group injected sequencer rank 1 */
845 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002UL) /*!< ADC group injected sequencer rank 2 */
846 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003UL) /*!< ADC group injected sequencer rank 3 */
847 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004UL) /*!< ADC group injected sequencer rank 4 */
848 /**
849 * @}
850 */
851
852 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
853 * @{
854 */
855 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000UL /*!< Sampling time 3 ADC clock cycles */
856 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
857 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
858 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
859 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
860 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
861 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
862 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
863 /**
864 * @}
865 */
866
867 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
868 * @{
869 */
870 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
871 /**
872 * @}
873 */
874
875 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
876 * @{
877 */
878 #define LL_ADC_AWD_DISABLE 0x00000000UL /*!< ADC analog watchdog monitoring disabled */
879 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
880 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
881 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
882 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
883 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
884 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
885 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
886 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
887 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
888 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
889 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
890 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
891 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
892 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
893 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
894 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
895 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
896 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
897 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
898 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
899 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
900 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
901 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
902 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
903 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
904 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
905 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
906 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
907 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
908 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
909 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
910 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
911 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
912 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
913 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
914 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
915 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
916 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
917 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
918 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
919 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
920 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
921 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
922 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
923 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
924 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
925 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
926 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
927 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
928 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
929 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
930 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
931 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
932 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
933 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
934 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
935 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
936 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
937 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
938 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
939 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
940 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
941 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
942 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
943 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
944 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
945 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
946 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
947 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
948 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
949 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
950 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
951 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
952 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
953 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
954 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
955 /**
956 * @}
957 */
958
959 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
960 * @{
961 */
962 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
963 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
964 /**
965 * @}
966 */
967
968 #if defined(ADC_MULTIMODE_SUPPORT)
969 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
970 * @{
971 */
972 #define LL_ADC_MULTI_INDEPENDENT 0x00000000UL /*!< ADC dual mode disabled (ADC independent mode) */
973 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
974 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
975 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
976 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
977 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
978 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
979 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
980 #if defined(ADC3)
981 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
982 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
983 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
984 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
985 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
986 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
987 #endif
988 /**
989 * @}
990 */
991
992 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
993 * @{
994 */
995 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000UL /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
996 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
997 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
998 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
999 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
1000 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
1001 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1002 /**
1003 * @}
1004 */
1005
1006 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1007 * @{
1008 */
1009 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000UL /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
1010 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1011 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1012 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1013 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1014 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1015 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1016 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1017 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
1018 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
1019 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
1020 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
1021 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
1022 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
1023 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
1024 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
1025 /**
1026 * @}
1027 */
1028
1029 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1030 * @{
1031 */
1032 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1033 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1034 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1035 /**
1036 * @}
1037 */
1038
1039 #endif /* ADC_MULTIMODE_SUPPORT */
1040
1041
1042 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1043 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1044 * not timeout values.
1045 * For details on delays values, refer to descriptions in source code
1046 * above each literal definition.
1047 * @{
1048 */
1049
1050 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1051 /* not timeout values. */
1052 /* Timeout values for ADC operations are dependent to device clock */
1053 /* configuration (system clock versus ADC clock), */
1054 /* and therefore must be defined in user application. */
1055 /* Indications for estimation of ADC timeout delays, for this */
1056 /* STM32 series: */
1057 /* - ADC enable time: maximum delay is 2us */
1058 /* (refer to device datasheet, parameter "tSTAB") */
1059 /* - ADC conversion time: duration depending on ADC clock and ADC */
1060 /* configuration. */
1061 /* (refer to device reference manual, section "Timing") */
1062
1063 /* Delay for internal voltage reference stabilization time. */
1064 /* Delay set to maximum value (refer to device datasheet, */
1065 /* parameter "tSTART"). */
1066 /* Unit: us */
1067 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */
1068
1069 /* Delay for temperature sensor stabilization time. */
1070 /* Literal set to maximum value (refer to device datasheet, */
1071 /* parameter "tSTART"). */
1072 /* Unit: us */
1073 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */
1074
1075 /**
1076 * @}
1077 */
1078
1079 /**
1080 * @}
1081 */
1082
1083
1084 /* Exported macro ------------------------------------------------------------*/
1085 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1086 * @{
1087 */
1088
1089 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1090 * @{
1091 */
1092
1093 /**
1094 * @brief Write a value in ADC register
1095 * @param __INSTANCE__ ADC Instance
1096 * @param __REG__ Register to be written
1097 * @param __VALUE__ Value to be written in the register
1098 * @retval None
1099 */
1100 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1101
1102 /**
1103 * @brief Read a value in ADC register
1104 * @param __INSTANCE__ ADC Instance
1105 * @param __REG__ Register to be read
1106 * @retval Register value
1107 */
1108 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1109 /**
1110 * @}
1111 */
1112
1113 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1114 * @{
1115 */
1116
1117 /**
1118 * @brief Helper macro to get ADC channel number in decimal format
1119 * from literals LL_ADC_CHANNEL_x.
1120 * @note Example:
1121 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1122 * will return decimal number "4".
1123 * @note The input can be a value from functions where a channel
1124 * number is returned, either defined with number
1125 * or with bitfield (only one bit must be set).
1126 * @param __CHANNEL__ This parameter can be one of the following values:
1127 * @arg @ref LL_ADC_CHANNEL_0
1128 * @arg @ref LL_ADC_CHANNEL_1
1129 * @arg @ref LL_ADC_CHANNEL_2
1130 * @arg @ref LL_ADC_CHANNEL_3
1131 * @arg @ref LL_ADC_CHANNEL_4
1132 * @arg @ref LL_ADC_CHANNEL_5
1133 * @arg @ref LL_ADC_CHANNEL_6
1134 * @arg @ref LL_ADC_CHANNEL_7
1135 * @arg @ref LL_ADC_CHANNEL_8
1136 * @arg @ref LL_ADC_CHANNEL_9
1137 * @arg @ref LL_ADC_CHANNEL_10
1138 * @arg @ref LL_ADC_CHANNEL_11
1139 * @arg @ref LL_ADC_CHANNEL_12
1140 * @arg @ref LL_ADC_CHANNEL_13
1141 * @arg @ref LL_ADC_CHANNEL_14
1142 * @arg @ref LL_ADC_CHANNEL_15
1143 * @arg @ref LL_ADC_CHANNEL_16
1144 * @arg @ref LL_ADC_CHANNEL_17
1145 * @arg @ref LL_ADC_CHANNEL_18
1146 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1147 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1148 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1149 *
1150 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1151 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1152 * @retval Value between Min_Data=0 and Max_Data=18
1153 */
1154 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1155 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1156
1157 /**
1158 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1159 * from number in decimal format.
1160 * @note Example:
1161 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1162 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1163 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1164 * @retval Returned value can be one of the following values:
1165 * @arg @ref LL_ADC_CHANNEL_0
1166 * @arg @ref LL_ADC_CHANNEL_1
1167 * @arg @ref LL_ADC_CHANNEL_2
1168 * @arg @ref LL_ADC_CHANNEL_3
1169 * @arg @ref LL_ADC_CHANNEL_4
1170 * @arg @ref LL_ADC_CHANNEL_5
1171 * @arg @ref LL_ADC_CHANNEL_6
1172 * @arg @ref LL_ADC_CHANNEL_7
1173 * @arg @ref LL_ADC_CHANNEL_8
1174 * @arg @ref LL_ADC_CHANNEL_9
1175 * @arg @ref LL_ADC_CHANNEL_10
1176 * @arg @ref LL_ADC_CHANNEL_11
1177 * @arg @ref LL_ADC_CHANNEL_12
1178 * @arg @ref LL_ADC_CHANNEL_13
1179 * @arg @ref LL_ADC_CHANNEL_14
1180 * @arg @ref LL_ADC_CHANNEL_15
1181 * @arg @ref LL_ADC_CHANNEL_16
1182 * @arg @ref LL_ADC_CHANNEL_17
1183 * @arg @ref LL_ADC_CHANNEL_18
1184 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1185 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1186 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1187 *
1188 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1189 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1190 * (1) For ADC channel read back from ADC register,
1191 * comparison with internal channel parameter to be done
1192 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1193 */
1194 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1195 (((__DECIMAL_NB__) <= 9UL) \
1196 ? ( \
1197 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1198 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1199 ) \
1200 : \
1201 ( \
1202 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1203 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1204 ) \
1205 )
1206
1207 /**
1208 * @brief Helper macro to determine whether the selected channel
1209 * corresponds to literal definitions of driver.
1210 * @note The different literal definitions of ADC channels are:
1211 * - ADC internal channel:
1212 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1213 * - ADC external channel (channel connected to a GPIO pin):
1214 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1215 * @note The channel parameter must be a value defined from literal
1216 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1217 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1218 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1219 * must not be a value from functions where a channel number is
1220 * returned from ADC registers,
1221 * because internal and external channels share the same channel
1222 * number in ADC registers. The differentiation is made only with
1223 * parameters definitions of driver.
1224 * @param __CHANNEL__ This parameter can be one of the following values:
1225 * @arg @ref LL_ADC_CHANNEL_0
1226 * @arg @ref LL_ADC_CHANNEL_1
1227 * @arg @ref LL_ADC_CHANNEL_2
1228 * @arg @ref LL_ADC_CHANNEL_3
1229 * @arg @ref LL_ADC_CHANNEL_4
1230 * @arg @ref LL_ADC_CHANNEL_5
1231 * @arg @ref LL_ADC_CHANNEL_6
1232 * @arg @ref LL_ADC_CHANNEL_7
1233 * @arg @ref LL_ADC_CHANNEL_8
1234 * @arg @ref LL_ADC_CHANNEL_9
1235 * @arg @ref LL_ADC_CHANNEL_10
1236 * @arg @ref LL_ADC_CHANNEL_11
1237 * @arg @ref LL_ADC_CHANNEL_12
1238 * @arg @ref LL_ADC_CHANNEL_13
1239 * @arg @ref LL_ADC_CHANNEL_14
1240 * @arg @ref LL_ADC_CHANNEL_15
1241 * @arg @ref LL_ADC_CHANNEL_16
1242 * @arg @ref LL_ADC_CHANNEL_17
1243 * @arg @ref LL_ADC_CHANNEL_18
1244 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1245 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1246 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1247 *
1248 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1249 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1250 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1251 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1252 */
1253 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1254 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1255
1256 /**
1257 * @brief Helper macro to convert a channel defined from parameter
1258 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1259 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1260 * to its equivalent parameter definition of a ADC external channel
1261 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1262 * @note The channel parameter can be, additionally to a value
1263 * defined from parameter definition of a ADC internal channel
1264 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1265 * a value defined from parameter definition of
1266 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1267 * or a value from functions where a channel number is returned
1268 * from ADC registers.
1269 * @param __CHANNEL__ This parameter can be one of the following values:
1270 * @arg @ref LL_ADC_CHANNEL_0
1271 * @arg @ref LL_ADC_CHANNEL_1
1272 * @arg @ref LL_ADC_CHANNEL_2
1273 * @arg @ref LL_ADC_CHANNEL_3
1274 * @arg @ref LL_ADC_CHANNEL_4
1275 * @arg @ref LL_ADC_CHANNEL_5
1276 * @arg @ref LL_ADC_CHANNEL_6
1277 * @arg @ref LL_ADC_CHANNEL_7
1278 * @arg @ref LL_ADC_CHANNEL_8
1279 * @arg @ref LL_ADC_CHANNEL_9
1280 * @arg @ref LL_ADC_CHANNEL_10
1281 * @arg @ref LL_ADC_CHANNEL_11
1282 * @arg @ref LL_ADC_CHANNEL_12
1283 * @arg @ref LL_ADC_CHANNEL_13
1284 * @arg @ref LL_ADC_CHANNEL_14
1285 * @arg @ref LL_ADC_CHANNEL_15
1286 * @arg @ref LL_ADC_CHANNEL_16
1287 * @arg @ref LL_ADC_CHANNEL_17
1288 * @arg @ref LL_ADC_CHANNEL_18
1289 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1290 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1291 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1292 *
1293 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1294 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1295 * @retval Returned value can be one of the following values:
1296 * @arg @ref LL_ADC_CHANNEL_0
1297 * @arg @ref LL_ADC_CHANNEL_1
1298 * @arg @ref LL_ADC_CHANNEL_2
1299 * @arg @ref LL_ADC_CHANNEL_3
1300 * @arg @ref LL_ADC_CHANNEL_4
1301 * @arg @ref LL_ADC_CHANNEL_5
1302 * @arg @ref LL_ADC_CHANNEL_6
1303 * @arg @ref LL_ADC_CHANNEL_7
1304 * @arg @ref LL_ADC_CHANNEL_8
1305 * @arg @ref LL_ADC_CHANNEL_9
1306 * @arg @ref LL_ADC_CHANNEL_10
1307 * @arg @ref LL_ADC_CHANNEL_11
1308 * @arg @ref LL_ADC_CHANNEL_12
1309 * @arg @ref LL_ADC_CHANNEL_13
1310 * @arg @ref LL_ADC_CHANNEL_14
1311 * @arg @ref LL_ADC_CHANNEL_15
1312 * @arg @ref LL_ADC_CHANNEL_16
1313 * @arg @ref LL_ADC_CHANNEL_17
1314 * @arg @ref LL_ADC_CHANNEL_18
1315 */
1316 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1317 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1318
1319 /**
1320 * @brief Helper macro to determine whether the internal channel
1321 * selected is available on the ADC instance selected.
1322 * @note The channel parameter must be a value defined from parameter
1323 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1324 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1325 * must not be a value defined from parameter definition of
1326 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1327 * or a value from functions where a channel number is
1328 * returned from ADC registers,
1329 * because internal and external channels share the same channel
1330 * number in ADC registers. The differentiation is made only with
1331 * parameters definitions of driver.
1332 * @param __ADC_INSTANCE__ ADC instance
1333 * @param __CHANNEL__ This parameter can be one of the following values:
1334 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1335 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1336 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1337 *
1338 * (1) On STM32F4, parameter available only on ADC instance: ADC1.
1339 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1340 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1341 * Value "1" if the internal channel selected is available on the ADC instance selected.
1342 */
1343 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1344 ( \
1345 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1346 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1347 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1348 )
1349 /**
1350 * @brief Helper macro to define ADC analog watchdog parameter:
1351 * define a single channel to monitor with analog watchdog
1352 * from sequencer channel and groups definition.
1353 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1354 * Example:
1355 * LL_ADC_SetAnalogWDMonitChannels(
1356 * ADC1, LL_ADC_AWD1,
1357 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1358 * @param __CHANNEL__ This parameter can be one of the following values:
1359 * @arg @ref LL_ADC_CHANNEL_0
1360 * @arg @ref LL_ADC_CHANNEL_1
1361 * @arg @ref LL_ADC_CHANNEL_2
1362 * @arg @ref LL_ADC_CHANNEL_3
1363 * @arg @ref LL_ADC_CHANNEL_4
1364 * @arg @ref LL_ADC_CHANNEL_5
1365 * @arg @ref LL_ADC_CHANNEL_6
1366 * @arg @ref LL_ADC_CHANNEL_7
1367 * @arg @ref LL_ADC_CHANNEL_8
1368 * @arg @ref LL_ADC_CHANNEL_9
1369 * @arg @ref LL_ADC_CHANNEL_10
1370 * @arg @ref LL_ADC_CHANNEL_11
1371 * @arg @ref LL_ADC_CHANNEL_12
1372 * @arg @ref LL_ADC_CHANNEL_13
1373 * @arg @ref LL_ADC_CHANNEL_14
1374 * @arg @ref LL_ADC_CHANNEL_15
1375 * @arg @ref LL_ADC_CHANNEL_16
1376 * @arg @ref LL_ADC_CHANNEL_17
1377 * @arg @ref LL_ADC_CHANNEL_18
1378 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1379 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1380 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1381 *
1382 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1383 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1384 * (1) For ADC channel read back from ADC register,
1385 * comparison with internal channel parameter to be done
1386 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1387 * @param __GROUP__ This parameter can be one of the following values:
1388 * @arg @ref LL_ADC_GROUP_REGULAR
1389 * @arg @ref LL_ADC_GROUP_INJECTED
1390 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1391 * @retval Returned value can be one of the following values:
1392 * @arg @ref LL_ADC_AWD_DISABLE
1393 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1394 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1395 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1396 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1397 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1398 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1399 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1400 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1401 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1402 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1403 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1404 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1405 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1406 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1407 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1408 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1409 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1410 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1411 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1412 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1413 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1414 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1415 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1416 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1417 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1418 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1419 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1420 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1421 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1422 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1423 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1424 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1425 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1426 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1427 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1428 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1429 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1430 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1431 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1432 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1433 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1434 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1435 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1436 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1437 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1438 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1439 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1440 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1441 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1442 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1443 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1444 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1445 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1446 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1447 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1448 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1449 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1450 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1451 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
1452 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1453 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1454 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1455 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1456 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
1457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
1458 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
1459 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1460 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
1461 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1462 *
1463 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1464 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1465 */
1466 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1467 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1468 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1469 : \
1470 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1471 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1472 : \
1473 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1474 )
1475
1476 /**
1477 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1478 * or low in function of ADC resolution, when ADC resolution is
1479 * different of 12 bits.
1480 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1481 * Example, with a ADC resolution of 8 bits, to set the value of
1482 * analog watchdog threshold high (on 8 bits):
1483 * LL_ADC_SetAnalogWDThresholds
1484 * (< ADCx param >,
1485 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1486 * );
1487 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1488 * @arg @ref LL_ADC_RESOLUTION_12B
1489 * @arg @ref LL_ADC_RESOLUTION_10B
1490 * @arg @ref LL_ADC_RESOLUTION_8B
1491 * @arg @ref LL_ADC_RESOLUTION_6B
1492 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1493 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1494 */
1495 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1496 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
1497
1498 /**
1499 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1500 * or low in function of ADC resolution, when ADC resolution is
1501 * different of 12 bits.
1502 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1503 * Example, with a ADC resolution of 8 bits, to get the value of
1504 * analog watchdog threshold high (on 8 bits):
1505 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1506 * (LL_ADC_RESOLUTION_8B,
1507 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1508 * );
1509 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1510 * @arg @ref LL_ADC_RESOLUTION_12B
1511 * @arg @ref LL_ADC_RESOLUTION_10B
1512 * @arg @ref LL_ADC_RESOLUTION_8B
1513 * @arg @ref LL_ADC_RESOLUTION_6B
1514 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1515 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1516 */
1517 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1518 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
1519
1520 #if defined(ADC_MULTIMODE_SUPPORT)
1521 /**
1522 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1523 * or ADC slave from raw value with both ADC conversion data concatenated.
1524 * @note This macro is intended to be used when multimode transfer by DMA
1525 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1526 * In this case the transferred data need to processed with this macro
1527 * to separate the conversion data of ADC master and ADC slave.
1528 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1529 * @arg @ref LL_ADC_MULTI_MASTER
1530 * @arg @ref LL_ADC_MULTI_SLAVE
1531 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1532 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1533 */
1534 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1535 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1536 #endif
1537
1538 /**
1539 * @brief Helper macro to select the ADC common instance
1540 * to which is belonging the selected ADC instance.
1541 * @note ADC common register instance can be used for:
1542 * - Set parameters common to several ADC instances
1543 * - Multimode (for devices with several ADC instances)
1544 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1545 * @param __ADCx__ ADC instance
1546 * @retval ADC common register instance
1547 */
1548 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1549 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1550 (ADC123_COMMON)
1551 #elif defined(ADC1) && defined(ADC2)
1552 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1553 (ADC12_COMMON)
1554 #else
1555 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1556 (ADC1_COMMON)
1557 #endif
1558
1559 /**
1560 * @brief Helper macro to check if all ADC instances sharing the same
1561 * ADC common instance are disabled.
1562 * @note This check is required by functions with setting conditioned to
1563 * ADC state:
1564 * All ADC instances of the ADC common group must be disabled.
1565 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1566 * @note On devices with only 1 ADC common instance, parameter of this macro
1567 * is useless and can be ignored (parameter kept for compatibility
1568 * with devices featuring several ADC common instances).
1569 * @param __ADCXY_COMMON__ ADC common instance
1570 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1571 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1572 * are disabled.
1573 * Value "1" if at least one ADC instance sharing the same ADC common instance
1574 * is enabled.
1575 */
1576 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1577 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1578 (LL_ADC_IsEnabled(ADC1) | \
1579 LL_ADC_IsEnabled(ADC2) | \
1580 LL_ADC_IsEnabled(ADC3) )
1581 #elif defined(ADC1) && defined(ADC2)
1582 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1583 (LL_ADC_IsEnabled(ADC1) | \
1584 LL_ADC_IsEnabled(ADC2) )
1585 #else
1586 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1587 (LL_ADC_IsEnabled(ADC1))
1588 #endif
1589
1590 /**
1591 * @brief Helper macro to define the ADC conversion data full-scale digital
1592 * value corresponding to the selected ADC resolution.
1593 * @note ADC conversion data full-scale corresponds to voltage range
1594 * determined by analog voltage references Vref+ and Vref-
1595 * (refer to reference manual).
1596 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1597 * @arg @ref LL_ADC_RESOLUTION_12B
1598 * @arg @ref LL_ADC_RESOLUTION_10B
1599 * @arg @ref LL_ADC_RESOLUTION_8B
1600 * @arg @ref LL_ADC_RESOLUTION_6B
1601 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1602 */
1603 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1604 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))
1605
1606 /**
1607 * @brief Helper macro to convert the ADC conversion data from
1608 * a resolution to another resolution.
1609 * @param __DATA__ ADC conversion data to be converted
1610 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1611 * This parameter can be one of the following values:
1612 * @arg @ref LL_ADC_RESOLUTION_12B
1613 * @arg @ref LL_ADC_RESOLUTION_10B
1614 * @arg @ref LL_ADC_RESOLUTION_8B
1615 * @arg @ref LL_ADC_RESOLUTION_6B
1616 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1617 * This parameter can be one of the following values:
1618 * @arg @ref LL_ADC_RESOLUTION_12B
1619 * @arg @ref LL_ADC_RESOLUTION_10B
1620 * @arg @ref LL_ADC_RESOLUTION_8B
1621 * @arg @ref LL_ADC_RESOLUTION_6B
1622 * @retval ADC conversion data to the requested resolution
1623 */
1624 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1625 (((__DATA__) \
1626 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) \
1627 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)) \
1628 )
1629
1630 /**
1631 * @brief Helper macro to calculate the voltage (unit: mVolt)
1632 * corresponding to a ADC conversion data (unit: digital value).
1633 * @note Analog reference voltage (Vref+) must be either known from
1634 * user board environment or can be calculated using ADC measurement
1635 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1636 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1637 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1638 * (unit: digital value).
1639 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1640 * @arg @ref LL_ADC_RESOLUTION_12B
1641 * @arg @ref LL_ADC_RESOLUTION_10B
1642 * @arg @ref LL_ADC_RESOLUTION_8B
1643 * @arg @ref LL_ADC_RESOLUTION_6B
1644 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1645 */
1646 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1647 __ADC_DATA__,\
1648 __ADC_RESOLUTION__) \
1649 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1650 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1651 )
1652
1653 /**
1654 * @brief Helper macro to calculate analog reference voltage (Vref+)
1655 * (unit: mVolt) from ADC conversion data of internal voltage
1656 * reference VrefInt.
1657 * @note Computation is using VrefInt calibration value
1658 * stored in system memory for each device during production.
1659 * @note This voltage depends on user board environment: voltage level
1660 * connected to pin Vref+.
1661 * On devices with small package, the pin Vref+ is not present
1662 * and internally bonded to pin Vdda.
1663 * @note On this STM32 series, calibration data of internal voltage reference
1664 * VrefInt corresponds to a resolution of 12 bits,
1665 * this is the recommended ADC resolution to convert voltage of
1666 * internal voltage reference VrefInt.
1667 * Otherwise, this macro performs the processing to scale
1668 * ADC conversion data to 12 bits.
1669 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1670 * of internal voltage reference VrefInt (unit: digital value).
1671 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1672 * @arg @ref LL_ADC_RESOLUTION_12B
1673 * @arg @ref LL_ADC_RESOLUTION_10B
1674 * @arg @ref LL_ADC_RESOLUTION_8B
1675 * @arg @ref LL_ADC_RESOLUTION_6B
1676 * @retval Analog reference voltage (unit: mV)
1677 */
1678 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1679 __ADC_RESOLUTION__) \
1680 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1681 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1682 (__ADC_RESOLUTION__), \
1683 LL_ADC_RESOLUTION_12B))
1684
1685 /* Note: On device STM32F4x9, calibration parameter TS_CAL2 is not available. */
1686 /* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
1687 /* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */
1688 #if !defined(STM32F469) && !defined(STM32F479xx) && !defined(STM32F429xx) && !defined(STM32F439xx)
1689 /**
1690 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1691 * from ADC conversion data of internal temperature sensor.
1692 * @note Computation is using temperature sensor calibration values
1693 * stored in system memory for each device during production.
1694 * @note Calculation formula:
1695 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1696 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1697 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1698 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1699 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1700 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1701 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1702 * TEMP_DEGC_CAL1 (calibrated in factory)
1703 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1704 * TEMP_DEGC_CAL2 (calibrated in factory)
1705 * Caution: Calculation relevancy under reserve that calibration
1706 * parameters are correct (address and data).
1707 * To calculate temperature using temperature sensor
1708 * datasheet typical values (generic values less, therefore
1709 * less accurate than calibrated values),
1710 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1711 * @note As calculation input, the analog reference voltage (Vref+) must be
1712 * defined as it impacts the ADC LSB equivalent voltage.
1713 * @note Analog reference voltage (Vref+) must be either known from
1714 * user board environment or can be calculated using ADC measurement
1715 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1716 * @note On this STM32 series, calibration data of temperature sensor
1717 * corresponds to a resolution of 12 bits,
1718 * this is the recommended ADC resolution to convert voltage of
1719 * temperature sensor.
1720 * Otherwise, this macro performs the processing to scale
1721 * ADC conversion data to 12 bits.
1722 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1723 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1724 * temperature sensor (unit: digital value).
1725 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1726 * sensor voltage has been measured.
1727 * This parameter can be one of the following values:
1728 * @arg @ref LL_ADC_RESOLUTION_12B
1729 * @arg @ref LL_ADC_RESOLUTION_10B
1730 * @arg @ref LL_ADC_RESOLUTION_8B
1731 * @arg @ref LL_ADC_RESOLUTION_6B
1732 * @retval Temperature (unit: degree Celsius)
1733 */
1734 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1735 __TEMPSENSOR_ADC_DATA__,\
1736 __ADC_RESOLUTION__) \
1737 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1738 (__ADC_RESOLUTION__), \
1739 LL_ADC_RESOLUTION_12B) \
1740 * (__VREFANALOG_VOLTAGE__)) \
1741 / TEMPSENSOR_CAL_VREFANALOG) \
1742 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1743 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1744 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1745 ) + TEMPSENSOR_CAL1_TEMP \
1746 )
1747 #endif
1748
1749 /**
1750 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1751 * from ADC conversion data of internal temperature sensor.
1752 * @note Computation is using temperature sensor typical values
1753 * (refer to device datasheet).
1754 * @note Calculation formula:
1755 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1756 * / Avg_Slope + CALx_TEMP
1757 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1758 * (unit: digital value)
1759 * Avg_Slope = temperature sensor slope
1760 * (unit: uV/Degree Celsius)
1761 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1762 * temperature CALx_TEMP (unit: mV)
1763 * Caution: Calculation relevancy under reserve the temperature sensor
1764 * of the current device has characteristics in line with
1765 * datasheet typical values.
1766 * If temperature sensor calibration values are available on
1767 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1768 * temperature calculation will be more accurate using
1769 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1770 * @note As calculation input, the analog reference voltage (Vref+) must be
1771 * defined as it impacts the ADC LSB equivalent voltage.
1772 * @note Analog reference voltage (Vref+) must be either known from
1773 * user board environment or can be calculated using ADC measurement
1774 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1775 * @note ADC measurement data must correspond to a resolution of 12bits
1776 * (full scale digital value 4095). If not the case, the data must be
1777 * preliminarily rescaled to an equivalent resolution of 12 bits.
1778 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
1779 * On STM32F4, refer to device datasheet parameter "Avg_Slope".
1780 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
1781 * On STM32F4, refer to device datasheet parameter "V25".
1782 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
1783 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV)
1784 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value).
1785 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1786 * This parameter can be one of the following values:
1787 * @arg @ref LL_ADC_RESOLUTION_12B
1788 * @arg @ref LL_ADC_RESOLUTION_10B
1789 * @arg @ref LL_ADC_RESOLUTION_8B
1790 * @arg @ref LL_ADC_RESOLUTION_6B
1791 * @retval Temperature (unit: degree Celsius)
1792 */
1793 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1794 __TEMPSENSOR_TYP_CALX_V__,\
1795 __TEMPSENSOR_CALX_TEMP__,\
1796 __VREFANALOG_VOLTAGE__,\
1797 __TEMPSENSOR_ADC_DATA__,\
1798 __ADC_RESOLUTION__) \
1799 ((( ( \
1800 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1801 * 1000) \
1802 - \
1803 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1804 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1805 * 1000) \
1806 ) \
1807 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1808 ) + (__TEMPSENSOR_CALX_TEMP__) \
1809 )
1810
1811 /**
1812 * @}
1813 */
1814
1815 /**
1816 * @}
1817 */
1818
1819
1820 /* Exported functions --------------------------------------------------------*/
1821 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1822 * @{
1823 */
1824
1825 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1826 * @{
1827 */
1828 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1829 /* configuration of ADC instance, groups and multimode (if available): */
1830 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1831
1832 /**
1833 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1834 * ADC register address from ADC instance and a list of ADC registers
1835 * intended to be used (most commonly) with DMA transfer.
1836 * @note These ADC registers are data registers:
1837 * when ADC conversion data is available in ADC data registers,
1838 * ADC generates a DMA transfer request.
1839 * @note This macro is intended to be used with LL DMA driver, refer to
1840 * function "LL_DMA_ConfigAddresses()".
1841 * Example:
1842 * LL_DMA_ConfigAddresses(DMA1,
1843 * LL_DMA_CHANNEL_1,
1844 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1845 * (uint32_t)&< array or variable >,
1846 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1847 * @note For devices with several ADC: in multimode, some devices
1848 * use a different data register outside of ADC instance scope
1849 * (common data register). This macro manages this register difference,
1850 * only ADC instance has to be set as parameter.
1851 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
1852 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
1853 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
1854 * @param ADCx ADC instance
1855 * @param Register This parameter can be one of the following values:
1856 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1857 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1858 *
1859 * (1) Available on devices with several ADC instances.
1860 * @retval ADC register address
1861 */
1862 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1863 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1864 {
1865 uint32_t data_reg_addr = 0UL;
1866
1867 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1868 {
1869 /* Retrieve address of register DR */
1870 data_reg_addr = (uint32_t)&(ADCx->DR);
1871 }
1872 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1873 {
1874 /* Retrieve address of register CDR */
1875 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1876 }
1877
1878 return data_reg_addr;
1879 }
1880 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1881 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1882 {
1883 /* Retrieve address of register DR */
1884 return (uint32_t)&(ADCx->DR);
1885 }
1886 #endif
1887
1888 /**
1889 * @}
1890 */
1891
1892 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1893 * @{
1894 */
1895
1896 /**
1897 * @brief Set parameter common to several ADC: Clock source and prescaler.
1898 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
1899 * @param ADCxy_COMMON ADC common instance
1900 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1901 * @param CommonClock This parameter can be one of the following values:
1902 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1903 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1904 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1905 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1906 * @retval None
1907 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1908 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1909 {
1910 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1911 }
1912
1913 /**
1914 * @brief Get parameter common to several ADC: Clock source and prescaler.
1915 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
1916 * @param ADCxy_COMMON ADC common instance
1917 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1918 * @retval Returned value can be one of the following values:
1919 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1920 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1921 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1922 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1923 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)1924 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1925 {
1926 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1927 }
1928
1929 /**
1930 * @brief Set parameter common to several ADC: measurement path to internal
1931 * channels (VrefInt, temperature sensor, ...).
1932 * @note One or several values can be selected.
1933 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1934 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1935 * @note Stabilization time of measurement path to internal channel:
1936 * After enabling internal paths, before starting ADC conversion,
1937 * a delay is required for internal voltage reference and
1938 * temperature sensor stabilization time.
1939 * Refer to device datasheet.
1940 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1941 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1942 * @note ADC internal channel sampling time constraint:
1943 * For ADC conversion of internal channels,
1944 * a sampling time minimum value is required.
1945 * Refer to device datasheet.
1946 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
1947 * CCR VBATE LL_ADC_SetCommonPathInternalCh
1948 * @param ADCxy_COMMON ADC common instance
1949 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1950 * @param PathInternal This parameter can be a combination of the following values:
1951 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1952 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1953 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1954 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1955 * @retval None
1956 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1957 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1958 {
1959 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1960 }
1961
1962 /**
1963 * @brief Get parameter common to several ADC: measurement path to internal
1964 * channels (VrefInt, temperature sensor, ...).
1965 * @note One or several values can be selected.
1966 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1967 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1968 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
1969 * CCR VBATE LL_ADC_GetCommonPathInternalCh
1970 * @param ADCxy_COMMON ADC common instance
1971 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1972 * @retval Returned value can be a combination of the following values:
1973 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1974 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1975 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1976 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1977 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1978 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1979 {
1980 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1981 }
1982
1983 /**
1984 * @}
1985 */
1986
1987 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1988 * @{
1989 */
1990
1991 /**
1992 * @brief Set ADC resolution.
1993 * Refer to reference manual for alignments formats
1994 * dependencies to ADC resolutions.
1995 * @rmtoll CR1 RES LL_ADC_SetResolution
1996 * @param ADCx ADC instance
1997 * @param Resolution This parameter can be one of the following values:
1998 * @arg @ref LL_ADC_RESOLUTION_12B
1999 * @arg @ref LL_ADC_RESOLUTION_10B
2000 * @arg @ref LL_ADC_RESOLUTION_8B
2001 * @arg @ref LL_ADC_RESOLUTION_6B
2002 * @retval None
2003 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2004 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2005 {
2006 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
2007 }
2008
2009 /**
2010 * @brief Get ADC resolution.
2011 * Refer to reference manual for alignments formats
2012 * dependencies to ADC resolutions.
2013 * @rmtoll CR1 RES LL_ADC_GetResolution
2014 * @param ADCx ADC instance
2015 * @retval Returned value can be one of the following values:
2016 * @arg @ref LL_ADC_RESOLUTION_12B
2017 * @arg @ref LL_ADC_RESOLUTION_10B
2018 * @arg @ref LL_ADC_RESOLUTION_8B
2019 * @arg @ref LL_ADC_RESOLUTION_6B
2020 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2021 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2022 {
2023 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
2024 }
2025
2026 /**
2027 * @brief Set ADC conversion data alignment.
2028 * @note Refer to reference manual for alignments formats
2029 * dependencies to ADC resolutions.
2030 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2031 * @param ADCx ADC instance
2032 * @param DataAlignment This parameter can be one of the following values:
2033 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2034 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2035 * @retval None
2036 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2037 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2038 {
2039 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
2040 }
2041
2042 /**
2043 * @brief Get ADC conversion data alignment.
2044 * @note Refer to reference manual for alignments formats
2045 * dependencies to ADC resolutions.
2046 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2047 * @param ADCx ADC instance
2048 * @retval Returned value can be one of the following values:
2049 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2050 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2051 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2052 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2053 {
2054 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
2055 }
2056
2057 /**
2058 * @brief Set ADC sequencers scan mode, for all ADC groups
2059 * (group regular, group injected).
2060 * @note According to sequencers scan mode :
2061 * - If disabled: ADC conversion is performed in unitary conversion
2062 * mode (one channel converted, that defined in rank 1).
2063 * Configuration of sequencers of all ADC groups
2064 * (sequencer scan length, ...) is discarded: equivalent to
2065 * scan length of 1 rank.
2066 * - If enabled: ADC conversions are performed in sequence conversions
2067 * mode, according to configuration of sequencers of
2068 * each ADC group (sequencer scan length, ...).
2069 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2070 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2071 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
2072 * @param ADCx ADC instance
2073 * @param ScanMode This parameter can be one of the following values:
2074 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2075 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2076 * @retval None
2077 */
LL_ADC_SetSequencersScanMode(ADC_TypeDef * ADCx,uint32_t ScanMode)2078 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
2079 {
2080 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
2081 }
2082
2083 /**
2084 * @brief Get ADC sequencers scan mode, for all ADC groups
2085 * (group regular, group injected).
2086 * @note According to sequencers scan mode :
2087 * - If disabled: ADC conversion is performed in unitary conversion
2088 * mode (one channel converted, that defined in rank 1).
2089 * Configuration of sequencers of all ADC groups
2090 * (sequencer scan length, ...) is discarded: equivalent to
2091 * scan length of 1 rank.
2092 * - If enabled: ADC conversions are performed in sequence conversions
2093 * mode, according to configuration of sequencers of
2094 * each ADC group (sequencer scan length, ...).
2095 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2096 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2097 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
2098 * @param ADCx ADC instance
2099 * @retval Returned value can be one of the following values:
2100 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2101 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2102 */
LL_ADC_GetSequencersScanMode(ADC_TypeDef * ADCx)2103 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
2104 {
2105 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2106 }
2107
2108 /**
2109 * @}
2110 */
2111
2112 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2113 * @{
2114 */
2115
2116 /**
2117 * @brief Set ADC group regular conversion trigger source:
2118 * internal (SW start) or from external IP (timer event,
2119 * external interrupt line).
2120 * @note On this STM32 series, setting of external trigger edge is performed
2121 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2122 * @note Availability of parameters of trigger sources from timer
2123 * depends on timers availability on the selected device.
2124 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
2125 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
2126 * @param ADCx ADC instance
2127 * @param TriggerSource This parameter can be one of the following values:
2128 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2129 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2130 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2131 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2132 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2133 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2134 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2135 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2136 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2137 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2138 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2139 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2140 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2141 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2142 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2143 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2144 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2145 * @retval None
2146 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2147 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2148 {
2149 /* Note: On this STM32 series, ADC group regular external trigger edge */
2150 /* is used to perform a ADC conversion start. */
2151 /* This function does not set external trigger edge. */
2152 /* This feature is set using function */
2153 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2154 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2155 }
2156
2157 /**
2158 * @brief Get ADC group regular conversion trigger source:
2159 * internal (SW start) or from external IP (timer event,
2160 * external interrupt line).
2161 * @note To determine whether group regular trigger source is
2162 * internal (SW start) or external, without detail
2163 * of which peripheral is selected as external trigger,
2164 * (equivalent to
2165 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2166 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2167 * @note Availability of parameters of trigger sources from timer
2168 * depends on timers availability on the selected device.
2169 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2170 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2171 * @param ADCx ADC instance
2172 * @retval Returned value can be one of the following values:
2173 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2174 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2175 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2176 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2177 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2178 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2179 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2180 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2181 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2182 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2183 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2184 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2185 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2186 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2187 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2188 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2189 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2190 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2191 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2192 {
2193 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2194
2195 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2196 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2197 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2198
2199 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2200 /* to match with triggers literals definition. */
2201 return ((TriggerSource
2202 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2203 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2204 );
2205 }
2206
2207 /**
2208 * @brief Get ADC group regular conversion trigger source internal (SW start)
2209 or external.
2210 * @note In case of group regular trigger source set to external trigger,
2211 * to determine which peripheral is selected as external trigger,
2212 * use function @ref LL_ADC_REG_GetTriggerSource().
2213 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2214 * @param ADCx ADC instance
2215 * @retval Value "0" if trigger source external trigger
2216 * Value "1" if trigger source SW start.
2217 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2218 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2219 {
2220 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2221 }
2222
2223 /**
2224 * @brief Get ADC group regular conversion trigger polarity.
2225 * @note Applicable only for trigger source set to external trigger.
2226 * @note On this STM32 series, setting of external trigger edge is performed
2227 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2228 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2229 * @param ADCx ADC instance
2230 * @retval Returned value can be one of the following values:
2231 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2232 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2233 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2234 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2235 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2236 {
2237 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2238 }
2239
2240
2241 /**
2242 * @brief Set ADC group regular sequencer length and scan direction.
2243 * @note Description of ADC group regular sequencer features:
2244 * - For devices with sequencer fully configurable
2245 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2246 * sequencer length and each rank affectation to a channel
2247 * are configurable.
2248 * This function performs configuration of:
2249 * - Sequence length: Number of ranks in the scan sequence.
2250 * - Sequence direction: Unless specified in parameters, sequencer
2251 * scan direction is forward (from rank 1 to rank n).
2252 * Sequencer ranks are selected using
2253 * function "LL_ADC_REG_SetSequencerRanks()".
2254 * - For devices with sequencer not fully configurable
2255 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2256 * sequencer length and each rank affectation to a channel
2257 * are defined by channel number.
2258 * This function performs configuration of:
2259 * - Sequence length: Number of ranks in the scan sequence is
2260 * defined by number of channels set in the sequence,
2261 * rank of each channel is fixed by channel HW number.
2262 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2263 * - Sequence direction: Unless specified in parameters, sequencer
2264 * scan direction is forward (from lowest channel number to
2265 * highest channel number).
2266 * Sequencer ranks are selected using
2267 * function "LL_ADC_REG_SetSequencerChannels()".
2268 * @note On this STM32 series, group regular sequencer configuration
2269 * is conditioned to ADC instance sequencer mode.
2270 * If ADC instance sequencer mode is disabled, sequencers of
2271 * all groups (group regular, group injected) can be configured
2272 * but their execution is disabled (limited to rank 1).
2273 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2274 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2275 * ADC conversion on only 1 channel.
2276 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2277 * @param ADCx ADC instance
2278 * @param SequencerNbRanks This parameter can be one of the following values:
2279 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2280 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2281 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2282 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2283 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2284 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2285 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2286 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2287 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2288 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2289 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2290 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2291 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2292 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2293 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2294 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2295 * @retval None
2296 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2297 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2298 {
2299 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2300 }
2301
2302 /**
2303 * @brief Get ADC group regular sequencer length and scan direction.
2304 * @note Description of ADC group regular sequencer features:
2305 * - For devices with sequencer fully configurable
2306 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2307 * sequencer length and each rank affectation to a channel
2308 * are configurable.
2309 * This function retrieves:
2310 * - Sequence length: Number of ranks in the scan sequence.
2311 * - Sequence direction: Unless specified in parameters, sequencer
2312 * scan direction is forward (from rank 1 to rank n).
2313 * Sequencer ranks are selected using
2314 * function "LL_ADC_REG_SetSequencerRanks()".
2315 * - For devices with sequencer not fully configurable
2316 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2317 * sequencer length and each rank affectation to a channel
2318 * are defined by channel number.
2319 * This function retrieves:
2320 * - Sequence length: Number of ranks in the scan sequence is
2321 * defined by number of channels set in the sequence,
2322 * rank of each channel is fixed by channel HW number.
2323 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2324 * - Sequence direction: Unless specified in parameters, sequencer
2325 * scan direction is forward (from lowest channel number to
2326 * highest channel number).
2327 * Sequencer ranks are selected using
2328 * function "LL_ADC_REG_SetSequencerChannels()".
2329 * @note On this STM32 series, group regular sequencer configuration
2330 * is conditioned to ADC instance sequencer mode.
2331 * If ADC instance sequencer mode is disabled, sequencers of
2332 * all groups (group regular, group injected) can be configured
2333 * but their execution is disabled (limited to rank 1).
2334 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2335 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2336 * ADC conversion on only 1 channel.
2337 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2338 * @param ADCx ADC instance
2339 * @retval Returned value can be one of the following values:
2340 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2341 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2342 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2343 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2344 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2345 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2346 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2347 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2348 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2349 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2350 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2351 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2352 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2353 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2354 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2355 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2356 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)2357 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2358 {
2359 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2360 }
2361
2362 /**
2363 * @brief Set ADC group regular sequencer discontinuous mode:
2364 * sequence subdivided and scan conversions interrupted every selected
2365 * number of ranks.
2366 * @note It is not possible to enable both ADC group regular
2367 * continuous mode and sequencer discontinuous mode.
2368 * @note It is not possible to enable both ADC auto-injected mode
2369 * and ADC group regular sequencer discontinuous mode.
2370 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2371 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2372 * @param ADCx ADC instance
2373 * @param SeqDiscont This parameter can be one of the following values:
2374 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2375 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2376 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2377 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2378 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2379 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2380 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2381 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2382 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2383 * @retval None
2384 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2385 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2386 {
2387 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2388 }
2389
2390 /**
2391 * @brief Get ADC group regular sequencer discontinuous mode:
2392 * sequence subdivided and scan conversions interrupted every selected
2393 * number of ranks.
2394 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2395 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2396 * @param ADCx ADC instance
2397 * @retval Returned value can be one of the following values:
2398 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2399 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2400 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2401 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2402 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2403 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2404 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2405 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2406 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2407 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2408 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2409 {
2410 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2411 }
2412
2413 /**
2414 * @brief Set ADC group regular sequence: channel on the selected
2415 * scan sequence rank.
2416 * @note This function performs configuration of:
2417 * - Channels ordering into each rank of scan sequence:
2418 * whatever channel can be placed into whatever rank.
2419 * @note On this STM32 series, ADC group regular sequencer is
2420 * fully configurable: sequencer length and each rank
2421 * affectation to a channel are configurable.
2422 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2423 * @note Depending on devices and packages, some channels may not be available.
2424 * Refer to device datasheet for channels availability.
2425 * @note On this STM32 series, to measure internal channels (VrefInt,
2426 * TempSensor, ...), measurement paths to internal channels must be
2427 * enabled separately.
2428 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2429 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2430 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2431 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2432 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2433 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2434 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2435 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2436 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2437 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2438 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2439 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2440 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2441 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2442 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2443 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2444 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2445 * @param ADCx ADC instance
2446 * @param Rank This parameter can be one of the following values:
2447 * @arg @ref LL_ADC_REG_RANK_1
2448 * @arg @ref LL_ADC_REG_RANK_2
2449 * @arg @ref LL_ADC_REG_RANK_3
2450 * @arg @ref LL_ADC_REG_RANK_4
2451 * @arg @ref LL_ADC_REG_RANK_5
2452 * @arg @ref LL_ADC_REG_RANK_6
2453 * @arg @ref LL_ADC_REG_RANK_7
2454 * @arg @ref LL_ADC_REG_RANK_8
2455 * @arg @ref LL_ADC_REG_RANK_9
2456 * @arg @ref LL_ADC_REG_RANK_10
2457 * @arg @ref LL_ADC_REG_RANK_11
2458 * @arg @ref LL_ADC_REG_RANK_12
2459 * @arg @ref LL_ADC_REG_RANK_13
2460 * @arg @ref LL_ADC_REG_RANK_14
2461 * @arg @ref LL_ADC_REG_RANK_15
2462 * @arg @ref LL_ADC_REG_RANK_16
2463 * @param Channel This parameter can be one of the following values:
2464 * @arg @ref LL_ADC_CHANNEL_0
2465 * @arg @ref LL_ADC_CHANNEL_1
2466 * @arg @ref LL_ADC_CHANNEL_2
2467 * @arg @ref LL_ADC_CHANNEL_3
2468 * @arg @ref LL_ADC_CHANNEL_4
2469 * @arg @ref LL_ADC_CHANNEL_5
2470 * @arg @ref LL_ADC_CHANNEL_6
2471 * @arg @ref LL_ADC_CHANNEL_7
2472 * @arg @ref LL_ADC_CHANNEL_8
2473 * @arg @ref LL_ADC_CHANNEL_9
2474 * @arg @ref LL_ADC_CHANNEL_10
2475 * @arg @ref LL_ADC_CHANNEL_11
2476 * @arg @ref LL_ADC_CHANNEL_12
2477 * @arg @ref LL_ADC_CHANNEL_13
2478 * @arg @ref LL_ADC_CHANNEL_14
2479 * @arg @ref LL_ADC_CHANNEL_15
2480 * @arg @ref LL_ADC_CHANNEL_16
2481 * @arg @ref LL_ADC_CHANNEL_17
2482 * @arg @ref LL_ADC_CHANNEL_18
2483 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2484 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2485 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2486 *
2487 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2488 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2489 * @retval None
2490 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2491 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2492 {
2493 /* Set bits with content of parameter "Channel" with bits position */
2494 /* in register and register position depending on parameter "Rank". */
2495 /* Parameters "Rank" and "Channel" are used with masks because containing */
2496 /* other bits reserved for other purpose. */
2497 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2498
2499 MODIFY_REG(*preg,
2500 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2501 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2502 }
2503
2504 /**
2505 * @brief Get ADC group regular sequence: channel on the selected
2506 * scan sequence rank.
2507 * @note On this STM32 series, ADC group regular sequencer is
2508 * fully configurable: sequencer length and each rank
2509 * affectation to a channel are configurable.
2510 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2511 * @note Depending on devices and packages, some channels may not be available.
2512 * Refer to device datasheet for channels availability.
2513 * @note Usage of the returned channel number:
2514 * - To reinject this channel into another function LL_ADC_xxx:
2515 * the returned channel number is only partly formatted on definition
2516 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2517 * with parts of literals LL_ADC_CHANNEL_x or using
2518 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2519 * Then the selected literal LL_ADC_CHANNEL_x can be used
2520 * as parameter for another function.
2521 * - To get the channel number in decimal format:
2522 * process the returned value with the helper macro
2523 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2524 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2525 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2526 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2527 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2528 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2529 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2530 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2531 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2532 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2533 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2534 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2535 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2536 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2537 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2538 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2539 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2540 * @param ADCx ADC instance
2541 * @param Rank This parameter can be one of the following values:
2542 * @arg @ref LL_ADC_REG_RANK_1
2543 * @arg @ref LL_ADC_REG_RANK_2
2544 * @arg @ref LL_ADC_REG_RANK_3
2545 * @arg @ref LL_ADC_REG_RANK_4
2546 * @arg @ref LL_ADC_REG_RANK_5
2547 * @arg @ref LL_ADC_REG_RANK_6
2548 * @arg @ref LL_ADC_REG_RANK_7
2549 * @arg @ref LL_ADC_REG_RANK_8
2550 * @arg @ref LL_ADC_REG_RANK_9
2551 * @arg @ref LL_ADC_REG_RANK_10
2552 * @arg @ref LL_ADC_REG_RANK_11
2553 * @arg @ref LL_ADC_REG_RANK_12
2554 * @arg @ref LL_ADC_REG_RANK_13
2555 * @arg @ref LL_ADC_REG_RANK_14
2556 * @arg @ref LL_ADC_REG_RANK_15
2557 * @arg @ref LL_ADC_REG_RANK_16
2558 * @retval Returned value can be one of the following values:
2559 * @arg @ref LL_ADC_CHANNEL_0
2560 * @arg @ref LL_ADC_CHANNEL_1
2561 * @arg @ref LL_ADC_CHANNEL_2
2562 * @arg @ref LL_ADC_CHANNEL_3
2563 * @arg @ref LL_ADC_CHANNEL_4
2564 * @arg @ref LL_ADC_CHANNEL_5
2565 * @arg @ref LL_ADC_CHANNEL_6
2566 * @arg @ref LL_ADC_CHANNEL_7
2567 * @arg @ref LL_ADC_CHANNEL_8
2568 * @arg @ref LL_ADC_CHANNEL_9
2569 * @arg @ref LL_ADC_CHANNEL_10
2570 * @arg @ref LL_ADC_CHANNEL_11
2571 * @arg @ref LL_ADC_CHANNEL_12
2572 * @arg @ref LL_ADC_CHANNEL_13
2573 * @arg @ref LL_ADC_CHANNEL_14
2574 * @arg @ref LL_ADC_CHANNEL_15
2575 * @arg @ref LL_ADC_CHANNEL_16
2576 * @arg @ref LL_ADC_CHANNEL_17
2577 * @arg @ref LL_ADC_CHANNEL_18
2578 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2579 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2580 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2581 *
2582 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2583 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2584 * (1) For ADC channel read back from ADC register,
2585 * comparison with internal channel parameter to be done
2586 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2587 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)2588 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2589 {
2590 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2591
2592 return (uint32_t) (READ_BIT(*preg,
2593 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2594 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2595 );
2596 }
2597
2598 /**
2599 * @brief Set ADC continuous conversion mode on ADC group regular.
2600 * @note Description of ADC continuous conversion mode:
2601 * - single mode: one conversion per trigger
2602 * - continuous mode: after the first trigger, following
2603 * conversions launched successively automatically.
2604 * @note It is not possible to enable both ADC group regular
2605 * continuous mode and sequencer discontinuous mode.
2606 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2607 * @param ADCx ADC instance
2608 * @param Continuous This parameter can be one of the following values:
2609 * @arg @ref LL_ADC_REG_CONV_SINGLE
2610 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2611 * @retval None
2612 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)2613 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2614 {
2615 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2616 }
2617
2618 /**
2619 * @brief Get ADC continuous conversion mode on ADC group regular.
2620 * @note Description of ADC continuous conversion mode:
2621 * - single mode: one conversion per trigger
2622 * - continuous mode: after the first trigger, following
2623 * conversions launched successively automatically.
2624 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2625 * @param ADCx ADC instance
2626 * @retval Returned value can be one of the following values:
2627 * @arg @ref LL_ADC_REG_CONV_SINGLE
2628 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2629 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)2630 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2631 {
2632 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2633 }
2634
2635 /**
2636 * @brief Set ADC group regular conversion data transfer: no transfer or
2637 * transfer by DMA, and DMA requests mode.
2638 * @note If transfer by DMA selected, specifies the DMA requests
2639 * mode:
2640 * - Limited mode (One shot mode): DMA transfer requests are stopped
2641 * when number of DMA data transfers (number of
2642 * ADC conversions) is reached.
2643 * This ADC mode is intended to be used with DMA mode non-circular.
2644 * - Unlimited mode: DMA transfer requests are unlimited,
2645 * whatever number of DMA data transfers (number of
2646 * ADC conversions).
2647 * This ADC mode is intended to be used with DMA mode circular.
2648 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2649 * mode non-circular:
2650 * when DMA transfers size will be reached, DMA will stop transfers of
2651 * ADC conversions data ADC will raise an overrun error
2652 * (overrun flag and interruption if enabled).
2653 * @note For devices with several ADC instances: ADC multimode DMA
2654 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
2655 * @note To configure DMA source address (peripheral address),
2656 * use function @ref LL_ADC_DMA_GetRegAddr().
2657 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
2658 * CR2 DDS LL_ADC_REG_SetDMATransfer
2659 * @param ADCx ADC instance
2660 * @param DMATransfer This parameter can be one of the following values:
2661 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2662 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2663 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2664 * @retval None
2665 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)2666 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2667 {
2668 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2669 }
2670
2671 /**
2672 * @brief Get ADC group regular conversion data transfer: no transfer or
2673 * transfer by DMA, and DMA requests mode.
2674 * @note If transfer by DMA selected, specifies the DMA requests
2675 * mode:
2676 * - Limited mode (One shot mode): DMA transfer requests are stopped
2677 * when number of DMA data transfers (number of
2678 * ADC conversions) is reached.
2679 * This ADC mode is intended to be used with DMA mode non-circular.
2680 * - Unlimited mode: DMA transfer requests are unlimited,
2681 * whatever number of DMA data transfers (number of
2682 * ADC conversions).
2683 * This ADC mode is intended to be used with DMA mode circular.
2684 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2685 * mode non-circular:
2686 * when DMA transfers size will be reached, DMA will stop transfers of
2687 * ADC conversions data ADC will raise an overrun error
2688 * (overrun flag and interruption if enabled).
2689 * @note For devices with several ADC instances: ADC multimode DMA
2690 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
2691 * @note To configure DMA source address (peripheral address),
2692 * use function @ref LL_ADC_DMA_GetRegAddr().
2693 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
2694 * CR2 DDS LL_ADC_REG_GetDMATransfer
2695 * @param ADCx ADC instance
2696 * @retval Returned value can be one of the following values:
2697 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2698 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2699 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2700 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)2701 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2702 {
2703 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2704 }
2705
2706 /**
2707 * @brief Specify which ADC flag between EOC (end of unitary conversion)
2708 * or EOS (end of sequence conversions) is used to indicate
2709 * the end of conversion.
2710 * @note This feature is aimed to be set when using ADC with
2711 * programming model by polling or interruption
2712 * (programming model by DMA usually uses DMA interruptions
2713 * to indicate end of conversion and data transfer).
2714 * @note For ADC group injected, end of conversion (flag&IT) is raised
2715 * only at the end of the sequence.
2716 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
2717 * @param ADCx ADC instance
2718 * @param EocSelection This parameter can be one of the following values:
2719 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2720 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2721 * @retval None
2722 */
LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef * ADCx,uint32_t EocSelection)2723 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2724 {
2725 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2726 }
2727
2728 /**
2729 * @brief Get which ADC flag between EOC (end of unitary conversion)
2730 * or EOS (end of sequence conversions) is used to indicate
2731 * the end of conversion.
2732 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
2733 * @param ADCx ADC instance
2734 * @retval Returned value can be one of the following values:
2735 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2736 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2737 */
LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef * ADCx)2738 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
2739 {
2740 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2741 }
2742
2743 /**
2744 * @}
2745 */
2746
2747 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2748 * @{
2749 */
2750
2751 /**
2752 * @brief Set ADC group injected conversion trigger source:
2753 * internal (SW start) or from external IP (timer event,
2754 * external interrupt line).
2755 * @note On this STM32 series, setting of external trigger edge is performed
2756 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
2757 * @note Availability of parameters of trigger sources from timer
2758 * depends on timers availability on the selected device.
2759 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
2760 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
2761 * @param ADCx ADC instance
2762 * @param TriggerSource This parameter can be one of the following values:
2763 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2764 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2765 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2766 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2767 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2768 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2769 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2770 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2771 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2772 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2773 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2774 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2775 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2776 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2777 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2778 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2779 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2780 * @retval None
2781 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2782 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2783 {
2784 /* Note: On this STM32 series, ADC group injected external trigger edge */
2785 /* is used to perform a ADC conversion start. */
2786 /* This function does not set external trigger edge. */
2787 /* This feature is set using function */
2788 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2789 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2790 }
2791
2792 /**
2793 * @brief Get ADC group injected conversion trigger source:
2794 * internal (SW start) or from external IP (timer event,
2795 * external interrupt line).
2796 * @note To determine whether group injected trigger source is
2797 * internal (SW start) or external, without detail
2798 * of which peripheral is selected as external trigger,
2799 * (equivalent to
2800 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2801 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2802 * @note Availability of parameters of trigger sources from timer
2803 * depends on timers availability on the selected device.
2804 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
2805 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
2806 * @param ADCx ADC instance
2807 * @retval Returned value can be one of the following values:
2808 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2809 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2810 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2811 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2812 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2813 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2814 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2815 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2816 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2817 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2818 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2819 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2820 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2821 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2822 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2823 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2824 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2825 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)2826 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
2827 {
2828 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2829
2830 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2831 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2832 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2833
2834 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2835 /* to match with triggers literals definition. */
2836 return ((TriggerSource
2837 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2838 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2839 );
2840 }
2841
2842 /**
2843 * @brief Get ADC group injected conversion trigger source internal (SW start)
2844 or external
2845 * @note In case of group injected trigger source set to external trigger,
2846 * to determine which peripheral is selected as external trigger,
2847 * use function @ref LL_ADC_INJ_GetTriggerSource.
2848 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
2849 * @param ADCx ADC instance
2850 * @retval Value "0" if trigger source external trigger
2851 * Value "1" if trigger source SW start.
2852 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2853 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2854 {
2855 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2856 }
2857
2858 /**
2859 * @brief Get ADC group injected conversion trigger polarity.
2860 * Applicable only for trigger source set to external trigger.
2861 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
2862 * @param ADCx ADC instance
2863 * @retval Returned value can be one of the following values:
2864 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
2865 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
2866 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
2867 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)2868 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
2869 {
2870 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2871 }
2872
2873 /**
2874 * @brief Set ADC group injected sequencer length and scan direction.
2875 * @note This function performs configuration of:
2876 * - Sequence length: Number of ranks in the scan sequence.
2877 * - Sequence direction: Unless specified in parameters, sequencer
2878 * scan direction is forward (from rank 1 to rank n).
2879 * @note On this STM32 series, group injected sequencer configuration
2880 * is conditioned to ADC instance sequencer mode.
2881 * If ADC instance sequencer mode is disabled, sequencers of
2882 * all groups (group regular, group injected) can be configured
2883 * but their execution is disabled (limited to rank 1).
2884 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2885 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2886 * ADC conversion on only 1 channel.
2887 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2888 * @param ADCx ADC instance
2889 * @param SequencerNbRanks This parameter can be one of the following values:
2890 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2891 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2892 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2893 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2894 * @retval None
2895 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2896 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2897 {
2898 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2899 }
2900
2901 /**
2902 * @brief Get ADC group injected sequencer length and scan direction.
2903 * @note This function retrieves:
2904 * - Sequence length: Number of ranks in the scan sequence.
2905 * - Sequence direction: Unless specified in parameters, sequencer
2906 * scan direction is forward (from rank 1 to rank n).
2907 * @note On this STM32 series, group injected sequencer configuration
2908 * is conditioned to ADC instance sequencer mode.
2909 * If ADC instance sequencer mode is disabled, sequencers of
2910 * all groups (group regular, group injected) can be configured
2911 * but their execution is disabled (limited to rank 1).
2912 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2913 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2914 * ADC conversion on only 1 channel.
2915 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2916 * @param ADCx ADC instance
2917 * @retval Returned value can be one of the following values:
2918 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2919 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2920 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2921 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2922 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)2923 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
2924 {
2925 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2926 }
2927
2928 /**
2929 * @brief Set ADC group injected sequencer discontinuous mode:
2930 * sequence subdivided and scan conversions interrupted every selected
2931 * number of ranks.
2932 * @note It is not possible to enable both ADC group injected
2933 * auto-injected mode and sequencer discontinuous mode.
2934 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2935 * @param ADCx ADC instance
2936 * @param SeqDiscont This parameter can be one of the following values:
2937 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2938 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2939 * @retval None
2940 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2941 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2942 {
2943 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2944 }
2945
2946 /**
2947 * @brief Get ADC group injected sequencer discontinuous mode:
2948 * sequence subdivided and scan conversions interrupted every selected
2949 * number of ranks.
2950 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2951 * @param ADCx ADC instance
2952 * @retval Returned value can be one of the following values:
2953 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2954 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2955 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)2956 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
2957 {
2958 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2959 }
2960
2961 /**
2962 * @brief Set ADC group injected sequence: channel on the selected
2963 * sequence rank.
2964 * @note Depending on devices and packages, some channels may not be available.
2965 * Refer to device datasheet for channels availability.
2966 * @note On this STM32 series, to measure internal channels (VrefInt,
2967 * TempSensor, ...), measurement paths to internal channels must be
2968 * enabled separately.
2969 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2970 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2971 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2972 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2973 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2974 * @param ADCx ADC instance
2975 * @param Rank This parameter can be one of the following values:
2976 * @arg @ref LL_ADC_INJ_RANK_1
2977 * @arg @ref LL_ADC_INJ_RANK_2
2978 * @arg @ref LL_ADC_INJ_RANK_3
2979 * @arg @ref LL_ADC_INJ_RANK_4
2980 * @param Channel This parameter can be one of the following values:
2981 * @arg @ref LL_ADC_CHANNEL_0
2982 * @arg @ref LL_ADC_CHANNEL_1
2983 * @arg @ref LL_ADC_CHANNEL_2
2984 * @arg @ref LL_ADC_CHANNEL_3
2985 * @arg @ref LL_ADC_CHANNEL_4
2986 * @arg @ref LL_ADC_CHANNEL_5
2987 * @arg @ref LL_ADC_CHANNEL_6
2988 * @arg @ref LL_ADC_CHANNEL_7
2989 * @arg @ref LL_ADC_CHANNEL_8
2990 * @arg @ref LL_ADC_CHANNEL_9
2991 * @arg @ref LL_ADC_CHANNEL_10
2992 * @arg @ref LL_ADC_CHANNEL_11
2993 * @arg @ref LL_ADC_CHANNEL_12
2994 * @arg @ref LL_ADC_CHANNEL_13
2995 * @arg @ref LL_ADC_CHANNEL_14
2996 * @arg @ref LL_ADC_CHANNEL_15
2997 * @arg @ref LL_ADC_CHANNEL_16
2998 * @arg @ref LL_ADC_CHANNEL_17
2999 * @arg @ref LL_ADC_CHANNEL_18
3000 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3001 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3002 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3003 *
3004 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3005 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3006 * @retval None
3007 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3008 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3009 {
3010 /* Set bits with content of parameter "Channel" with bits position */
3011 /* in register depending on parameter "Rank". */
3012 /* Parameters "Rank" and "Channel" are used with masks because containing */
3013 /* other bits reserved for other purpose. */
3014 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
3015
3016 MODIFY_REG(ADCx->JSQR,
3017 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))),
3018 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))));
3019 }
3020
3021 /**
3022 * @brief Get ADC group injected sequence: channel on the selected
3023 * sequence rank.
3024 * @note Depending on devices and packages, some channels may not be available.
3025 * Refer to device datasheet for channels availability.
3026 * @note Usage of the returned channel number:
3027 * - To reinject this channel into another function LL_ADC_xxx:
3028 * the returned channel number is only partly formatted on definition
3029 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3030 * with parts of literals LL_ADC_CHANNEL_x or using
3031 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3032 * Then the selected literal LL_ADC_CHANNEL_x can be used
3033 * as parameter for another function.
3034 * - To get the channel number in decimal format:
3035 * process the returned value with the helper macro
3036 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3037 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
3038 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
3039 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
3040 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
3041 * @param ADCx ADC instance
3042 * @param Rank This parameter can be one of the following values:
3043 * @arg @ref LL_ADC_INJ_RANK_1
3044 * @arg @ref LL_ADC_INJ_RANK_2
3045 * @arg @ref LL_ADC_INJ_RANK_3
3046 * @arg @ref LL_ADC_INJ_RANK_4
3047 * @retval Returned value can be one of the following values:
3048 * @arg @ref LL_ADC_CHANNEL_0
3049 * @arg @ref LL_ADC_CHANNEL_1
3050 * @arg @ref LL_ADC_CHANNEL_2
3051 * @arg @ref LL_ADC_CHANNEL_3
3052 * @arg @ref LL_ADC_CHANNEL_4
3053 * @arg @ref LL_ADC_CHANNEL_5
3054 * @arg @ref LL_ADC_CHANNEL_6
3055 * @arg @ref LL_ADC_CHANNEL_7
3056 * @arg @ref LL_ADC_CHANNEL_8
3057 * @arg @ref LL_ADC_CHANNEL_9
3058 * @arg @ref LL_ADC_CHANNEL_10
3059 * @arg @ref LL_ADC_CHANNEL_11
3060 * @arg @ref LL_ADC_CHANNEL_12
3061 * @arg @ref LL_ADC_CHANNEL_13
3062 * @arg @ref LL_ADC_CHANNEL_14
3063 * @arg @ref LL_ADC_CHANNEL_15
3064 * @arg @ref LL_ADC_CHANNEL_16
3065 * @arg @ref LL_ADC_CHANNEL_17
3066 * @arg @ref LL_ADC_CHANNEL_18
3067 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3068 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3069 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3070 *
3071 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3072 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
3073 * (1) For ADC channel read back from ADC register,
3074 * comparison with internal channel parameter to be done
3075 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3076 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3077 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3078 {
3079 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
3080
3081 return (uint32_t)(READ_BIT(ADCx->JSQR,
3082 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))))
3083 >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))
3084 );
3085 }
3086
3087 /**
3088 * @brief Set ADC group injected conversion trigger:
3089 * independent or from ADC group regular.
3090 * @note This mode can be used to extend number of data registers
3091 * updated after one ADC conversion trigger and with data
3092 * permanently kept (not erased by successive conversions of scan of
3093 * ADC sequencer ranks), up to 5 data registers:
3094 * 1 data register on ADC group regular, 4 data registers
3095 * on ADC group injected.
3096 * @note If ADC group injected injected trigger source is set to an
3097 * external trigger, this feature must be must be set to
3098 * independent trigger.
3099 * ADC group injected automatic trigger is compliant only with
3100 * group injected trigger source set to SW start, without any
3101 * further action on ADC group injected conversion start or stop:
3102 * in this case, ADC group injected is controlled only
3103 * from ADC group regular.
3104 * @note It is not possible to enable both ADC group injected
3105 * auto-injected mode and sequencer discontinuous mode.
3106 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
3107 * @param ADCx ADC instance
3108 * @param TrigAuto This parameter can be one of the following values:
3109 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3110 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3111 * @retval None
3112 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)3113 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3114 {
3115 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3116 }
3117
3118 /**
3119 * @brief Get ADC group injected conversion trigger:
3120 * independent or from ADC group regular.
3121 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
3122 * @param ADCx ADC instance
3123 * @retval Returned value can be one of the following values:
3124 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3125 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3126 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)3127 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
3128 {
3129 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3130 }
3131
3132 /**
3133 * @brief Set ADC group injected offset.
3134 * @note It sets:
3135 * - ADC group injected rank to which the offset programmed
3136 * will be applied
3137 * - Offset level (offset to be subtracted from the raw
3138 * converted data).
3139 * Caution: Offset format is dependent to ADC resolution:
3140 * offset has to be left-aligned on bit 11, the LSB (right bits)
3141 * are set to 0.
3142 * @note Offset cannot be enabled or disabled.
3143 * To emulate offset disabled, set an offset value equal to 0.
3144 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
3145 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
3146 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
3147 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
3148 * @param ADCx ADC instance
3149 * @param Rank This parameter can be one of the following values:
3150 * @arg @ref LL_ADC_INJ_RANK_1
3151 * @arg @ref LL_ADC_INJ_RANK_2
3152 * @arg @ref LL_ADC_INJ_RANK_3
3153 * @arg @ref LL_ADC_INJ_RANK_4
3154 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3155 * @retval None
3156 */
LL_ADC_INJ_SetOffset(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t OffsetLevel)3157 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3158 {
3159 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3160
3161 MODIFY_REG(*preg,
3162 ADC_JOFR1_JOFFSET1,
3163 OffsetLevel);
3164 }
3165
3166 /**
3167 * @brief Get ADC group injected offset.
3168 * @note It gives offset level (offset to be subtracted from the raw converted data).
3169 * Caution: Offset format is dependent to ADC resolution:
3170 * offset has to be left-aligned on bit 11, the LSB (right bits)
3171 * are set to 0.
3172 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3173 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3174 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3175 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3176 * @param ADCx ADC instance
3177 * @param Rank This parameter can be one of the following values:
3178 * @arg @ref LL_ADC_INJ_RANK_1
3179 * @arg @ref LL_ADC_INJ_RANK_2
3180 * @arg @ref LL_ADC_INJ_RANK_3
3181 * @arg @ref LL_ADC_INJ_RANK_4
3182 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3183 */
LL_ADC_INJ_GetOffset(ADC_TypeDef * ADCx,uint32_t Rank)3184 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
3185 {
3186 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3187
3188 return (uint32_t)(READ_BIT(*preg,
3189 ADC_JOFR1_JOFFSET1)
3190 );
3191 }
3192
3193 /**
3194 * @}
3195 */
3196
3197 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3198 * @{
3199 */
3200
3201 /**
3202 * @brief Set sampling time of the selected ADC channel
3203 * Unit: ADC clock cycles.
3204 * @note On this device, sampling time is on channel scope: independently
3205 * of channel mapped on ADC group regular or injected.
3206 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3207 * converted:
3208 * sampling time constraints must be respected (sampling time can be
3209 * adjusted in function of ADC clock frequency and sampling time
3210 * setting).
3211 * Refer to device datasheet for timings values (parameters TS_vrefint,
3212 * TS_temp, ...).
3213 * @note Conversion time is the addition of sampling time and processing time.
3214 * Refer to reference manual for ADC processing time of
3215 * this STM32 series.
3216 * @note In case of ADC conversion of internal channel (VrefInt,
3217 * temperature sensor, ...), a sampling time minimum value
3218 * is required.
3219 * Refer to device datasheet.
3220 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
3221 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
3222 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
3223 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
3224 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
3225 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
3226 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
3227 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
3228 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
3229 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
3230 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
3231 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
3232 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
3233 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
3234 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
3235 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
3236 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
3237 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
3238 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
3239 * @param ADCx ADC instance
3240 * @param Channel This parameter can be one of the following values:
3241 * @arg @ref LL_ADC_CHANNEL_0
3242 * @arg @ref LL_ADC_CHANNEL_1
3243 * @arg @ref LL_ADC_CHANNEL_2
3244 * @arg @ref LL_ADC_CHANNEL_3
3245 * @arg @ref LL_ADC_CHANNEL_4
3246 * @arg @ref LL_ADC_CHANNEL_5
3247 * @arg @ref LL_ADC_CHANNEL_6
3248 * @arg @ref LL_ADC_CHANNEL_7
3249 * @arg @ref LL_ADC_CHANNEL_8
3250 * @arg @ref LL_ADC_CHANNEL_9
3251 * @arg @ref LL_ADC_CHANNEL_10
3252 * @arg @ref LL_ADC_CHANNEL_11
3253 * @arg @ref LL_ADC_CHANNEL_12
3254 * @arg @ref LL_ADC_CHANNEL_13
3255 * @arg @ref LL_ADC_CHANNEL_14
3256 * @arg @ref LL_ADC_CHANNEL_15
3257 * @arg @ref LL_ADC_CHANNEL_16
3258 * @arg @ref LL_ADC_CHANNEL_17
3259 * @arg @ref LL_ADC_CHANNEL_18
3260 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3261 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3262 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3263 *
3264 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3265 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3266 * @param SamplingTime This parameter can be one of the following values:
3267 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3268 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3269 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3270 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3271 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3272 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3273 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3274 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3275 * @retval None
3276 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)3277 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3278 {
3279 /* Set bits with content of parameter "SamplingTime" with bits position */
3280 /* in register and register position depending on parameter "Channel". */
3281 /* Parameter "Channel" is used with masks because containing */
3282 /* other bits reserved for other purpose. */
3283 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3284
3285 MODIFY_REG(*preg,
3286 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3287 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3288 }
3289
3290 /**
3291 * @brief Get sampling time of the selected ADC channel
3292 * Unit: ADC clock cycles.
3293 * @note On this device, sampling time is on channel scope: independently
3294 * of channel mapped on ADC group regular or injected.
3295 * @note Conversion time is the addition of sampling time and processing time.
3296 * Refer to reference manual for ADC processing time of
3297 * this STM32 series.
3298 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
3299 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
3300 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
3301 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
3302 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
3303 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
3304 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
3305 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
3306 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
3307 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
3308 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
3309 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
3310 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
3311 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
3312 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
3313 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
3314 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
3315 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
3316 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
3317 * @param ADCx ADC instance
3318 * @param Channel This parameter can be one of the following values:
3319 * @arg @ref LL_ADC_CHANNEL_0
3320 * @arg @ref LL_ADC_CHANNEL_1
3321 * @arg @ref LL_ADC_CHANNEL_2
3322 * @arg @ref LL_ADC_CHANNEL_3
3323 * @arg @ref LL_ADC_CHANNEL_4
3324 * @arg @ref LL_ADC_CHANNEL_5
3325 * @arg @ref LL_ADC_CHANNEL_6
3326 * @arg @ref LL_ADC_CHANNEL_7
3327 * @arg @ref LL_ADC_CHANNEL_8
3328 * @arg @ref LL_ADC_CHANNEL_9
3329 * @arg @ref LL_ADC_CHANNEL_10
3330 * @arg @ref LL_ADC_CHANNEL_11
3331 * @arg @ref LL_ADC_CHANNEL_12
3332 * @arg @ref LL_ADC_CHANNEL_13
3333 * @arg @ref LL_ADC_CHANNEL_14
3334 * @arg @ref LL_ADC_CHANNEL_15
3335 * @arg @ref LL_ADC_CHANNEL_16
3336 * @arg @ref LL_ADC_CHANNEL_17
3337 * @arg @ref LL_ADC_CHANNEL_18
3338 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3339 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3340 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3341 *
3342 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3343 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3344 * @retval Returned value can be one of the following values:
3345 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3346 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3347 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3348 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3349 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3350 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3351 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3352 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3353 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)3354 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3355 {
3356 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3357
3358 return (uint32_t)(READ_BIT(*preg,
3359 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3360 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3361 );
3362 }
3363
3364 /**
3365 * @}
3366 */
3367
3368 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3369 * @{
3370 */
3371
3372 /**
3373 * @brief Set ADC analog watchdog monitored channels:
3374 * a single channel or all channels,
3375 * on ADC groups regular and-or injected.
3376 * @note Once monitored channels are selected, analog watchdog
3377 * is enabled.
3378 * @note In case of need to define a single channel to monitor
3379 * with analog watchdog from sequencer channel definition,
3380 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3381 * @note On this STM32 series, there is only 1 kind of analog watchdog
3382 * instance:
3383 * - AWD standard (instance AWD1):
3384 * - channels monitored: can monitor 1 channel or all channels.
3385 * - groups monitored: ADC groups regular and-or injected.
3386 * - resolution: resolution is not limited (corresponds to
3387 * ADC resolution configured).
3388 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3389 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3390 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
3391 * @param ADCx ADC instance
3392 * @param AWDChannelGroup This parameter can be one of the following values:
3393 * @arg @ref LL_ADC_AWD_DISABLE
3394 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3395 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3396 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3397 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3398 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3399 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3400 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3401 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3402 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3403 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3404 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3405 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3406 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3407 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3408 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3409 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3410 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3411 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3412 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3413 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3414 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3415 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3416 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3417 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3418 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3419 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3420 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3421 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3422 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3423 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3424 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3425 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3426 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3427 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3428 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3429 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3430 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3431 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3432 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3433 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3434 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3435 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3436 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3437 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3438 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3439 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3440 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3441 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3442 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3443 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3444 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3445 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3446 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3447 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3448 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3449 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3450 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3451 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3452 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3453 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3454 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3455 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3456 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
3458 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
3459 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
3460 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
3461 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
3462 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
3463 *
3464 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3465 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3466 * @retval None
3467 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)3468 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3469 {
3470 MODIFY_REG(ADCx->CR1,
3471 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3472 AWDChannelGroup);
3473 }
3474
3475 /**
3476 * @brief Get ADC analog watchdog monitored channel.
3477 * @note Usage of the returned channel number:
3478 * - To reinject this channel into another function LL_ADC_xxx:
3479 * the returned channel number is only partly formatted on definition
3480 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3481 * with parts of literals LL_ADC_CHANNEL_x or using
3482 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3483 * Then the selected literal LL_ADC_CHANNEL_x can be used
3484 * as parameter for another function.
3485 * - To get the channel number in decimal format:
3486 * process the returned value with the helper macro
3487 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3488 * Applicable only when the analog watchdog is set to monitor
3489 * one channel.
3490 * @note On this STM32 series, there is only 1 kind of analog watchdog
3491 * instance:
3492 * - AWD standard (instance AWD1):
3493 * - channels monitored: can monitor 1 channel or all channels.
3494 * - groups monitored: ADC groups regular and-or injected.
3495 * - resolution: resolution is not limited (corresponds to
3496 * ADC resolution configured).
3497 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3498 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3499 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3500 * @param ADCx ADC instance
3501 * @retval Returned value can be one of the following values:
3502 * @arg @ref LL_ADC_AWD_DISABLE
3503 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3504 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3505 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3506 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3507 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3508 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3509 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3510 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3511 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3512 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3513 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3514 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3515 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3516 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3517 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3518 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3519 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3520 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3521 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3522 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3523 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3524 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3525 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3526 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3527 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3528 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3529 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3530 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3531 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3532 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3533 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3534 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3535 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3536 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3537 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3538 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3539 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3540 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3541 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3542 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3543 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3544 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3545 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3546 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3547 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3548 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3549 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3550 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3551 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3552 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3553 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3554 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3555 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3556 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3557 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3558 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3559 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3560 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3561 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3562 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3563 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx)3564 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3565 {
3566 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3567 }
3568
3569 /**
3570 * @brief Set ADC analog watchdog threshold value of threshold
3571 * high or low.
3572 * @note In case of ADC resolution different of 12 bits,
3573 * analog watchdog thresholds data require a specific shift.
3574 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3575 * @note On this STM32 series, there is only 1 kind of analog watchdog
3576 * instance:
3577 * - AWD standard (instance AWD1):
3578 * - channels monitored: can monitor 1 channel or all channels.
3579 * - groups monitored: ADC groups regular and-or injected.
3580 * - resolution: resolution is not limited (corresponds to
3581 * ADC resolution configured).
3582 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3583 * LTR LT LL_ADC_SetAnalogWDThresholds
3584 * @param ADCx ADC instance
3585 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3586 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3587 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3588 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3589 * @retval None
3590 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3591 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3592 {
3593 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3594
3595 MODIFY_REG(*preg,
3596 ADC_HTR_HT,
3597 AWDThresholdValue);
3598 }
3599
3600 /**
3601 * @brief Get ADC analog watchdog threshold value of threshold high or
3602 * threshold low.
3603 * @note In case of ADC resolution different of 12 bits,
3604 * analog watchdog thresholds data require a specific shift.
3605 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3606 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3607 * LTR LT LL_ADC_GetAnalogWDThresholds
3608 * @param ADCx ADC instance
3609 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3610 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3611 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3612 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3613 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)3614 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3615 {
3616 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3617
3618 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3619 }
3620
3621 /**
3622 * @}
3623 */
3624
3625 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3626 * @{
3627 */
3628
3629 #if defined(ADC_MULTIMODE_SUPPORT)
3630 /**
3631 * @brief Set ADC multimode configuration to operate in independent mode
3632 * or multimode (for devices with several ADC instances).
3633 * @note If multimode configuration: the selected ADC instance is
3634 * either master or slave depending on hardware.
3635 * Refer to reference manual.
3636 * @rmtoll CCR MULTI LL_ADC_SetMultimode
3637 * @param ADCxy_COMMON ADC common instance
3638 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3639 * @param Multimode This parameter can be one of the following values:
3640 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3641 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3642 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3643 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3644 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3645 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3646 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3647 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3648 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3649 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3650 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3651 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3652 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3653 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3654 * @retval None
3655 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)3656 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3657 {
3658 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3659 }
3660
3661 /**
3662 * @brief Get ADC multimode configuration to operate in independent mode
3663 * or multimode (for devices with several ADC instances).
3664 * @note If multimode configuration: the selected ADC instance is
3665 * either master or slave depending on hardware.
3666 * Refer to reference manual.
3667 * @rmtoll CCR MULTI LL_ADC_GetMultimode
3668 * @param ADCxy_COMMON ADC common instance
3669 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3670 * @retval Returned value can be one of the following values:
3671 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3672 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3673 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3674 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3675 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3676 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3677 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3678 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3679 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3680 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3681 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3682 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3683 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3684 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3685 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)3686 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
3687 {
3688 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3689 }
3690
3691 /**
3692 * @brief Set ADC multimode conversion data transfer: no transfer
3693 * or transfer by DMA.
3694 * @note If ADC multimode transfer by DMA is not selected:
3695 * each ADC uses its own DMA channel, with its individual
3696 * DMA transfer settings.
3697 * If ADC multimode transfer by DMA is selected:
3698 * One DMA channel is used for both ADC (DMA of ADC master)
3699 * Specifies the DMA requests mode:
3700 * - Limited mode (One shot mode): DMA transfer requests are stopped
3701 * when number of DMA data transfers (number of
3702 * ADC conversions) is reached.
3703 * This ADC mode is intended to be used with DMA mode non-circular.
3704 * - Unlimited mode: DMA transfer requests are unlimited,
3705 * whatever number of DMA data transfers (number of
3706 * ADC conversions).
3707 * This ADC mode is intended to be used with DMA mode circular.
3708 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3709 * mode non-circular:
3710 * when DMA transfers size will be reached, DMA will stop transfers of
3711 * ADC conversions data ADC will raise an overrun error
3712 * (overrun flag and interruption if enabled).
3713 * @note How to retrieve multimode conversion data:
3714 * Whatever multimode transfer by DMA setting: using function
3715 * @ref LL_ADC_REG_ReadMultiConversionData32().
3716 * If ADC multimode transfer by DMA is selected: conversion data
3717 * is a raw data with ADC master and slave concatenated.
3718 * A macro is available to get the conversion data of
3719 * ADC master or ADC slave: see helper macro
3720 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3721 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
3722 * CCR DDS LL_ADC_SetMultiDMATransfer
3723 * @param ADCxy_COMMON ADC common instance
3724 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3725 * @param MultiDMATransfer This parameter can be one of the following values:
3726 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3727 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3728 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3729 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3730 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3731 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3732 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3733 * @retval None
3734 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)3735 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3736 {
3737 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3738 }
3739
3740 /**
3741 * @brief Get ADC multimode conversion data transfer: no transfer
3742 * or transfer by DMA.
3743 * @note If ADC multimode transfer by DMA is not selected:
3744 * each ADC uses its own DMA channel, with its individual
3745 * DMA transfer settings.
3746 * If ADC multimode transfer by DMA is selected:
3747 * One DMA channel is used for both ADC (DMA of ADC master)
3748 * Specifies the DMA requests mode:
3749 * - Limited mode (One shot mode): DMA transfer requests are stopped
3750 * when number of DMA data transfers (number of
3751 * ADC conversions) is reached.
3752 * This ADC mode is intended to be used with DMA mode non-circular.
3753 * - Unlimited mode: DMA transfer requests are unlimited,
3754 * whatever number of DMA data transfers (number of
3755 * ADC conversions).
3756 * This ADC mode is intended to be used with DMA mode circular.
3757 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3758 * mode non-circular:
3759 * when DMA transfers size will be reached, DMA will stop transfers of
3760 * ADC conversions data ADC will raise an overrun error
3761 * (overrun flag and interruption if enabled).
3762 * @note How to retrieve multimode conversion data:
3763 * Whatever multimode transfer by DMA setting: using function
3764 * @ref LL_ADC_REG_ReadMultiConversionData32().
3765 * If ADC multimode transfer by DMA is selected: conversion data
3766 * is a raw data with ADC master and slave concatenated.
3767 * A macro is available to get the conversion data of
3768 * ADC master or ADC slave: see helper macro
3769 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3770 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
3771 * CCR DDS LL_ADC_GetMultiDMATransfer
3772 * @param ADCxy_COMMON ADC common instance
3773 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3774 * @retval Returned value can be one of the following values:
3775 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3776 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3777 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3778 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3779 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3780 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3781 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3782 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)3783 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
3784 {
3785 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3786 }
3787
3788 /**
3789 * @brief Set ADC multimode delay between 2 sampling phases.
3790 * @note The sampling delay range depends on ADC resolution:
3791 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
3792 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
3793 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
3794 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
3795 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
3796 * @param ADCxy_COMMON ADC common instance
3797 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3798 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
3799 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3800 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3801 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3802 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3803 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3804 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3805 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3806 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3807 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3808 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3809 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3810 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3811 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3812 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3813 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3814 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3815 * @retval None
3816 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)3817 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3818 {
3819 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3820 }
3821
3822 /**
3823 * @brief Get ADC multimode delay between 2 sampling phases.
3824 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
3825 * @param ADCxy_COMMON ADC common instance
3826 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3827 * @retval Returned value can be one of the following values:
3828 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3829 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3830 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3831 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3832 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3833 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3834 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3835 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3836 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3837 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3838 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3839 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3840 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3841 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3842 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3843 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3844 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)3845 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
3846 {
3847 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3848 }
3849 #endif /* ADC_MULTIMODE_SUPPORT */
3850
3851 /**
3852 * @}
3853 */
3854 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3855 * @{
3856 */
3857
3858 /**
3859 * @brief Enable the selected ADC instance.
3860 * @note On this STM32 series, after ADC enable, a delay for
3861 * ADC internal analog stabilization is required before performing a
3862 * ADC conversion start.
3863 * Refer to device datasheet, parameter tSTAB.
3864 * @rmtoll CR2 ADON LL_ADC_Enable
3865 * @param ADCx ADC instance
3866 * @retval None
3867 */
LL_ADC_Enable(ADC_TypeDef * ADCx)3868 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3869 {
3870 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3871 }
3872
3873 /**
3874 * @brief Disable the selected ADC instance.
3875 * @rmtoll CR2 ADON LL_ADC_Disable
3876 * @param ADCx ADC instance
3877 * @retval None
3878 */
LL_ADC_Disable(ADC_TypeDef * ADCx)3879 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3880 {
3881 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3882 }
3883
3884 /**
3885 * @brief Get the selected ADC instance enable state.
3886 * @rmtoll CR2 ADON LL_ADC_IsEnabled
3887 * @param ADCx ADC instance
3888 * @retval 0: ADC is disabled, 1: ADC is enabled.
3889 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)3890 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3891 {
3892 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3893 }
3894
3895 /**
3896 * @}
3897 */
3898
3899 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3900 * @{
3901 */
3902
3903 /**
3904 * @brief Start ADC group regular conversion.
3905 * @note On this STM32 series, this function is relevant only for
3906 * internal trigger (SW start), not for external trigger:
3907 * - If ADC trigger has been set to software start, ADC conversion
3908 * starts immediately.
3909 * - If ADC trigger has been set to external trigger, ADC conversion
3910 * start must be performed using function
3911 * @ref LL_ADC_REG_StartConversionExtTrig().
3912 * (if external trigger edge would have been set during ADC other
3913 * settings, ADC conversion would start at trigger event
3914 * as soon as ADC is enabled).
3915 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3916 * @param ADCx ADC instance
3917 * @retval None
3918 */
LL_ADC_REG_StartConversionSWStart(ADC_TypeDef * ADCx)3919 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3920 {
3921 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3922 }
3923
3924 /**
3925 * @brief Start ADC group regular conversion from external trigger.
3926 * @note ADC conversion will start at next trigger event (on the selected
3927 * trigger edge) following the ADC start conversion command.
3928 * @note On this STM32 series, this function is relevant for
3929 * ADC conversion start from external trigger.
3930 * If internal trigger (SW start) is needed, perform ADC conversion
3931 * start using function @ref LL_ADC_REG_StartConversionSWStart().
3932 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3933 * @param ExternalTriggerEdge This parameter can be one of the following values:
3934 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3935 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3936 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3937 * @param ADCx ADC instance
3938 * @retval None
3939 */
LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3940 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3941 {
3942 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3943 }
3944
3945 /**
3946 * @brief Stop ADC group regular conversion from external trigger.
3947 * @note No more ADC conversion will start at next trigger event
3948 * following the ADC stop conversion command.
3949 * If a conversion is on-going, it will be completed.
3950 * @note On this STM32 series, there is no specific command
3951 * to stop a conversion on-going or to stop ADC converting
3952 * in continuous mode. These actions can be performed
3953 * using function @ref LL_ADC_Disable().
3954 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
3955 * @param ADCx ADC instance
3956 * @retval None
3957 */
LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef * ADCx)3958 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3959 {
3960 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3961 }
3962
3963 /**
3964 * @brief Get ADC group regular conversion data, range fit for
3965 * all ADC configurations: all ADC resolutions and
3966 * all oversampling increased data width (for devices
3967 * with feature oversampling).
3968 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3969 * @param ADCx ADC instance
3970 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3971 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)3972 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3973 {
3974 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3975 }
3976
3977 /**
3978 * @brief Get ADC group regular conversion data, range fit for
3979 * ADC resolution 12 bits.
3980 * @note For devices with feature oversampling: Oversampling
3981 * can increase data width, function for extended range
3982 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3983 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3984 * @param ADCx ADC instance
3985 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3986 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)3987 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3988 {
3989 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3990 }
3991
3992 /**
3993 * @brief Get ADC group regular conversion data, range fit for
3994 * ADC resolution 10 bits.
3995 * @note For devices with feature oversampling: Oversampling
3996 * can increase data width, function for extended range
3997 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3998 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
3999 * @param ADCx ADC instance
4000 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4001 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)4002 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
4003 {
4004 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4005 }
4006
4007 /**
4008 * @brief Get ADC group regular conversion data, range fit for
4009 * ADC resolution 8 bits.
4010 * @note For devices with feature oversampling: Oversampling
4011 * can increase data width, function for extended range
4012 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4013 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
4014 * @param ADCx ADC instance
4015 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4016 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)4017 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
4018 {
4019 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4020 }
4021
4022 /**
4023 * @brief Get ADC group regular conversion data, range fit for
4024 * ADC resolution 6 bits.
4025 * @note For devices with feature oversampling: Oversampling
4026 * can increase data width, function for extended range
4027 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4028 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
4029 * @param ADCx ADC instance
4030 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4031 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)4032 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
4033 {
4034 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4035 }
4036
4037 #if defined(ADC_MULTIMODE_SUPPORT)
4038 /**
4039 * @brief Get ADC multimode conversion data of ADC master, ADC slave
4040 * or raw data with ADC master and slave concatenated.
4041 * @note If raw data with ADC master and slave concatenated is retrieved,
4042 * a macro is available to get the conversion data of
4043 * ADC master or ADC slave: see helper macro
4044 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
4045 * (however this macro is mainly intended for multimode
4046 * transfer by DMA, because this function can do the same
4047 * by getting multimode conversion data of ADC master or ADC slave
4048 * separately).
4049 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
4050 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
4051 * @param ADCxy_COMMON ADC common instance
4052 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4053 * @param ConversionData This parameter can be one of the following values:
4054 * @arg @ref LL_ADC_MULTI_MASTER
4055 * @arg @ref LL_ADC_MULTI_SLAVE
4056 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
4057 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4058 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)4059 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
4060 {
4061 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
4062 ADC_DR_ADC2DATA)
4063 >> POSITION_VAL(ConversionData)
4064 );
4065 }
4066 #endif /* ADC_MULTIMODE_SUPPORT */
4067
4068 /**
4069 * @}
4070 */
4071
4072 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
4073 * @{
4074 */
4075
4076 /**
4077 * @brief Start ADC group injected conversion.
4078 * @note On this STM32 series, this function is relevant only for
4079 * internal trigger (SW start), not for external trigger:
4080 * - If ADC trigger has been set to software start, ADC conversion
4081 * starts immediately.
4082 * - If ADC trigger has been set to external trigger, ADC conversion
4083 * start must be performed using function
4084 * @ref LL_ADC_INJ_StartConversionExtTrig().
4085 * (if external trigger edge would have been set during ADC other
4086 * settings, ADC conversion would start at trigger event
4087 * as soon as ADC is enabled).
4088 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
4089 * @param ADCx ADC instance
4090 * @retval None
4091 */
LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef * ADCx)4092 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4093 {
4094 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4095 }
4096
4097 /**
4098 * @brief Start ADC group injected conversion from external trigger.
4099 * @note ADC conversion will start at next trigger event (on the selected
4100 * trigger edge) following the ADC start conversion command.
4101 * @note On this STM32 series, this function is relevant for
4102 * ADC conversion start from external trigger.
4103 * If internal trigger (SW start) is needed, perform ADC conversion
4104 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
4105 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
4106 * @param ExternalTriggerEdge This parameter can be one of the following values:
4107 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4108 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4109 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4110 * @param ADCx ADC instance
4111 * @retval None
4112 */
LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4113 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4114 {
4115 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4116 }
4117
4118 /**
4119 * @brief Stop ADC group injected conversion from external trigger.
4120 * @note No more ADC conversion will start at next trigger event
4121 * following the ADC stop conversion command.
4122 * If a conversion is on-going, it will be completed.
4123 * @note On this STM32 series, there is no specific command
4124 * to stop a conversion on-going or to stop ADC converting
4125 * in continuous mode. These actions can be performed
4126 * using function @ref LL_ADC_Disable().
4127 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
4128 * @param ADCx ADC instance
4129 * @retval None
4130 */
LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef * ADCx)4131 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4132 {
4133 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4134 }
4135
4136 /**
4137 * @brief Get ADC group regular conversion data, range fit for
4138 * all ADC configurations: all ADC resolutions and
4139 * all oversampling increased data width (for devices
4140 * with feature oversampling).
4141 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
4142 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
4143 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
4144 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
4145 * @param ADCx ADC instance
4146 * @param Rank This parameter can be one of the following values:
4147 * @arg @ref LL_ADC_INJ_RANK_1
4148 * @arg @ref LL_ADC_INJ_RANK_2
4149 * @arg @ref LL_ADC_INJ_RANK_3
4150 * @arg @ref LL_ADC_INJ_RANK_4
4151 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4152 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)4153 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
4154 {
4155 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4156
4157 return (uint32_t)(READ_BIT(*preg,
4158 ADC_JDR1_JDATA)
4159 );
4160 }
4161
4162 /**
4163 * @brief Get ADC group injected conversion data, range fit for
4164 * ADC resolution 12 bits.
4165 * @note For devices with feature oversampling: Oversampling
4166 * can increase data width, function for extended range
4167 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4168 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4169 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4170 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4171 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4172 * @param ADCx ADC instance
4173 * @param Rank This parameter can be one of the following values:
4174 * @arg @ref LL_ADC_INJ_RANK_1
4175 * @arg @ref LL_ADC_INJ_RANK_2
4176 * @arg @ref LL_ADC_INJ_RANK_3
4177 * @arg @ref LL_ADC_INJ_RANK_4
4178 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4179 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)4180 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
4181 {
4182 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4183
4184 return (uint16_t)(READ_BIT(*preg,
4185 ADC_JDR1_JDATA)
4186 );
4187 }
4188
4189 /**
4190 * @brief Get ADC group injected conversion data, range fit for
4191 * ADC resolution 10 bits.
4192 * @note For devices with feature oversampling: Oversampling
4193 * can increase data width, function for extended range
4194 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4195 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4196 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4197 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4198 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4199 * @param ADCx ADC instance
4200 * @param Rank This parameter can be one of the following values:
4201 * @arg @ref LL_ADC_INJ_RANK_1
4202 * @arg @ref LL_ADC_INJ_RANK_2
4203 * @arg @ref LL_ADC_INJ_RANK_3
4204 * @arg @ref LL_ADC_INJ_RANK_4
4205 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4206 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)4207 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
4208 {
4209 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4210
4211 return (uint16_t)(READ_BIT(*preg,
4212 ADC_JDR1_JDATA)
4213 );
4214 }
4215
4216 /**
4217 * @brief Get ADC group injected conversion data, range fit for
4218 * ADC resolution 8 bits.
4219 * @note For devices with feature oversampling: Oversampling
4220 * can increase data width, function for extended range
4221 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4222 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4223 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4224 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4225 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4226 * @param ADCx ADC instance
4227 * @param Rank This parameter can be one of the following values:
4228 * @arg @ref LL_ADC_INJ_RANK_1
4229 * @arg @ref LL_ADC_INJ_RANK_2
4230 * @arg @ref LL_ADC_INJ_RANK_3
4231 * @arg @ref LL_ADC_INJ_RANK_4
4232 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4233 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)4234 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
4235 {
4236 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4237
4238 return (uint8_t)(READ_BIT(*preg,
4239 ADC_JDR1_JDATA)
4240 );
4241 }
4242
4243 /**
4244 * @brief Get ADC group injected conversion data, range fit for
4245 * ADC resolution 6 bits.
4246 * @note For devices with feature oversampling: Oversampling
4247 * can increase data width, function for extended range
4248 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4249 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4250 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4251 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4252 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4253 * @param ADCx ADC instance
4254 * @param Rank This parameter can be one of the following values:
4255 * @arg @ref LL_ADC_INJ_RANK_1
4256 * @arg @ref LL_ADC_INJ_RANK_2
4257 * @arg @ref LL_ADC_INJ_RANK_3
4258 * @arg @ref LL_ADC_INJ_RANK_4
4259 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4260 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)4261 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
4262 {
4263 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4264
4265 return (uint8_t)(READ_BIT(*preg,
4266 ADC_JDR1_JDATA)
4267 );
4268 }
4269
4270 /**
4271 * @}
4272 */
4273
4274 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4275 * @{
4276 */
4277
4278 /**
4279 * @brief Get flag ADC group regular end of unitary conversion
4280 * or end of sequence conversions, depending on
4281 * ADC configuration.
4282 * @note To configure flag of end of conversion,
4283 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4284 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4285 * @param ADCx ADC instance
4286 * @retval State of bit (1 or 0).
4287 */
LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef * ADCx)4288 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
4289 {
4290 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4291 }
4292
4293 /**
4294 * @brief Get flag ADC group regular overrun.
4295 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4296 * @param ADCx ADC instance
4297 * @retval State of bit (1 or 0).
4298 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)4299 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4300 {
4301 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4302 }
4303
4304
4305 /**
4306 * @brief Get flag ADC group injected end of sequence conversions.
4307 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4308 * @param ADCx ADC instance
4309 * @retval State of bit (1 or 0).
4310 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)4311 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
4312 {
4313 /* Note: on this STM32 series, there is no flag ADC group injected */
4314 /* end of unitary conversion. */
4315 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4316 /* in other STM32 families). */
4317 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4318 }
4319
4320 /**
4321 * @brief Get flag ADC analog watchdog 1 flag
4322 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4323 * @param ADCx ADC instance
4324 * @retval State of bit (1 or 0).
4325 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)4326 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4327 {
4328 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4329 }
4330
4331 /**
4332 * @brief Clear flag ADC group regular end of unitary conversion
4333 * or end of sequence conversions, depending on
4334 * ADC configuration.
4335 * @note To configure flag of end of conversion,
4336 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4337 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4338 * @param ADCx ADC instance
4339 * @retval None
4340 */
LL_ADC_ClearFlag_EOCS(ADC_TypeDef * ADCx)4341 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4342 {
4343 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4344 }
4345
4346 /**
4347 * @brief Clear flag ADC group regular overrun.
4348 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4349 * @param ADCx ADC instance
4350 * @retval None
4351 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4352 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4353 {
4354 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4355 }
4356
4357
4358 /**
4359 * @brief Clear flag ADC group injected end of sequence conversions.
4360 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4361 * @param ADCx ADC instance
4362 * @retval None
4363 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)4364 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4365 {
4366 /* Note: on this STM32 series, there is no flag ADC group injected */
4367 /* end of unitary conversion. */
4368 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4369 /* in other STM32 families). */
4370 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4371 }
4372
4373 /**
4374 * @brief Clear flag ADC analog watchdog 1.
4375 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4376 * @param ADCx ADC instance
4377 * @retval None
4378 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4379 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4380 {
4381 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4382 }
4383
4384 #if defined(ADC_MULTIMODE_SUPPORT)
4385 /**
4386 * @brief Get flag multimode ADC group regular end of unitary conversion
4387 * or end of sequence conversions, depending on
4388 * ADC configuration, of the ADC master.
4389 * @note To configure flag of end of conversion,
4390 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4391 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
4392 * @param ADCxy_COMMON ADC common instance
4393 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4394 * @retval State of bit (1 or 0).
4395 */
LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4396 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4397 {
4398 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4399 }
4400
4401 /**
4402 * @brief Get flag multimode ADC group regular end of unitary conversion
4403 * or end of sequence conversions, depending on
4404 * ADC configuration, of the ADC slave 1.
4405 * @note To configure flag of end of conversion,
4406 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4407 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
4408 * @param ADCxy_COMMON ADC common instance
4409 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4410 * @retval State of bit (1 or 0).
4411 */
LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4412 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4413 {
4414 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4415 }
4416
4417 /**
4418 * @brief Get flag multimode ADC group regular end of unitary conversion
4419 * or end of sequence conversions, depending on
4420 * ADC configuration, of the ADC slave 2.
4421 * @note To configure flag of end of conversion,
4422 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4423 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
4424 * @param ADCxy_COMMON ADC common instance
4425 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4426 * @retval State of bit (1 or 0).
4427 */
LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef * ADCxy_COMMON)4428 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4429 {
4430 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4431 }
4432 /**
4433 * @brief Get flag multimode ADC group regular overrun of the ADC master.
4434 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
4435 * @param ADCxy_COMMON ADC common instance
4436 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4437 * @retval State of bit (1 or 0).
4438 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4439 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4440 {
4441 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4442 }
4443
4444 /**
4445 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
4446 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
4447 * @param ADCxy_COMMON ADC common instance
4448 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4449 * @retval State of bit (1 or 0).
4450 */
LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4451 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4452 {
4453 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4454 }
4455
4456 /**
4457 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
4458 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
4459 * @param ADCxy_COMMON ADC common instance
4460 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4461 * @retval State of bit (1 or 0).
4462 */
LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef * ADCxy_COMMON)4463 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4464 {
4465 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4466 }
4467
4468
4469 /**
4470 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
4471 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
4472 * @param ADCxy_COMMON ADC common instance
4473 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4474 * @retval State of bit (1 or 0).
4475 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4476 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4477 {
4478 /* Note: on this STM32 series, there is no flag ADC group injected */
4479 /* end of unitary conversion. */
4480 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4481 /* in other STM32 families). */
4482 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4483 }
4484
4485 /**
4486 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
4487 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
4488 * @param ADCxy_COMMON ADC common instance
4489 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4490 * @retval State of bit (1 or 0).
4491 */
LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4492 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4493 {
4494 /* Note: on this STM32 series, there is no flag ADC group injected */
4495 /* end of unitary conversion. */
4496 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4497 /* in other STM32 families). */
4498 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4499 }
4500
4501 /**
4502 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
4503 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
4504 * @param ADCxy_COMMON ADC common instance
4505 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4506 * @retval State of bit (1 or 0).
4507 */
LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)4508 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4509 {
4510 /* Note: on this STM32 series, there is no flag ADC group injected */
4511 /* end of unitary conversion. */
4512 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4513 /* in other STM32 families). */
4514 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4515 }
4516
4517 /**
4518 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
4519 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
4520 * @param ADCxy_COMMON ADC common instance
4521 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4522 * @retval State of bit (1 or 0).
4523 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4524 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4525 {
4526 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4527 }
4528
4529 /**
4530 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
4531 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
4532 * @param ADCxy_COMMON ADC common instance
4533 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4534 * @retval State of bit (1 or 0).
4535 */
LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4536 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4537 {
4538 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4539 }
4540
4541 /**
4542 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
4543 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
4544 * @param ADCxy_COMMON ADC common instance
4545 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4546 * @retval State of bit (1 or 0).
4547 */
LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)4548 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4549 {
4550 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4551 }
4552
4553 #endif /* ADC_MULTIMODE_SUPPORT */
4554
4555 /**
4556 * @}
4557 */
4558
4559 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4560 * @{
4561 */
4562
4563 /**
4564 * @brief Enable interruption ADC group regular end of unitary conversion
4565 * or end of sequence conversions, depending on
4566 * ADC configuration.
4567 * @note To configure flag of end of conversion,
4568 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4569 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4570 * @param ADCx ADC instance
4571 * @retval None
4572 */
LL_ADC_EnableIT_EOCS(ADC_TypeDef * ADCx)4573 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4574 {
4575 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4576 }
4577
4578 /**
4579 * @brief Enable ADC group regular interruption overrun.
4580 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4581 * @param ADCx ADC instance
4582 * @retval None
4583 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4584 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4585 {
4586 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4587 }
4588
4589
4590 /**
4591 * @brief Enable interruption ADC group injected end of sequence conversions.
4592 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4593 * @param ADCx ADC instance
4594 * @retval None
4595 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)4596 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4597 {
4598 /* Note: on this STM32 series, there is no flag ADC group injected */
4599 /* end of unitary conversion. */
4600 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4601 /* in other STM32 families). */
4602 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4603 }
4604
4605 /**
4606 * @brief Enable interruption ADC analog watchdog 1.
4607 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4608 * @param ADCx ADC instance
4609 * @retval None
4610 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4611 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4612 {
4613 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4614 }
4615
4616 /**
4617 * @brief Disable interruption ADC group regular end of unitary conversion
4618 * or end of sequence conversions, depending on
4619 * ADC configuration.
4620 * @note To configure flag of end of conversion,
4621 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4622 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
4623 * @param ADCx ADC instance
4624 * @retval None
4625 */
LL_ADC_DisableIT_EOCS(ADC_TypeDef * ADCx)4626 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4627 {
4628 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4629 }
4630
4631 /**
4632 * @brief Disable interruption ADC group regular overrun.
4633 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
4634 * @param ADCx ADC instance
4635 * @retval None
4636 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4637 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4638 {
4639 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4640 }
4641
4642
4643 /**
4644 * @brief Disable interruption ADC group injected end of sequence conversions.
4645 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4646 * @param ADCx ADC instance
4647 * @retval None
4648 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)4649 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4650 {
4651 /* Note: on this STM32 series, there is no flag ADC group injected */
4652 /* end of unitary conversion. */
4653 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4654 /* in other STM32 families). */
4655 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4656 }
4657
4658 /**
4659 * @brief Disable interruption ADC analog watchdog 1.
4660 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4661 * @param ADCx ADC instance
4662 * @retval None
4663 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4664 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4665 {
4666 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4667 }
4668
4669 /**
4670 * @brief Get state of interruption ADC group regular end of unitary conversion
4671 * or end of sequence conversions, depending on
4672 * ADC configuration.
4673 * @note To configure flag of end of conversion,
4674 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4675 * (0: interrupt disabled, 1: interrupt enabled)
4676 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
4677 * @param ADCx ADC instance
4678 * @retval State of bit (1 or 0).
4679 */
LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef * ADCx)4680 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
4681 {
4682 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4683 }
4684
4685 /**
4686 * @brief Get state of interruption ADC group regular overrun
4687 * (0: interrupt disabled, 1: interrupt enabled).
4688 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
4689 * @param ADCx ADC instance
4690 * @retval State of bit (1 or 0).
4691 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)4692 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
4693 {
4694 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4695 }
4696
4697
4698 /**
4699 * @brief Get state of interruption ADC group injected end of sequence conversions
4700 * (0: interrupt disabled, 1: interrupt enabled).
4701 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4702 * @param ADCx ADC instance
4703 * @retval State of bit (1 or 0).
4704 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)4705 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
4706 {
4707 /* Note: on this STM32 series, there is no flag ADC group injected */
4708 /* end of unitary conversion. */
4709 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4710 /* in other STM32 families). */
4711 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4712 }
4713
4714 /**
4715 * @brief Get state of interruption ADC analog watchdog 1
4716 * (0: interrupt disabled, 1: interrupt enabled).
4717 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4718 * @param ADCx ADC instance
4719 * @retval State of bit (1 or 0).
4720 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)4721 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
4722 {
4723 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4724 }
4725
4726 /**
4727 * @}
4728 */
4729
4730 #if defined(USE_FULL_LL_DRIVER)
4731 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4732 * @{
4733 */
4734
4735 /* Initialization of some features of ADC common parameters and multimode */
4736 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4737 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4738 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4739
4740 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
4741 /* (availability of ADC group injected depends on STM32 families) */
4742 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4743
4744 /* Initialization of some features of ADC instance */
4745 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4746 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4747
4748 /* Initialization of some features of ADC instance and ADC group regular */
4749 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4750 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4751
4752 /* Initialization of some features of ADC instance and ADC group injected */
4753 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4754 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4755
4756 /**
4757 * @}
4758 */
4759 #endif /* USE_FULL_LL_DRIVER */
4760
4761 /**
4762 * @}
4763 */
4764
4765 /**
4766 * @}
4767 */
4768
4769 #endif /* ADC1 || ADC2 || ADC3 */
4770
4771 /**
4772 * @}
4773 */
4774
4775 #ifdef __cplusplus
4776 }
4777 #endif
4778
4779 #endif /* __STM32F4xx_LL_ADC_H */
4780
4781 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4782