1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f4xx_ll_tim.h"
23 #include "stm32f4xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
36
37 /** @addtogroup TIM_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @addtogroup TIM_LL_Private_Macros
46 * @{
47 */
48 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
52 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
53
54 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
56 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
57
58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
66
67 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
68 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
69
70 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
71 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
72
73 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
74 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
75
76 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
77 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
78 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
79
80 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
81 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
82 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
83 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
84
85 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
86 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
87 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
88 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
89 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
90 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
101
102 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
103 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
104 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
105
106 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
107 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
108 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
109
110 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
111 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
112
113 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
114 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
115
116 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
117 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
118
119 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
120 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
121 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
122 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
123
124 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
125 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
126
127 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
128 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
129
130 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
131 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
132 /**
133 * @}
134 */
135
136
137 /* Private function prototypes -----------------------------------------------*/
138 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
139 * @{
140 */
141 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
144 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
145 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
148 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
149 /**
150 * @}
151 */
152
153 /* Exported functions --------------------------------------------------------*/
154 /** @addtogroup TIM_LL_Exported_Functions
155 * @{
156 */
157
158 /** @addtogroup TIM_LL_EF_Init
159 * @{
160 */
161
162 /**
163 * @brief Set TIMx registers to their reset values.
164 * @param TIMx Timer instance
165 * @retval An ErrorStatus enumeration value:
166 * - SUCCESS: TIMx registers are de-initialized
167 * - ERROR: invalid TIMx instance
168 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)169 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
170 {
171 ErrorStatus result = SUCCESS;
172
173 /* Check the parameters */
174 assert_param(IS_TIM_INSTANCE(TIMx));
175
176 if (TIMx == TIM1)
177 {
178 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
179 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
180 }
181 #if defined(TIM2)
182 else if (TIMx == TIM2)
183 {
184 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
185 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
186 }
187 #endif /* TIM2 */
188 #if defined(TIM3)
189 else if (TIMx == TIM3)
190 {
191 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
192 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
193 }
194 #endif /* TIM3 */
195 #if defined(TIM4)
196 else if (TIMx == TIM4)
197 {
198 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
199 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
200 }
201 #endif /* TIM4 */
202 #if defined(TIM5)
203 else if (TIMx == TIM5)
204 {
205 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
206 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
207 }
208 #endif /* TIM5 */
209 #if defined(TIM6)
210 else if (TIMx == TIM6)
211 {
212 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
213 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
214 }
215 #endif /* TIM6 */
216 #if defined (TIM7)
217 else if (TIMx == TIM7)
218 {
219 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
220 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
221 }
222 #endif /* TIM7 */
223 #if defined(TIM8)
224 else if (TIMx == TIM8)
225 {
226 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
227 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
228 }
229 #endif /* TIM8 */
230 #if defined(TIM9)
231 else if (TIMx == TIM9)
232 {
233 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
234 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
235 }
236 #endif /* TIM9 */
237 #if defined(TIM10)
238 else if (TIMx == TIM10)
239 {
240 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
241 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
242 }
243 #endif /* TIM10 */
244 #if defined(TIM11)
245 else if (TIMx == TIM11)
246 {
247 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
248 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
249 }
250 #endif /* TIM11 */
251 #if defined(TIM12)
252 else if (TIMx == TIM12)
253 {
254 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
255 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
256 }
257 #endif /* TIM12 */
258 #if defined(TIM13)
259 else if (TIMx == TIM13)
260 {
261 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
262 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
263 }
264 #endif /* TIM13 */
265 #if defined(TIM14)
266 else if (TIMx == TIM14)
267 {
268 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
269 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
270 }
271 #endif /* TIM14 */
272 else
273 {
274 result = ERROR;
275 }
276
277 return result;
278 }
279
280 /**
281 * @brief Set the fields of the time base unit configuration data structure
282 * to their default values.
283 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
284 * @retval None
285 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)286 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
287 {
288 /* Set the default configuration */
289 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
290 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
291 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
292 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
293 TIM_InitStruct->RepetitionCounter = 0x00000000U;
294 }
295
296 /**
297 * @brief Configure the TIMx time base unit.
298 * @param TIMx Timer Instance
299 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
300 * (TIMx time base unit configuration data structure)
301 * @retval An ErrorStatus enumeration value:
302 * - SUCCESS: TIMx registers are de-initialized
303 * - ERROR: not applicable
304 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)305 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
306 {
307 uint32_t tmpcr1;
308
309 /* Check the parameters */
310 assert_param(IS_TIM_INSTANCE(TIMx));
311 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
312 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
313
314 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
315
316 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
317 {
318 /* Select the Counter Mode */
319 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
320 }
321
322 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
323 {
324 /* Set the clock division */
325 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
326 }
327
328 /* Write to TIMx CR1 */
329 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
330
331 /* Set the Autoreload value */
332 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
333
334 /* Set the Prescaler value */
335 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
336
337 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
338 {
339 /* Set the Repetition Counter value */
340 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
341 }
342
343 /* Generate an update event to reload the Prescaler
344 and the repetition counter value (if applicable) immediately */
345 LL_TIM_GenerateEvent_UPDATE(TIMx);
346
347 return SUCCESS;
348 }
349
350 /**
351 * @brief Set the fields of the TIMx output channel configuration data
352 * structure to their default values.
353 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
354 * (the output channel configuration data structure)
355 * @retval None
356 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)357 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
358 {
359 /* Set the default configuration */
360 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
361 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
362 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
363 TIM_OC_InitStruct->CompareValue = 0x00000000U;
364 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
365 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
366 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
367 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
368 }
369
370 /**
371 * @brief Configure the TIMx output channel.
372 * @param TIMx Timer Instance
373 * @param Channel This parameter can be one of the following values:
374 * @arg @ref LL_TIM_CHANNEL_CH1
375 * @arg @ref LL_TIM_CHANNEL_CH2
376 * @arg @ref LL_TIM_CHANNEL_CH3
377 * @arg @ref LL_TIM_CHANNEL_CH4
378 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
379 * data structure)
380 * @retval An ErrorStatus enumeration value:
381 * - SUCCESS: TIMx output channel is initialized
382 * - ERROR: TIMx output channel is not initialized
383 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)384 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
385 {
386 ErrorStatus result = ERROR;
387
388 switch (Channel)
389 {
390 case LL_TIM_CHANNEL_CH1:
391 result = OC1Config(TIMx, TIM_OC_InitStruct);
392 break;
393 case LL_TIM_CHANNEL_CH2:
394 result = OC2Config(TIMx, TIM_OC_InitStruct);
395 break;
396 case LL_TIM_CHANNEL_CH3:
397 result = OC3Config(TIMx, TIM_OC_InitStruct);
398 break;
399 case LL_TIM_CHANNEL_CH4:
400 result = OC4Config(TIMx, TIM_OC_InitStruct);
401 break;
402 default:
403 break;
404 }
405
406 return result;
407 }
408
409 /**
410 * @brief Set the fields of the TIMx input channel configuration data
411 * structure to their default values.
412 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
413 * data structure)
414 * @retval None
415 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)416 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
417 {
418 /* Set the default configuration */
419 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
420 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
421 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
422 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
423 }
424
425 /**
426 * @brief Configure the TIMx input channel.
427 * @param TIMx Timer Instance
428 * @param Channel This parameter can be one of the following values:
429 * @arg @ref LL_TIM_CHANNEL_CH1
430 * @arg @ref LL_TIM_CHANNEL_CH2
431 * @arg @ref LL_TIM_CHANNEL_CH3
432 * @arg @ref LL_TIM_CHANNEL_CH4
433 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
434 * structure)
435 * @retval An ErrorStatus enumeration value:
436 * - SUCCESS: TIMx output channel is initialized
437 * - ERROR: TIMx output channel is not initialized
438 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)439 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
440 {
441 ErrorStatus result = ERROR;
442
443 switch (Channel)
444 {
445 case LL_TIM_CHANNEL_CH1:
446 result = IC1Config(TIMx, TIM_IC_InitStruct);
447 break;
448 case LL_TIM_CHANNEL_CH2:
449 result = IC2Config(TIMx, TIM_IC_InitStruct);
450 break;
451 case LL_TIM_CHANNEL_CH3:
452 result = IC3Config(TIMx, TIM_IC_InitStruct);
453 break;
454 case LL_TIM_CHANNEL_CH4:
455 result = IC4Config(TIMx, TIM_IC_InitStruct);
456 break;
457 default:
458 break;
459 }
460
461 return result;
462 }
463
464 /**
465 * @brief Fills each TIM_EncoderInitStruct field with its default value
466 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
467 * configuration data structure)
468 * @retval None
469 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)470 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
471 {
472 /* Set the default configuration */
473 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
474 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
475 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
476 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
477 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
478 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
479 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
480 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
481 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
482 }
483
484 /**
485 * @brief Configure the encoder interface of the timer instance.
486 * @param TIMx Timer Instance
487 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
488 * configuration data structure)
489 * @retval An ErrorStatus enumeration value:
490 * - SUCCESS: TIMx registers are de-initialized
491 * - ERROR: not applicable
492 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)493 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
494 {
495 uint32_t tmpccmr1;
496 uint32_t tmpccer;
497
498 /* Check the parameters */
499 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
500 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
501 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
502 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
503 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
504 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
505 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
506 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
507 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
508 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
509
510 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
511 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
512
513 /* Get the TIMx CCMR1 register value */
514 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
515
516 /* Get the TIMx CCER register value */
517 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
518
519 /* Configure TI1 */
520 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
521 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
522 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
523 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
524
525 /* Configure TI2 */
526 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
527 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
528 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
529 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
530
531 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
532 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
533 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
534 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
535 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
536
537 /* Set encoder mode */
538 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
539
540 /* Write to TIMx CCMR1 */
541 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
542
543 /* Write to TIMx CCER */
544 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
545
546 return SUCCESS;
547 }
548
549 /**
550 * @brief Set the fields of the TIMx Hall sensor interface configuration data
551 * structure to their default values.
552 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
553 * configuration data structure)
554 * @retval None
555 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)556 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
557 {
558 /* Set the default configuration */
559 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
560 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
561 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
562 TIM_HallSensorInitStruct->CommutationDelay = 0U;
563 }
564
565 /**
566 * @brief Configure the Hall sensor interface of the timer instance.
567 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
568 * to the TI1 input channel
569 * @note TIMx slave mode controller is configured in reset mode.
570 Selected internal trigger is TI1F_ED.
571 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
572 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
573 * between 2 changes on the inputs. It gives information about motor speed.
574 * @note Channel 2 is configured in output PWM 2 mode.
575 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
576 * @note OC2REF is selected as trigger output on TRGO.
577 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
578 * when TIMx operates in Hall sensor interface mode.
579 * @param TIMx Timer Instance
580 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
581 * interface configuration data structure)
582 * @retval An ErrorStatus enumeration value:
583 * - SUCCESS: TIMx registers are de-initialized
584 * - ERROR: not applicable
585 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)586 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
587 {
588 uint32_t tmpcr2;
589 uint32_t tmpccmr1;
590 uint32_t tmpccer;
591 uint32_t tmpsmcr;
592
593 /* Check the parameters */
594 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
595 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
596 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
597 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
598
599 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
600 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
601
602 /* Get the TIMx CR2 register value */
603 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
604
605 /* Get the TIMx CCMR1 register value */
606 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
607
608 /* Get the TIMx CCER register value */
609 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
610
611 /* Get the TIMx SMCR register value */
612 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
613
614 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
615 tmpcr2 |= TIM_CR2_TI1S;
616
617 /* OC2REF signal is used as trigger output (TRGO) */
618 tmpcr2 |= LL_TIM_TRGO_OC2REF;
619
620 /* Configure the slave mode controller */
621 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
622 tmpsmcr |= LL_TIM_TS_TI1F_ED;
623 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
624
625 /* Configure input channel 1 */
626 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
627 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
628 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
629 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
630
631 /* Configure input channel 2 */
632 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
633 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
634
635 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
636 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
637 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
638 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
639
640 /* Write to TIMx CR2 */
641 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
642
643 /* Write to TIMx SMCR */
644 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
645
646 /* Write to TIMx CCMR1 */
647 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
648
649 /* Write to TIMx CCER */
650 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
651
652 /* Write to TIMx CCR2 */
653 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
654
655 return SUCCESS;
656 }
657
658 /**
659 * @brief Set the fields of the Break and Dead Time configuration data structure
660 * to their default values.
661 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
662 * data structure)
663 * @retval None
664 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)665 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
666 {
667 /* Set the default configuration */
668 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
669 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
670 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
671 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
672 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
673 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
674 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
675 }
676
677 /**
678 * @brief Configure the Break and Dead Time feature of the timer instance.
679 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
680 * depending on the LOCK configuration, it can be necessary to configure all of
681 * them during the first write access to the TIMx_BDTR register.
682 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
683 * a timer instance provides a break input.
684 * @param TIMx Timer Instance
685 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
686 * data structure)
687 * @retval An ErrorStatus enumeration value:
688 * - SUCCESS: Break and Dead Time is initialized
689 * - ERROR: not applicable
690 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)691 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
692 {
693 uint32_t tmpbdtr = 0;
694
695 /* Check the parameters */
696 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
697 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
698 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
699 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
700 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
701 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
702 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
703
704 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
705 the OSSI State, the dead time value and the Automatic Output Enable Bit */
706
707 /* Set the BDTR bits */
708 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
709 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
710 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
711 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
712 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
713 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
714 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
715 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
716
717 /* Set TIMx_BDTR */
718 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
719
720 return SUCCESS;
721 }
722 /**
723 * @}
724 */
725
726 /**
727 * @}
728 */
729
730 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
731 * @brief Private functions
732 * @{
733 */
734 /**
735 * @brief Configure the TIMx output channel 1.
736 * @param TIMx Timer Instance
737 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
738 * @retval An ErrorStatus enumeration value:
739 * - SUCCESS: TIMx registers are de-initialized
740 * - ERROR: not applicable
741 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)742 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
743 {
744 uint32_t tmpccmr1;
745 uint32_t tmpccer;
746 uint32_t tmpcr2;
747
748 /* Check the parameters */
749 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
750 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
751 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
752 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
753 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
754 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
755
756 /* Disable the Channel 1: Reset the CC1E Bit */
757 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
758
759 /* Get the TIMx CCER register value */
760 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
761
762 /* Get the TIMx CR2 register value */
763 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
764
765 /* Get the TIMx CCMR1 register value */
766 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
767
768 /* Reset Capture/Compare selection Bits */
769 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
770
771 /* Set the Output Compare Mode */
772 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
773
774 /* Set the Output Compare Polarity */
775 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
776
777 /* Set the Output State */
778 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
779
780 if (IS_TIM_BREAK_INSTANCE(TIMx))
781 {
782 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
783 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
784
785 /* Set the complementary output Polarity */
786 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
787
788 /* Set the complementary output State */
789 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
790
791 /* Set the Output Idle state */
792 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
793
794 /* Set the complementary output Idle state */
795 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
796 }
797
798 /* Write to TIMx CR2 */
799 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
800
801 /* Write to TIMx CCMR1 */
802 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
803
804 /* Set the Capture Compare Register value */
805 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
806
807 /* Write to TIMx CCER */
808 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
809
810 return SUCCESS;
811 }
812
813 /**
814 * @brief Configure the TIMx output channel 2.
815 * @param TIMx Timer Instance
816 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
817 * @retval An ErrorStatus enumeration value:
818 * - SUCCESS: TIMx registers are de-initialized
819 * - ERROR: not applicable
820 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)821 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
822 {
823 uint32_t tmpccmr1;
824 uint32_t tmpccer;
825 uint32_t tmpcr2;
826
827 /* Check the parameters */
828 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
829 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
830 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
831 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
832 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
833 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
834
835 /* Disable the Channel 2: Reset the CC2E Bit */
836 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
837
838 /* Get the TIMx CCER register value */
839 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
840
841 /* Get the TIMx CR2 register value */
842 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
843
844 /* Get the TIMx CCMR1 register value */
845 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
846
847 /* Reset Capture/Compare selection Bits */
848 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
849
850 /* Select the Output Compare Mode */
851 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
852
853 /* Set the Output Compare Polarity */
854 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
855
856 /* Set the Output State */
857 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
858
859 if (IS_TIM_BREAK_INSTANCE(TIMx))
860 {
861 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
862 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
863
864 /* Set the complementary output Polarity */
865 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
866
867 /* Set the complementary output State */
868 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
869
870 /* Set the Output Idle state */
871 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
872
873 /* Set the complementary output Idle state */
874 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
875 }
876
877 /* Write to TIMx CR2 */
878 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
879
880 /* Write to TIMx CCMR1 */
881 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
882
883 /* Set the Capture Compare Register value */
884 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
885
886 /* Write to TIMx CCER */
887 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
888
889 return SUCCESS;
890 }
891
892 /**
893 * @brief Configure the TIMx output channel 3.
894 * @param TIMx Timer Instance
895 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
896 * @retval An ErrorStatus enumeration value:
897 * - SUCCESS: TIMx registers are de-initialized
898 * - ERROR: not applicable
899 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)900 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
901 {
902 uint32_t tmpccmr2;
903 uint32_t tmpccer;
904 uint32_t tmpcr2;
905
906 /* Check the parameters */
907 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
908 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
909 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
910 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
911 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
912 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
913
914 /* Disable the Channel 3: Reset the CC3E Bit */
915 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
916
917 /* Get the TIMx CCER register value */
918 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
919
920 /* Get the TIMx CR2 register value */
921 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
922
923 /* Get the TIMx CCMR2 register value */
924 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
925
926 /* Reset Capture/Compare selection Bits */
927 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
928
929 /* Select the Output Compare Mode */
930 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
931
932 /* Set the Output Compare Polarity */
933 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
934
935 /* Set the Output State */
936 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
937
938 if (IS_TIM_BREAK_INSTANCE(TIMx))
939 {
940 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
941 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
942
943 /* Set the complementary output Polarity */
944 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
945
946 /* Set the complementary output State */
947 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
948
949 /* Set the Output Idle state */
950 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
951
952 /* Set the complementary output Idle state */
953 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
954 }
955
956 /* Write to TIMx CR2 */
957 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
958
959 /* Write to TIMx CCMR2 */
960 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
961
962 /* Set the Capture Compare Register value */
963 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
964
965 /* Write to TIMx CCER */
966 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
967
968 return SUCCESS;
969 }
970
971 /**
972 * @brief Configure the TIMx output channel 4.
973 * @param TIMx Timer Instance
974 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
975 * @retval An ErrorStatus enumeration value:
976 * - SUCCESS: TIMx registers are de-initialized
977 * - ERROR: not applicable
978 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)979 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
980 {
981 uint32_t tmpccmr2;
982 uint32_t tmpccer;
983 uint32_t tmpcr2;
984
985 /* Check the parameters */
986 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
987 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
988 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
989 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
990 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
991 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
992
993 /* Disable the Channel 4: Reset the CC4E Bit */
994 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
995
996 /* Get the TIMx CCER register value */
997 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
998
999 /* Get the TIMx CR2 register value */
1000 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1001
1002 /* Get the TIMx CCMR2 register value */
1003 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1004
1005 /* Reset Capture/Compare selection Bits */
1006 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1007
1008 /* Select the Output Compare Mode */
1009 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1010
1011 /* Set the Output Compare Polarity */
1012 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1013
1014 /* Set the Output State */
1015 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1016
1017 if (IS_TIM_BREAK_INSTANCE(TIMx))
1018 {
1019 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1020 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1021
1022 /* Set the Output Idle state */
1023 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1024 }
1025
1026 /* Write to TIMx CR2 */
1027 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1028
1029 /* Write to TIMx CCMR2 */
1030 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1031
1032 /* Set the Capture Compare Register value */
1033 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1034
1035 /* Write to TIMx CCER */
1036 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1037
1038 return SUCCESS;
1039 }
1040
1041
1042 /**
1043 * @brief Configure the TIMx input channel 1.
1044 * @param TIMx Timer Instance
1045 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1046 * @retval An ErrorStatus enumeration value:
1047 * - SUCCESS: TIMx registers are de-initialized
1048 * - ERROR: not applicable
1049 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1050 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1051 {
1052 /* Check the parameters */
1053 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1054 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1055 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1056 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1057 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1058
1059 /* Disable the Channel 1: Reset the CC1E Bit */
1060 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1061
1062 /* Select the Input and set the filter and the prescaler value */
1063 MODIFY_REG(TIMx->CCMR1,
1064 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1065 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1066
1067 /* Select the Polarity and set the CC1E Bit */
1068 MODIFY_REG(TIMx->CCER,
1069 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1070 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1071
1072 return SUCCESS;
1073 }
1074
1075 /**
1076 * @brief Configure the TIMx input channel 2.
1077 * @param TIMx Timer Instance
1078 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1079 * @retval An ErrorStatus enumeration value:
1080 * - SUCCESS: TIMx registers are de-initialized
1081 * - ERROR: not applicable
1082 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1083 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1084 {
1085 /* Check the parameters */
1086 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1087 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1088 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1089 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1090 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1091
1092 /* Disable the Channel 2: Reset the CC2E Bit */
1093 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1094
1095 /* Select the Input and set the filter and the prescaler value */
1096 MODIFY_REG(TIMx->CCMR1,
1097 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1098 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1099
1100 /* Select the Polarity and set the CC2E Bit */
1101 MODIFY_REG(TIMx->CCER,
1102 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1103 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1104
1105 return SUCCESS;
1106 }
1107
1108 /**
1109 * @brief Configure the TIMx input channel 3.
1110 * @param TIMx Timer Instance
1111 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1112 * @retval An ErrorStatus enumeration value:
1113 * - SUCCESS: TIMx registers are de-initialized
1114 * - ERROR: not applicable
1115 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1116 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1117 {
1118 /* Check the parameters */
1119 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1120 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1121 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1122 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1123 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1124
1125 /* Disable the Channel 3: Reset the CC3E Bit */
1126 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1127
1128 /* Select the Input and set the filter and the prescaler value */
1129 MODIFY_REG(TIMx->CCMR2,
1130 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1131 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1132
1133 /* Select the Polarity and set the CC3E Bit */
1134 MODIFY_REG(TIMx->CCER,
1135 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1136 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1137
1138 return SUCCESS;
1139 }
1140
1141 /**
1142 * @brief Configure the TIMx input channel 4.
1143 * @param TIMx Timer Instance
1144 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1145 * @retval An ErrorStatus enumeration value:
1146 * - SUCCESS: TIMx registers are de-initialized
1147 * - ERROR: not applicable
1148 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1149 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1150 {
1151 /* Check the parameters */
1152 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1153 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1154 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1155 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1156 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1157
1158 /* Disable the Channel 4: Reset the CC4E Bit */
1159 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1160
1161 /* Select the Input and set the filter and the prescaler value */
1162 MODIFY_REG(TIMx->CCMR2,
1163 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1164 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1165
1166 /* Select the Polarity and set the CC2E Bit */
1167 MODIFY_REG(TIMx->CCER,
1168 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1169 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1170
1171 return SUCCESS;
1172 }
1173
1174
1175 /**
1176 * @}
1177 */
1178
1179 /**
1180 * @}
1181 */
1182
1183 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
1184
1185 /**
1186 * @}
1187 */
1188
1189 #endif /* USE_FULL_LL_DRIVER */
1190
1191 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1192