1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_dfsdm.h 4 * @author MCD Application Team 5 * @brief Header file of DFSDM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32MP1xx_HAL_DFSDM_H 22 #define STM32MP1xx_HAL_DFSDM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 /** @addtogroup STM32MP1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DFSDM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief HAL DFSDM Channel states definition 46 */ 47 typedef enum 48 { 49 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 50 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 51 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 52 }HAL_DFSDM_Channel_StateTypeDef; 53 54 /** 55 * @brief DFSDM channel output clock structure definition 56 */ 57 typedef struct 58 { 59 FunctionalState Activation; /*!< Output clock enable/disable */ 60 uint32_t Selection; /*!< Output clock is system clock or audio clock. 61 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 62 uint32_t Divider; /*!< Output clock divider. 63 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 64 }DFSDM_Channel_OutputClockTypeDef; 65 66 /** 67 * @brief DFSDM channel input structure definition 68 */ 69 typedef struct 70 { 71 uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. 72 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 73 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 74 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 75 uint32_t Pins; /*!< Input pins are taken from same or following channel. 76 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 77 }DFSDM_Channel_InputTypeDef; 78 79 /** 80 * @brief DFSDM channel serial interface structure definition 81 */ 82 typedef struct 83 { 84 uint32_t Type; /*!< SPI or Manchester modes. 85 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 86 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 87 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 88 }DFSDM_Channel_SerialInterfaceTypeDef; 89 90 /** 91 * @brief DFSDM channel analog watchdog structure definition 92 */ 93 typedef struct 94 { 95 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 96 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 97 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 98 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 99 }DFSDM_Channel_AwdTypeDef; 100 101 /** 102 * @brief DFSDM channel init structure definition 103 */ 104 typedef struct 105 { 106 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 107 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 108 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 109 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 110 int32_t Offset; /*!< DFSDM channel offset. 111 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 112 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 114 }DFSDM_Channel_InitTypeDef; 115 116 /** 117 * @brief DFSDM channel handle structure definition 118 */ 119 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 120 typedef struct __DFSDM_Channel_HandleTypeDef 121 #else 122 typedef struct 123 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 124 { 125 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 126 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 127 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 128 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 129 void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 130 void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 131 void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 132 void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 133 #endif 134 }DFSDM_Channel_HandleTypeDef; 135 136 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 137 /** 138 * @brief DFSDM channel callback ID enumeration definition 139 */ 140 typedef enum 141 { 142 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 143 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 144 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 145 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 146 }HAL_DFSDM_Channel_CallbackIDTypeDef; 147 148 /** 149 * @brief DFSDM channel callback pointer definition 150 */ 151 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 152 #endif 153 154 /** 155 * @brief HAL DFSDM Filter states definition 156 */ 157 typedef enum 158 { 159 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 160 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 161 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 162 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 163 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 164 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 165 }HAL_DFSDM_Filter_StateTypeDef; 166 167 /** 168 * @brief DFSDM filter regular conversion parameters structure definition 169 */ 170 typedef struct 171 { 172 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 173 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 174 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 175 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 176 }DFSDM_Filter_RegularParamTypeDef; 177 178 /** 179 * @brief DFSDM filter injected conversion parameters structure definition 180 */ 181 typedef struct 182 { 183 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 184 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 185 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 186 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 187 uint32_t ExtTrigger; /*!< External trigger. 188 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 189 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 190 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 191 }DFSDM_Filter_InjectedParamTypeDef; 192 193 /** 194 * @brief DFSDM filter parameters structure definition 195 */ 196 typedef struct 197 { 198 uint32_t SincOrder; /*!< Sinc filter order. 199 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 200 uint32_t Oversampling; /*!< Filter oversampling ratio. 201 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 202 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 203 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 204 }DFSDM_Filter_FilterParamTypeDef; 205 206 /** 207 * @brief DFSDM filter init structure definition 208 */ 209 typedef struct 210 { 211 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 212 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 213 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 214 }DFSDM_Filter_InitTypeDef; 215 216 /** 217 * @brief DFSDM filter handle structure definition 218 */ 219 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 220 typedef struct __DFSDM_Filter_HandleTypeDef 221 #else 222 typedef struct 223 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 224 { 225 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 226 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 227 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 228 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 229 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 230 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 231 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 232 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 233 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 234 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 235 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 236 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 237 uint32_t ErrorCode; /*!< DFSDM filter error code */ 238 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 239 void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 240 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 241 void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 242 void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 243 void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 244 void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 245 void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 246 void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 247 void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 248 #endif 249 }DFSDM_Filter_HandleTypeDef; 250 251 /** 252 * @brief DFSDM filter analog watchdog parameters structure definition 253 */ 254 typedef struct 255 { 256 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 257 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 258 uint32_t Channel; /*!< Analog watchdog channel selection. 259 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 260 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 261 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 262 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 263 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 264 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 265 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 266 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 267 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 268 }DFSDM_Filter_AwdParamTypeDef; 269 270 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 271 /** 272 * @brief DFSDM filter callback ID enumeration definition 273 */ 274 typedef enum 275 { 276 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 277 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 278 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 279 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 280 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 281 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 282 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 283 }HAL_DFSDM_Filter_CallbackIDTypeDef; 284 285 /** 286 * @brief DFSDM filter callback pointer definition 287 */ 288 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 289 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 290 #endif 291 292 /** 293 * @} 294 */ 295 /* End of exported types -----------------------------------------------------*/ 296 297 /* Exported constants --------------------------------------------------------*/ 298 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 299 * @{ 300 */ 301 302 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 303 * @{ 304 */ 305 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ 306 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ 307 /** 308 * @} 309 */ 310 311 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 312 * @{ 313 */ 314 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ 315 #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ 316 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 322 * @{ 323 */ 324 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ 325 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 326 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 332 * @{ 333 */ 334 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ 335 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 336 /** 337 * @} 338 */ 339 340 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 341 * @{ 342 */ 343 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ 344 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 345 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 346 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 347 /** 348 * @} 349 */ 350 351 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 352 * @{ 353 */ 354 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ 355 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 356 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 357 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 358 /** 359 * @} 360 */ 361 362 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 363 * @{ 364 */ 365 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 366 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 367 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 368 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 369 /** 370 * @} 371 */ 372 373 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 374 * @{ 375 */ 376 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ 377 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ 378 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ 379 /** 380 * @} 381 */ 382 383 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 384 * @{ 385 */ 386 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */ 387 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ 388 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ 389 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ 390 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ 391 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 392 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 393 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 394 DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 395 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ 396 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 397 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ 398 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 399 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ 400 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 401 #define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 402 DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 403 #define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_3 | \ 404 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 405 /** 406 * @} 407 */ 408 409 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 410 * @{ 411 */ 412 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 413 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 414 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 415 /** 416 * @} 417 */ 418 419 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 420 * @{ 421 */ 422 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 423 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 424 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 425 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 426 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 427 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 433 * @{ 434 */ 435 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ 436 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 442 * @{ 443 */ 444 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ 445 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ 446 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ 447 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ 448 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 449 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ 450 #endif 451 /** 452 * @} 453 */ 454 455 /** @defgroup DFSDM_BreakSignals DFSDM break signals 456 * @{ 457 */ 458 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ 459 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ 460 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ 461 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ 462 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 468 * @{ 469 */ 470 /* DFSDM Channels ------------------------------------------------------------*/ 471 /* The DFSDM channels are defined as follows: 472 - in 16-bit LSB the channel mask is set 473 - in 16-bit MSB the channel number is set 474 e.g. for channel 5 definition: 475 - the channel mask is 0x00000020 (bit 5 is set) 476 - the channel number 5 is 0x00050000 477 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 478 #define DFSDM_CHANNEL_0 0x00000001U 479 #define DFSDM_CHANNEL_1 0x00010002U 480 #define DFSDM_CHANNEL_2 0x00020004U 481 #define DFSDM_CHANNEL_3 0x00030008U 482 #define DFSDM_CHANNEL_4 0x00040010U 483 #define DFSDM_CHANNEL_5 0x00050020U 484 #define DFSDM_CHANNEL_6 0x00060040U 485 #define DFSDM_CHANNEL_7 0x00070080U 486 /** 487 * @} 488 */ 489 490 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 491 * @{ 492 */ 493 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ 494 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ 495 /** 496 * @} 497 */ 498 499 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 500 * @{ 501 */ 502 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ 503 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ 504 /** 505 * @} 506 */ 507 508 /** 509 * @} 510 */ 511 /* End of exported constants -------------------------------------------------*/ 512 513 /* Exported macros -----------------------------------------------------------*/ 514 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 515 * @{ 516 */ 517 518 /** @brief Reset DFSDM channel handle state. 519 * @param __HANDLE__ DFSDM channel handle. 520 * @retval None 521 */ 522 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 523 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 524 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 525 (__HANDLE__)->MspInitCallback = NULL; \ 526 (__HANDLE__)->MspDeInitCallback = NULL; \ 527 } while(0) 528 #else 529 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 530 #endif 531 532 /** @brief Reset DFSDM filter handle state. 533 * @param __HANDLE__ DFSDM filter handle. 534 * @retval None 535 */ 536 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 537 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 538 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 539 (__HANDLE__)->MspInitCallback = NULL; \ 540 (__HANDLE__)->MspDeInitCallback = NULL; \ 541 } while(0) 542 #else 543 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 544 #endif 545 546 /** 547 * @} 548 */ 549 /* End of exported macros ----------------------------------------------------*/ 550 551 /* Include DFSDM HAL Extension module */ 552 #include "stm32mp1xx_hal_dfsdm_ex.h" 553 554 /* Exported functions --------------------------------------------------------*/ 555 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 556 * @{ 557 */ 558 559 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 560 * @{ 561 */ 562 /* Channel initialization and de-initialization functions *********************/ 563 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 564 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 565 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 566 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 567 568 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 569 /* Channel callbacks register/unregister functions ****************************/ 570 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 571 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 572 pDFSDM_Channel_CallbackTypeDef pCallback); 573 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 574 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 575 #endif 576 /** 577 * @} 578 */ 579 580 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 581 * @{ 582 */ 583 /* Channel operation functions ************************************************/ 584 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 585 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 586 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 587 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 588 589 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 590 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 591 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 592 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 593 594 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 595 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 596 597 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 598 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 599 600 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 601 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 602 /** 603 * @} 604 */ 605 606 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 607 * @{ 608 */ 609 /* Channel state function *****************************************************/ 610 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 611 /** 612 * @} 613 */ 614 615 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 616 * @{ 617 */ 618 /* Filter initialization and de-initialization functions *********************/ 619 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 620 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 621 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 622 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 623 624 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 625 /* Filter callbacks register/unregister functions ****************************/ 626 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 627 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 628 pDFSDM_Filter_CallbackTypeDef pCallback); 629 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 630 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 631 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 632 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 633 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 634 #endif 635 /** 636 * @} 637 */ 638 639 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 640 * @{ 641 */ 642 /* Filter control functions *********************/ 643 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 644 uint32_t Channel, 645 uint32_t ContinuousMode); 646 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 647 uint32_t Channel); 648 /** 649 * @} 650 */ 651 652 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 653 * @{ 654 */ 655 /* Filter operation functions *********************/ 656 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 657 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 658 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 659 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 660 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 661 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 662 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 663 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 664 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 665 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 666 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 667 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 668 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 669 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 670 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 671 DFSDM_Filter_AwdParamTypeDef* awdParam); 672 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 673 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 674 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 675 676 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 677 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 678 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 679 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 680 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 681 682 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 683 684 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 685 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 686 687 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 688 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 689 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 690 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 691 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 692 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 693 /** 694 * @} 695 */ 696 697 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 698 * @{ 699 */ 700 /* Filter state functions *****************************************************/ 701 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 702 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 703 /** 704 * @} 705 */ 706 707 /** 708 * @} 709 */ 710 /* End of exported functions -------------------------------------------------*/ 711 712 /* Private macros ------------------------------------------------------------*/ 713 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 714 * @{ 715 */ 716 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 717 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 718 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) 719 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 720 ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ 721 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 722 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 723 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 724 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 725 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 726 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 727 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 728 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 729 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 730 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 731 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 732 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 733 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 734 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 735 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 736 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 737 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 738 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 739 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) 740 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 741 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) 742 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) 743 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 744 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 745 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 746 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 747 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 748 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 749 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 750 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 751 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 752 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 753 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 754 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 755 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 756 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 757 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 758 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ 759 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \ 760 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \ 761 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT)) 762 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 763 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 764 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 765 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 766 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 767 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 768 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 769 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 770 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 771 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) 772 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) 773 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 774 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 775 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 776 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 777 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 778 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 779 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 780 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 781 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 782 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 783 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 784 ((CHANNEL) == DFSDM_CHANNEL_7)) 785 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) 786 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 787 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 788 /** 789 * @} 790 */ 791 /* End of private macros -----------------------------------------------------*/ 792 793 /** 794 * @} 795 */ 796 797 /** 798 * @} 799 */ 800 801 #ifdef __cplusplus 802 } 803 #endif 804 805 #endif /* STM32MP1xx_HAL_DFSDM_H */ 806 807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 808