1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32MP1xx_HAL_DMA_H 22 #define __STM32MP1xx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 /** @addtogroup STM32MP1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @brief DMA Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief DMA Configuration Structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Request; /*!< Specifies the request selected for the specified stream. 52 This parameter can be a value of @ref DMA_Request_selection */ 53 54 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 55 from memory to memory or from peripheral to memory. 56 This parameter can be a value of @ref DMA_Data_transfer_direction */ 57 58 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 59 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 60 61 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 62 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 63 64 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 65 This parameter can be a value of @ref DMA_Peripheral_data_size */ 66 67 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 68 This parameter can be a value of @ref DMA_Memory_data_size */ 69 70 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 71 This parameter can be a value of @ref DMA_mode 72 @note The circular buffer mode cannot be used if the memory-to-memory 73 data transfer is configured on the selected Stream */ 74 75 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 76 This parameter can be a value of @ref DMA_Priority_level */ 77 78 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 79 This parameter can be a value of @ref DMA_FIFO_direct_mode 80 @note The Direct mode (FIFO mode disabled) cannot be used if the 81 memory-to-memory data transfer is configured on the selected stream */ 82 83 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 84 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 85 86 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 87 It specifies the amount of data to be transferred in a single non interruptible 88 transaction. 89 This parameter can be a value of @ref DMA_Memory_burst 90 @note The burst mode is possible only if the address Increment mode is enabled. */ 91 92 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 93 It specifies the amount of data to be transferred in a single non interruptible 94 transaction. 95 This parameter can be a value of @ref DMA_Peripheral_burst 96 @note The burst mode is possible only if the address Increment mode is enabled. */ 97 } DMA_InitTypeDef; 98 99 /** 100 * @brief HAL DMA State structures definition 101 */ 102 typedef enum 103 { 104 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 105 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 106 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 107 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 108 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 109 } HAL_DMA_StateTypeDef; 110 111 /** 112 * @brief HAL DMA Transfer complete level structure definition 113 */ 114 typedef enum 115 { 116 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 117 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ 118 } HAL_DMA_LevelCompleteTypeDef; 119 120 /** 121 * @brief HAL DMA Callbacks IDs structure definition 122 */ 123 typedef enum 124 { 125 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 126 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 127 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 128 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 129 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 130 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 131 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 132 } HAL_DMA_CallbackIDTypeDef; 133 134 /** 135 * @brief DMA handle Structure definition 136 */ 137 typedef struct __DMA_HandleTypeDef 138 { 139 DMA_Stream_TypeDef *Instance; /*!< Register base address */ 140 141 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 142 143 HAL_LockTypeDef Lock; /*!< DMA locking object */ 144 145 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 146 147 void *Parent; /*!< Parent object state */ 148 149 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 150 151 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 152 153 void (* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete Memory1 callback */ 154 155 void (* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Half complete Memory1 callback */ 156 157 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 158 159 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ 160 161 __IO uint32_t ErrorCode; /*!< DMA Error code */ 162 163 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 164 165 uint32_t StreamIndex; /*!< DMA Stream Index */ 166 167 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */ 168 169 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 170 171 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 172 173 174 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 175 176 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */ 177 178 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 179 180 } DMA_HandleTypeDef; 181 182 /** 183 * @} 184 */ 185 186 187 /* Exported constants --------------------------------------------------------*/ 188 189 /** @defgroup DMA_Exported_Constants DMA Exported Constants 190 * @brief DMA Exported constants 191 * @{ 192 */ 193 194 /** @defgroup DMA_Error_Code DMA Error Code 195 * @brief DMA Error Code 196 * @{ 197 */ 198 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ 199 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ 200 #define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */ 201 #define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */ 202 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ 203 #define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */ 204 #define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */ 205 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ 206 #define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */ 207 #define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */ 208 #define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */ 209 210 /** 211 * @} 212 */ 213 214 /** @defgroup DMA_Request_selection DMA Request selection 215 * @brief DMA Request selection 216 * @{ 217 */ 218 /* D2 Domain : DMAMUX1 requests */ 219 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 220 221 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 222 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 223 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 224 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 225 #define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ 226 #define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ 227 #define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ 228 #define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ 229 230 #define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */ 231 #define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */ 232 233 #define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ 234 #define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ 235 #define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ 236 #define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ 237 #define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ 238 #define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ 239 #define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ 240 241 #define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ 242 #define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ 243 #define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ 244 #define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ 245 #define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ 246 247 #define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ 248 #define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ 249 #define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ 250 #define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ 251 #define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ 252 #define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ 253 254 #define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ 255 #define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ 256 #define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ 257 #define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ 258 259 #define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ 260 #define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ 261 #define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ 262 #define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ 263 264 #define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ 265 #define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ 266 #define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ 267 #define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ 268 269 #define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ 270 #define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ 271 #define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ 272 #define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ 273 274 #define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ 275 #define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ 276 #define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ 277 #define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ 278 #define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ 279 #define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ 280 #define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ 281 282 #define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ 283 #define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ 284 #define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ 285 #define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ 286 #define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ 287 #define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ 288 289 #define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ 290 #define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ 291 292 #define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ 293 #define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ 294 #define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ 295 #define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ 296 297 #define DMA_REQUEST_DAC1 67U /*!< DMAMUX1 DAC1 request */ 298 #define DMA_REQUEST_DAC2 68U /*!< DMAMUX1 DAC2 request */ 299 300 #define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ 301 #define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ 302 303 #define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ 304 #define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ 305 306 #define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ 307 #define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ 308 309 #define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ 310 311 #if defined(CRYP2) 312 #define DMA_REQUEST_CRYP2_IN 76U /*!< DMAMUX1 CRYP2 IN request */ 313 #define DMA_REQUEST_CRYP2_OUT 77U /*!< DMAMUX1 CRYP2 OUT request */ 314 #endif 315 316 #define DMA_REQUEST_HASH2_IN 78U /*!< DMAMUX1 HASH2 IN request */ 317 318 #define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ 319 #define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ 320 #define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ 321 #define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ 322 323 #define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ 324 #define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ 325 #define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ 326 #define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ 327 328 #define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ 329 #define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ 330 #define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ 331 #define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ 332 333 #define DMA_REQUEST_DFSDM1_FLT4 91U /*!< DMAMUX1 DFSDM1 Filter4 request */ 334 #define DMA_REQUEST_DFSDM1_FLT5 92U /*!< DMAMUX1 DFSDM1 Filter5 request */ 335 336 #define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ 337 #define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ 338 339 #define DMA_REQUEST_SAI4_A 99U /*!< DMAMUX1 SAI4 A request */ 340 #define DMA_REQUEST_SAI4_B 100U /*!< DMAMUX1 SAI4 B request */ 341 342 #define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ 343 #define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ 344 #define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ 345 #define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */ 346 347 #define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ 348 #define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ 349 #define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ 350 #define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ 351 352 #define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ 353 #define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ 354 355 #define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ 356 #define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ 357 358 #define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ 359 #define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ 360 361 #define DMA_REQUEST_I2C5_RX 115U /*!< DMAMUX1 I2C5 RX request */ 362 #define DMA_REQUEST_I2C5_TX 116U /*!< DMAMUX1 I2C5 TX request */ 363 364 /** 365 * @} 366 */ 367 368 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 369 * @brief DMA data transfer direction 370 * @{ 371 */ 372 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ 373 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 374 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 375 /** 376 * @} 377 */ 378 379 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 380 * @brief DMA peripheral incremented mode 381 * @{ 382 */ 383 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 384 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ 385 /** 386 * @} 387 */ 388 389 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 390 * @brief DMA memory incremented mode 391 * @{ 392 */ 393 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 394 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ 395 /** 396 * @} 397 */ 398 399 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 400 * @brief DMA peripheral data size 401 * @{ 402 */ 403 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ 404 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 405 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 406 /** 407 * @} 408 */ 409 410 /** @defgroup DMA_Memory_data_size DMA Memory data size 411 * @brief DMA memory data size 412 * @{ 413 */ 414 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ 415 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 416 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup DMA_mode DMA mode 422 * @brief DMA mode 423 * @{ 424 */ 425 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 426 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 427 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup DMA_Priority_level DMA Priority level 433 * @brief DMA priority levels 434 * @{ 435 */ 436 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ 437 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 438 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 439 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 440 /** 441 * @} 442 */ 443 444 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 445 * @brief DMA FIFO direct mode 446 * @{ 447 */ 448 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ 449 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 450 /** 451 * @} 452 */ 453 454 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 455 * @brief DMA FIFO level 456 * @{ 457 */ 458 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ 459 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 460 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 461 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 462 /** 463 * @} 464 */ 465 466 /** @defgroup DMA_Memory_burst DMA Memory burst 467 * @brief DMA memory burst 468 * @{ 469 */ 470 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) 471 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 472 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 473 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 474 /** 475 * @} 476 */ 477 478 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 479 * @brief DMA peripheral burst 480 * @{ 481 */ 482 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) 483 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 484 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 485 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 486 /** 487 * @} 488 */ 489 490 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 491 * @brief DMA interrupts definition 492 * @{ 493 */ 494 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 495 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 496 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 497 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 498 #define DMA_IT_FE ((uint32_t)0x00000080U) 499 /** 500 * @} 501 */ 502 503 /** @defgroup DMA_flag_definitions DMA flag definitions 504 * @brief DMA flag definitions 505 * @{ 506 */ 507 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) 508 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) 509 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) 510 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) 511 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) 512 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) 513 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) 514 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) 515 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) 516 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) 517 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) 518 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) 519 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) 520 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) 521 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) 522 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) 523 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) 524 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) 525 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) 526 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) 527 /** 528 * @} 529 */ 530 531 532 /** 533 * @} 534 */ 535 536 /* Exported macro ------------------------------------------------------------*/ 537 /** @defgroup DMA_Exported_Macros DMA Exported Macros 538 * @{ 539 */ 540 541 /** @brief Reset DMA handle state 542 * @param __HANDLE__: specifies the DMA handle. 543 * @retval None 544 */ 545 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 546 547 /** 548 * @brief Return the current DMA Stream FIFO filled level. 549 * @param __HANDLE__: DMA handle 550 * @retval The FIFO filling state. 551 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 552 * and not empty. 553 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 554 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 555 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 556 * - DMA_FIFOStatus_Empty: when FIFO is empty 557 * - DMA_FIFOStatus_Full: when FIFO is full 558 */ 559 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) 560 561 /** 562 * @brief Enable the specified DMA Stream. 563 * @param __HANDLE__: DMA handle 564 * @retval None 565 */ 566 #define __HAL_DMA_ENABLE(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) 567 568 /** 569 * @brief Disable the specified DMA Stream. 570 * @param __HANDLE__: DMA handle 571 * @retval None 572 */ 573 #define __HAL_DMA_DISABLE(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) 574 575 /* Interrupt & Flag management */ 576 577 /** 578 * @brief Return the current DMA Stream transfer complete flag. 579 * @param __HANDLE__: DMA handle 580 * @retval The specified transfer complete flag index. 581 */ 582 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 583 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 584 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 585 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 586 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 587 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 588 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 589 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 590 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 591 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 592 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 593 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 594 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 595 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ 596 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ 598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ 599 (uint32_t)0x00000000) 600 601 /** 602 * @brief Return the current DMA Stream half transfer complete flag. 603 * @param __HANDLE__: DMA handle 604 * @retval The specified half transfer complete flag index. 605 */ 606 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 607 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 608 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 609 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 610 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 611 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 612 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 613 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 614 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 615 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 616 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 617 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 618 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ 620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ 621 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ 622 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ 623 (uint32_t)0x00000000) 624 625 /** 626 * @brief Return the current DMA Stream transfer error flag. 627 * @param __HANDLE__: DMA handle 628 * @retval The specified transfer error flag index. 629 */ 630 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 631 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 632 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 633 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 634 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 635 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 636 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 637 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 641 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 642 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 643 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ 644 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ 645 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ 646 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ 647 (uint32_t)0x00000000) 648 649 /** 650 * @brief Return the current DMA Stream FIFO error flag. 651 * @param __HANDLE__: DMA handle 652 * @retval The specified FIFO error flag index. 653 */ 654 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 655 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 658 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 659 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 660 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 661 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 662 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 663 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 664 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 665 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 666 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 667 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\ 668 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\ 669 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\ 670 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\ 671 (uint32_t)0x00000000) 672 673 /** 674 * @brief Return the current DMA Stream direct mode error flag. 675 * @param __HANDLE__: DMA handle 676 * @retval The specified direct mode error flag index. 677 */ 678 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 679 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 680 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 681 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 682 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 683 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 684 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 685 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 686 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 687 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 688 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 689 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 690 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 691 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\ 692 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\ 693 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\ 694 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\ 695 (uint32_t)0x00000000) 696 697 698 /** 699 * @brief Get the DMA Stream pending flags. 700 * @param __HANDLE__: DMA handle 701 * @param __FLAG__: Get the specified flag. 702 * This parameter can be any combination of the following values: 703 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 704 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 705 * @arg DMA_FLAG_TEIFx: Transfer error flag. 706 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 707 * @arg DMA_FLAG_FEIFx: FIFO error flag. 708 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 709 * @retval The state of FLAG (SET or RESET). 710 */ 711 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 712 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 713 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 714 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 715 716 /** 717 * @brief Clear the DMA Stream pending flags. 718 * @param __HANDLE__: DMA handle 719 * @param __FLAG__: specifies the flag to clear. 720 * This parameter can be any combination of the following values: 721 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 722 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 723 * @arg DMA_FLAG_TEIFx: Transfer error flag. 724 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 725 * @arg DMA_FLAG_FEIFx: FIFO error flag. 726 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 727 * @retval None 728 */ 729 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 730 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 731 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 732 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 733 734 /** 735 * @brief Enable the specified DMA Stream interrupts. 736 * @param __HANDLE__: DMA handle 737 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 738 * This parameter can be one of the following values: 739 * @arg DMA_IT_TC: Transfer complete interrupt mask. 740 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 741 * @arg DMA_IT_TE: Transfer error interrupt mask. 742 * @arg DMA_IT_FE: FIFO error interrupt mask. 743 * @arg DMA_IT_DME: Direct mode error interrupt. 744 * @retval None 745 */ 746 747 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 748 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__))) 749 750 /** 751 * @brief Disable the specified DMA Stream interrupts. 752 * @param __HANDLE__: DMA handle 753 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 754 * This parameter can be one of the following values: 755 * @arg DMA_IT_TC: Transfer complete interrupt mask. 756 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 757 * @arg DMA_IT_TE: Transfer error interrupt mask. 758 * @arg DMA_IT_FE: FIFO error interrupt mask. 759 * @arg DMA_IT_DME: Direct mode error interrupt. 760 * @retval None 761 */ 762 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 763 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__))) 764 765 /** 766 * @brief Check whether the specified DMA Stream interrupt is enabled or not. 767 * @param __HANDLE__: DMA handle 768 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 769 * This parameter can be one of the following values: 770 * @arg DMA_IT_TC: Transfer complete interrupt mask. 771 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 772 * @arg DMA_IT_TE: Transfer error interrupt mask. 773 * @arg DMA_IT_FE: FIFO error interrupt mask. 774 * @arg DMA_IT_DME: Direct mode error interrupt. 775 * @retval The state of DMA_IT. 776 */ 777 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 778 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \ 779 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__))) 780 781 /** 782 * @brief Writes the number of data units to be transferred on the DMA Stream. 783 * @param __HANDLE__: DMA handle 784 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) 785 * Number of data items depends only on the Peripheral data format. 786 * 787 * @note If Peripheral data format is Bytes: number of data units is equal 788 * to total number of bytes to be transferred. 789 * 790 * @note If Peripheral data format is Half-Word: number of data units is 791 * equal to total number of bytes to be transferred / 2. 792 * 793 * @note If Peripheral data format is Word: number of data units is equal 794 * to total number of bytes to be transferred / 4. 795 * 796 * @retval The number of remaining data units in the current DMAy Streamx transfer. 797 */ 798 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) 799 800 /** 801 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 802 * @param __HANDLE__: DMA handle 803 * 804 * @retval The number of remaining data units in the current DMA Stream transfer. 805 */ 806 #define __HAL_DMA_GET_COUNTER(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) 807 /** 808 * @} 809 */ 810 811 /* Include DMA HAL Extension module */ 812 #include "stm32mp1xx_hal_dma_ex.h" 813 814 /* Exported functions --------------------------------------------------------*/ 815 816 /** @defgroup DMA_Exported_Functions DMA Exported Functions 817 * @brief DMA Exported functions 818 * @{ 819 */ 820 821 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 822 * @brief Initialization and de-initialization functions 823 * @{ 824 */ 825 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 826 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 827 /** 828 * @} 829 */ 830 831 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 832 * @brief I/O operation functions 833 * @{ 834 */ 835 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 836 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 837 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 838 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 839 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 840 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 841 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 842 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 843 844 /** 845 * @} 846 */ 847 848 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 849 * @brief Peripheral State functions 850 * @{ 851 */ 852 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 853 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 854 /** 855 * @} 856 */ 857 /** 858 * @} 859 */ 860 /* Private Constants -------------------------------------------------------------*/ 861 /** @defgroup DMA_Private_Constants DMA Private Constants 862 * @brief DMA private defines and constants 863 * @{ 864 */ 865 /** 866 * @} 867 */ 868 869 /* Private macros ------------------------------------------------------------*/ 870 /** @defgroup DMA_Private_Macros DMA Private Macros 871 * @brief DMA private macros 872 * @{ 873 */ 874 #define IS_DMA_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_I2C5_TX) 875 876 877 #define IS_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7))) 878 879 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 880 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 881 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 882 883 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 884 885 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 886 ((STATE) == DMA_PINC_DISABLE)) 887 888 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 889 ((STATE) == DMA_MINC_DISABLE)) 890 891 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 892 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 893 ((SIZE) == DMA_PDATAALIGN_WORD)) 894 895 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 896 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 897 ((SIZE) == DMA_MDATAALIGN_WORD )) 898 899 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 900 ((MODE) == DMA_CIRCULAR) || \ 901 ((MODE) == DMA_PFCTRL)) 902 903 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 904 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 905 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 906 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 907 908 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 909 ((STATE) == DMA_FIFOMODE_ENABLE)) 910 911 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 912 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 913 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 914 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 915 916 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 917 ((BURST) == DMA_MBURST_INC4) || \ 918 ((BURST) == DMA_MBURST_INC8) || \ 919 ((BURST) == DMA_MBURST_INC16)) 920 921 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 922 ((BURST) == DMA_PBURST_INC4) || \ 923 ((BURST) == DMA_PBURST_INC8) || \ 924 ((BURST) == DMA_PBURST_INC16)) 925 /** 926 * @} 927 */ 928 929 /* Private functions ---------------------------------------------------------*/ 930 /** @defgroup DMA_Private_Functions DMA Private Functions 931 * @brief DMA private functions 932 * @{ 933 */ 934 /** 935 * @} 936 */ 937 938 /** 939 * @} 940 */ 941 942 /** 943 * @} 944 */ 945 946 #ifdef __cplusplus 947 } 948 #endif 949 950 #endif /* __STM32MP1xx_HAL_DMA_H */ 951 952 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 953