1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_qspi.h 4 * @author MCD Application Team 5 * @brief Header file of QSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32MP1xx_HAL_QSPI_H 22 #define STM32MP1xx_HAL_QSPI_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 #include "stm32mp1xx_hal_mdma.h" 31 32 #if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) 33 34 /** @addtogroup STM32MP1xx_HAL_Driver 35 * @{ 36 */ 37 38 /** @addtogroup QSPI 39 * @{ 40 */ 41 42 /* Exported types ------------------------------------------------------------*/ 43 /** @defgroup QSPI_Exported_Types QSPI Exported Types 44 * @{ 45 */ 46 47 /** 48 * @brief QSPI Init structure definition 49 */ 50 typedef struct 51 { 52 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 53 This parameter can be a number between 0 and 255 */ 54 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 55 This parameter can be a value between 1 and 32 */ 56 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 57 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 58 This parameter can be a value of @ref QSPI_SampleShifting */ 59 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 60 required to address the flash memory. The flash capacity can be up to 4GB 61 (addressed using 32 bits) in indirect mode, but the addressable space in 62 memory-mapped mode is limited to 256MB 63 This parameter can be a number between 0 and 31 */ 64 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 65 of clock cycles which the chip select must remain high between commands. 66 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 67 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 68 This parameter can be a value of @ref QSPI_ClockMode */ 69 uint32_t FlashID; /* Specifies the Flash which will be used, 70 This parameter can be a value of @ref QSPI_Flash_Select */ 71 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 72 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 73 }QSPI_InitTypeDef; 74 75 /** 76 * @brief HAL QSPI State structures definition 77 */ 78 typedef enum 79 { 80 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 81 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 82 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 83 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 84 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 85 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 86 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 87 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 88 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 89 }HAL_QSPI_StateTypeDef; 90 91 /** 92 * @brief QSPI Handle Structure definition 93 */ 94 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 95 typedef struct __QSPI_HandleTypeDef 96 #else 97 typedef struct 98 #endif 99 { 100 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 101 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 102 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 103 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 104 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 105 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 106 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 107 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 108 MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ 109 __IO HAL_LockTypeDef Lock; /* Locking object */ 110 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 111 __IO uint32_t ErrorCode; /* QSPI Error code */ 112 uint32_t Timeout; /* Timeout for the QSPI memory access */ 113 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 114 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 115 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 116 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 117 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 118 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 119 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 120 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 121 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 122 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 123 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 124 125 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 126 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 127 #endif 128 }QSPI_HandleTypeDef; 129 130 /** 131 * @brief QSPI Command structure definition 132 */ 133 typedef struct 134 { 135 uint32_t Instruction; /* Specifies the Instruction to be sent 136 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 137 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 138 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 139 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 140 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 141 uint32_t AddressSize; /* Specifies the Address Size 142 This parameter can be a value of @ref QSPI_AddressSize */ 143 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 144 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 145 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 146 This parameter can be a number between 0 and 31 */ 147 uint32_t InstructionMode; /* Specifies the Instruction Mode 148 This parameter can be a value of @ref QSPI_InstructionMode */ 149 uint32_t AddressMode; /* Specifies the Address Mode 150 This parameter can be a value of @ref QSPI_AddressMode */ 151 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 152 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 153 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 154 This parameter can be a value of @ref QSPI_DataMode */ 155 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 156 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 157 until end of memory)*/ 158 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 159 This parameter can be a value of @ref QSPI_DdrMode */ 160 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 161 output by one half of system clock in DDR mode. 162 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 163 uint32_t SIOOMode; /* Specifies the send instruction only once mode 164 This parameter can be a value of @ref QSPI_SIOOMode */ 165 }QSPI_CommandTypeDef; 166 167 /** 168 * @brief QSPI Auto Polling mode configuration structure definition 169 */ 170 typedef struct 171 { 172 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 173 This parameter can be any value between 0 and 0xFFFFFFFF */ 174 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 175 This parameter can be any value between 0 and 0xFFFFFFFF */ 176 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 177 This parameter can be any value between 0 and 0xFFFF */ 178 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 179 This parameter can be any value between 1 and 4 */ 180 uint32_t MatchMode; /* Specifies the method used for determining a match. 181 This parameter can be a value of @ref QSPI_MatchMode */ 182 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 183 This parameter can be a value of @ref QSPI_AutomaticStop */ 184 }QSPI_AutoPollingTypeDef; 185 186 /** 187 * @brief QSPI Memory Mapped mode configuration structure definition 188 */ 189 typedef struct 190 { 191 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 192 This parameter can be any value between 0 and 0xFFFF */ 193 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 194 This parameter can be a value of @ref QSPI_TimeOutActivation */ 195 }QSPI_MemoryMappedTypeDef; 196 197 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 198 /** 199 * @brief HAL QSPI Callback ID enumeration definition 200 */ 201 typedef enum 202 { 203 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 204 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 205 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 206 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 207 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 208 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 209 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ 210 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ 211 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 212 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 213 214 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 215 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 216 }HAL_QSPI_CallbackIDTypeDef; 217 218 /** 219 * @brief HAL QSPI Callback pointer definition 220 */ 221 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 222 #endif 223 /** 224 * @} 225 */ 226 227 /* Exported constants --------------------------------------------------------*/ 228 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 229 * @{ 230 */ 231 232 /** @defgroup QSPI_ErrorCode QSPI Error Code 233 * @{ 234 */ 235 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 236 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 237 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 238 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 239 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 240 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 241 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 242 #endif 243 /** 244 * @} 245 */ 246 247 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 248 * @{ 249 */ 250 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 251 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 252 /** 253 * @} 254 */ 255 256 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 257 * @{ 258 */ 259 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 260 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 261 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 262 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 263 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 264 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 265 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 266 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 267 /** 268 * @} 269 */ 270 271 /** @defgroup QSPI_ClockMode QSPI Clock Mode 272 * @{ 273 */ 274 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 275 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 276 /** 277 * @} 278 */ 279 280 /** @defgroup QSPI_Flash_Select QSPI Flash Select 281 * @{ 282 */ 283 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 284 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 285 /** 286 * @} 287 */ 288 289 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 290 * @{ 291 */ 292 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 293 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 294 /** 295 * @} 296 */ 297 298 /** @defgroup QSPI_AddressSize QSPI Address Size 299 * @{ 300 */ 301 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 302 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 303 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 304 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 305 /** 306 * @} 307 */ 308 309 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 310 * @{ 311 */ 312 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 313 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 314 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 315 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 316 /** 317 * @} 318 */ 319 320 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 321 * @{ 322 */ 323 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 324 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 325 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 326 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 327 /** 328 * @} 329 */ 330 331 /** @defgroup QSPI_AddressMode QSPI Address Mode 332 * @{ 333 */ 334 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 335 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 336 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 337 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 338 /** 339 * @} 340 */ 341 342 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 343 * @{ 344 */ 345 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 346 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 347 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 348 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 349 /** 350 * @} 351 */ 352 353 /** @defgroup QSPI_DataMode QSPI Data Mode 354 * @{ 355 */ 356 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 357 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 358 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 359 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 360 /** 361 * @} 362 */ 363 364 /** @defgroup QSPI_DdrMode QSPI DDR Mode 365 * @{ 366 */ 367 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 368 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 369 /** 370 * @} 371 */ 372 373 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 374 * @{ 375 */ 376 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 377 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 378 /** 379 * @} 380 */ 381 382 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 383 * @{ 384 */ 385 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 386 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 387 /** 388 * @} 389 */ 390 391 /** @defgroup QSPI_MatchMode QSPI Match Mode 392 * @{ 393 */ 394 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 395 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 396 /** 397 * @} 398 */ 399 400 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 401 * @{ 402 */ 403 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 404 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 405 /** 406 * @} 407 */ 408 409 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 410 * @{ 411 */ 412 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 413 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 414 /** 415 * @} 416 */ 417 418 /** @defgroup QSPI_Flags QSPI Flags 419 * @{ 420 */ 421 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 422 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 423 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 424 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 425 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 426 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 427 /** 428 * @} 429 */ 430 431 /** @defgroup QSPI_Interrupts QSPI Interrupts 432 * @{ 433 */ 434 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 435 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 436 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 437 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 438 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 439 /** 440 * @} 441 */ 442 443 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 444 * @brief QSPI Timeout definition 445 * @{ 446 */ 447 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 448 /** 449 * @} 450 */ 451 452 /** 453 * @} 454 */ 455 456 /* Exported macros -----------------------------------------------------------*/ 457 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 458 * @{ 459 */ 460 /** @brief Reset QSPI handle state. 461 * @param __HANDLE__ : QSPI handle. 462 * @retval None 463 */ 464 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 465 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 466 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 467 (__HANDLE__)->MspInitCallback = NULL; \ 468 (__HANDLE__)->MspDeInitCallback = NULL; \ 469 } while(0) 470 #else 471 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 472 #endif 473 474 /** @brief Enable the QSPI peripheral. 475 * @param __HANDLE__ : specifies the QSPI Handle. 476 * @retval None 477 */ 478 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 479 480 /** @brief Disable the QSPI peripheral. 481 * @param __HANDLE__ : specifies the QSPI Handle. 482 * @retval None 483 */ 484 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 485 486 /** @brief Enable the specified QSPI interrupt. 487 * @param __HANDLE__ : specifies the QSPI Handle. 488 * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. 489 * This parameter can be one of the following values: 490 * @arg QSPI_IT_TO: QSPI Timeout interrupt 491 * @arg QSPI_IT_SM: QSPI Status match interrupt 492 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 493 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 494 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 495 * @retval None 496 */ 497 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 498 499 500 /** @brief Disable the specified QSPI interrupt. 501 * @param __HANDLE__ : specifies the QSPI Handle. 502 * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. 503 * This parameter can be one of the following values: 504 * @arg QSPI_IT_TO: QSPI Timeout interrupt 505 * @arg QSPI_IT_SM: QSPI Status match interrupt 506 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 507 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 508 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 509 * @retval None 510 */ 511 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 512 513 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 514 * @param __HANDLE__ : specifies the QSPI Handle. 515 * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. 516 * This parameter can be one of the following values: 517 * @arg QSPI_IT_TO: QSPI Timeout interrupt 518 * @arg QSPI_IT_SM: QSPI Status match interrupt 519 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 520 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 521 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 522 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 523 */ 524 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 525 526 /** 527 * @brief Check whether the selected QSPI flag is set or not. 528 * @param __HANDLE__ : specifies the QSPI Handle. 529 * @param __FLAG__ : specifies the QSPI flag to check. 530 * This parameter can be one of the following values: 531 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 532 * @arg QSPI_FLAG_TO: QSPI Timeout flag 533 * @arg QSPI_FLAG_SM: QSPI Status match flag 534 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 535 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 536 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 537 * @retval None 538 */ 539 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 540 541 /** @brief Clears the specified QSPI's flag status. 542 * @param __HANDLE__ : specifies the QSPI Handle. 543 * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set 544 * This parameter can be one of the following values: 545 * @arg QSPI_FLAG_TO: QSPI Timeout flag 546 * @arg QSPI_FLAG_SM: QSPI Status match flag 547 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 548 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 549 * @retval None 550 */ 551 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 552 /** 553 * @} 554 */ 555 556 /* Exported functions --------------------------------------------------------*/ 557 /** @addtogroup QSPI_Exported_Functions 558 * @{ 559 */ 560 561 /** @addtogroup QSPI_Exported_Functions_Group1 562 * @{ 563 */ 564 /* Initialization/de-initialization functions ********************************/ 565 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 566 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 567 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 568 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 569 /** 570 * @} 571 */ 572 573 /** @addtogroup QSPI_Exported_Functions_Group2 574 * @{ 575 */ 576 /* IO operation functions *****************************************************/ 577 /* QSPI IRQ handler method */ 578 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 579 580 /* QSPI indirect mode */ 581 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 582 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 583 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 584 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 585 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 586 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 587 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 588 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 589 590 /* QSPI status flag polling mode */ 591 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 592 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 593 594 /* QSPI memory-mapped mode */ 595 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 596 597 /* Callback functions in non-blocking modes ***********************************/ 598 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 599 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 600 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 601 602 /* QSPI indirect mode */ 603 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 604 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 605 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 606 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 607 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 608 609 /* QSPI status flag polling mode */ 610 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 611 612 /* QSPI memory-mapped mode */ 613 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 614 615 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 616 /* QSPI callback registering/unregistering */ 617 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 618 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 619 #endif 620 /** 621 * @} 622 */ 623 624 /** @addtogroup QSPI_Exported_Functions_Group3 625 * @{ 626 */ 627 /* Peripheral Control and State functions ************************************/ 628 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 629 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 630 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 631 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 632 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 633 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 634 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 635 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 636 /** 637 * @} 638 */ 639 640 /** 641 * @} 642 */ 643 /* End of exported functions -------------------------------------------------*/ 644 645 /* Private macros ------------------------------------------------------------*/ 646 /** @defgroup QSPI_Private_Macros QSPI Private Macros 647 * @{ 648 */ 649 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 650 651 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) 652 653 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 654 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 655 656 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 657 658 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 659 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 660 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 661 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 662 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 663 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 664 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 665 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 666 667 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 668 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 669 670 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 671 ((FLASH_ID) == QSPI_FLASH_ID_2)) 672 673 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 674 ((MODE) == QSPI_DUALFLASH_DISABLE)) 675 676 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 677 678 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 679 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 680 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 681 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 682 683 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 684 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 685 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 686 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 687 688 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 689 690 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 691 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 692 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 693 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 694 695 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 696 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 697 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 698 ((MODE) == QSPI_ADDRESS_4_LINES)) 699 700 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 701 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 702 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 703 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 704 705 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 706 ((MODE) == QSPI_DATA_1_LINE) || \ 707 ((MODE) == QSPI_DATA_2_LINES) || \ 708 ((MODE) == QSPI_DATA_4_LINES)) 709 710 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 711 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 712 713 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 714 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 715 716 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 717 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 718 719 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 720 721 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 722 723 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 724 ((MODE) == QSPI_MATCH_MODE_OR)) 725 726 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 727 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 728 729 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 730 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 731 732 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 733 /** 734 * @} 735 */ 736 /* End of private macros -----------------------------------------------------*/ 737 738 /** 739 * @} 740 */ 741 742 /** 743 * @} 744 */ 745 746 #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ 747 748 #ifdef __cplusplus 749 } 750 #endif 751 752 #endif /* STM32MP1xx_HAL_QSPI_H */ 753 754 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 755