1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32MP1xx_HAL_RCC_H 22 #define __STM32MP1xx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 /** @addtogroup STM32MP1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup RCC_Exported_Types RCC Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief RCC PLL configuration structure definition 47 */ 48 typedef struct 49 { 50 uint32_t PLLState; /*!< The new state of the PLL. 51 This parameter can be a value of @ref RCC_PLL_Config */ 52 53 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 54 This parameter must be a value of @ref RCC_PLL12_Clock_Source */ 55 56 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 57 This parameter must be a number between 1 and 64 */ 58 59 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock 60 This parameter must be a number between: 61 Integer mode: 25 and 100 for PLL1600 (PLL1 and PLL2), 25 and 200 for PLL800 62 Fractional mode: 4 and 512 (PLL1600 and PLL800) */ 63 64 uint32_t PLLP; /*!< PLLP: Division factor ck_pll1_p 65 This parameter must be a number between 1 and 128 */ 66 67 uint32_t PLLQ; /*!< PLLQ: Division factor ck_pll1_q 68 This parameter must be a number between 1 and 128 */ 69 70 uint32_t PLLR; /*!< PLLR: Division for ck_pll1_r 71 This parameter must be a number between 1 and 128 */ 72 73 uint32_t PLLRGE; /*!< PLLRGE: PLL input frequency range for PLL3 and PLL4 74 This parameter must be a value of @ref RCC_PLL3_IF_Range and RCC_PLL4_IF_Range */ 75 76 uint32_t PLLFRACV; /*!< PLLFRACV: Fractional Part Of The Multiplication Factor for PLL1 VCO 77 It should be a value between 0 and 8191 ((2^13)-1) */ 78 79 uint32_t PLLMODE; /*!< PLLMODE: PLL mode used 80 This parameter must be a value of @ref RCC_PLL_Mode */ 81 82 uint32_t MOD_PER; /*!< MOD_PER: Modulation Period Adjustment 83 This parameter must have a value contained on @ref RCC_MOD_PER */ 84 85 uint32_t RPDFN_DIS; /*!< RPDFN_DIS: Dithering RPDF noise control 86 This parameter must be a value of @ref RCC_RPDFN_DIS*/ 87 88 uint32_t TPDFN_DIS; /*!< TPDFN_DIS: Dithering TPDF noise control 89 This parameter must be a value of @ref RCC_TPDFN_DIS*/ 90 91 uint32_t SSCG_MODE; /*!< SSCG_MODE: Spread spectrum clock generator mode 92 This parameter must be a value of @ref RCC_SSCG_MODE*/ 93 94 uint32_t INC_STEP; /*!< INC_STEP: Modulation Depth Adjustment 95 This parameter must have a value contained on @ref RCC_INC_STEP */ 96 97 } RCC_PLLInitTypeDef; 98 99 100 101 102 typedef struct 103 { 104 uint32_t PLL1_P_Frequency; 105 uint32_t PLL1_Q_Frequency; 106 uint32_t PLL1_R_Frequency; 107 } PLL1_ClocksTypeDef; 108 109 /** 110 * @brief RCC PLL2 Clocks structure definition => [FCH] used in UART set_config use case 111 */ 112 typedef struct 113 { 114 uint32_t PLL2_P_Frequency; 115 uint32_t PLL2_Q_Frequency; 116 uint32_t PLL2_R_Frequency; 117 } PLL2_ClocksTypeDef; 118 119 /** 120 * @brief RCC PLL3 Clocks structure definition => [FCH] used in UART set_config use case 121 */ 122 typedef struct 123 { 124 uint32_t PLL3_P_Frequency; 125 uint32_t PLL3_Q_Frequency; 126 uint32_t PLL3_R_Frequency; 127 } PLL3_ClocksTypeDef; 128 129 130 typedef struct 131 { 132 uint32_t PLL4_P_Frequency; 133 uint32_t PLL4_Q_Frequency; 134 uint32_t PLL4_R_Frequency; 135 } PLL4_ClocksTypeDef; 136 137 /** 138 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition 139 */ 140 typedef struct 141 { 142 143 uint32_t OscillatorType; /*!< The oscillators to be configured. 144 This parameter can be a value of @ref RCC_Oscillator_Type */ 145 146 uint32_t HSEState; /*!< The new state of the HSE. 147 This parameter can be a value of @ref RCC_HSE_Config */ 148 149 uint32_t LSEState; /*!< The new state of the LSE. 150 This parameter can be a value of @ref RCC_LSE_Config */ 151 152 uint32_t HSIState; /*!< The new state of the HSI. 153 This parameter can be a value of @ref RCC_HSI_Config */ 154 155 uint32_t HSICalibrationValue; /*!< The calibration trimming value. 156 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ 157 158 uint32_t HSIDivValue; /*!< The HSI Division value. 159 This parameter must be a value of @ref RCC_HSI_Clock_Prescaler */ 160 161 uint32_t LSIState; /*!< The new state of the LSI. 162 This parameter can be a value of @ref RCC_LSI_Config */ 163 164 uint32_t CSIState; /*!< The new state of the CSI. 165 This parameter can be a value of @ref RCC_CSI_Config */ 166 167 uint32_t CSICalibrationValue; /*!< The calibration trimming value. 168 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 169 170 RCC_PLLInitTypeDef PLL; /*!< PLL1 structure parameters */ 171 172 RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters */ 173 174 RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters */ 175 176 RCC_PLLInitTypeDef PLL4; /*!< PLL4 structure parameters */ 177 178 } RCC_OscInitTypeDef; 179 180 /** 181 * @brief MPU configuration structure definition. 182 */ 183 typedef struct 184 { 185 uint32_t MPU_Clock; 186 uint32_t MPU_Div; 187 } RCC_MPUInitTypeDef; 188 189 /** 190 * @brief AXI configuration structure definition. 191 */ 192 typedef struct 193 { 194 uint32_t AXI_Clock; 195 uint32_t AXI_Div; 196 } RCC_AXISSInitTypeDef; 197 198 199 /** 200 * @brief MCU configuration structure definition. 201 */ 202 typedef struct 203 { 204 uint32_t MCU_Clock; 205 uint32_t MCU_Div; 206 } RCC_MCUInitTypeDef; 207 208 /** 209 * @brief RCC MPU, MCU, AXI, AHB and APB busses clock configuration structure definition. 210 */ 211 typedef struct 212 { 213 uint32_t ClockType; /*!< The clock to be configured. 214 This parameter can be a value of @ref RCC_System_Clock_Type */ 215 216 RCC_MPUInitTypeDef MPUInit; 217 RCC_AXISSInitTypeDef AXISSInit; 218 RCC_MCUInitTypeDef MCUInit; 219 uint32_t APB4_Div; 220 uint32_t APB5_Div; 221 uint32_t APB1_Div; 222 uint32_t APB2_Div; 223 uint32_t APB3_Div; 224 } RCC_ClkInitTypeDef; 225 226 /** 227 * @} 228 */ 229 230 /* Exported constants --------------------------------------------------------*/ 231 232 /** @defgroup RCC_Exported_Constants RCC Exported Constants 233 * @{ 234 */ 235 #define DBP_TIMEOUT_VALUE ((uint32_t)100) 236 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) 237 238 /** @defgroup RCC_Oscillator_Type RCC_Oscillator_Type 239 * @{ 240 */ 241 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) 242 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) 243 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) 244 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) 245 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) 246 #define RCC_OSCILLATORTYPE_CSI ((uint32_t)0x00000010) 247 248 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ 249 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 250 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 251 (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ 252 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 253 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 254 /** 255 * @} 256 */ 257 258 /** @defgroup RCC_System_Clock_Type RCC_System_Clock_Type 259 * @{ 260 */ 261 #define RCC_CLOCKTYPE_NONE ((uint32_t)0x00000000) 262 #define RCC_CLOCKTYPE_MPU ((uint32_t)0x00000001) 263 #define RCC_CLOCKTYPE_ACLK ((uint32_t)0x00000002) 264 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000004) 265 #define RCC_CLOCKTYPE_PCLK4 ((uint32_t)0x00000008) 266 #define RCC_CLOCKTYPE_PCLK5 ((uint32_t)0x00000010) 267 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000020) 268 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000040) 269 #define RCC_CLOCKTYPE_PCLK3 ((uint32_t)0x00000080) 270 271 272 273 #define IS_RCC_CLOCKTYPETYPE(CLOCK) (((CLOCK) == RCC_CLOCKTYPE_NONE) || \ 274 (((CLOCK) & RCC_CLOCKTYPE_MPU) == RCC_CLOCKTYPE_MPU) || \ 275 (((CLOCK) & RCC_CLOCKTYPE_ACLK)== RCC_CLOCKTYPE_ACLK) || \ 276 (((CLOCK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 277 (((CLOCK) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) || \ 278 (((CLOCK) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) || \ 279 (((CLOCK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 280 (((CLOCK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) || \ 281 (((CLOCK) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)) 282 /** 283 * @} 284 */ 285 286 /** @defgroup RCC_HSE_Config RCC_HSE_Config 287 * @{ 288 */ 289 #define RCC_HSE_OFF ((uint32_t)0x00000000) 290 #define RCC_HSE_ON RCC_OCENSETR_HSEON 291 #define RCC_HSE_BYPASS (RCC_OCENSETR_HSEBYP | RCC_OCENSETR_HSEON) 292 #define RCC_HSE_BYPASS_DIG (RCC_OCENSETR_HSEBYP | RCC_OCENSETR_HSEON | RCC_OCENSETR_DIGBYP) 293 294 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 295 ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIG)) 296 /** 297 * @} 298 */ 299 300 /** @defgroup RCC_LSE_Config RCC_LSE_Config 301 * @{ 302 */ 303 #define RCC_LSE_OFF ((uint32_t)0x00000000) 304 #define RCC_LSE_ON RCC_BDCR_LSEON 305 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) 306 #define RCC_LSE_BYPASS_DIG (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON | RCC_BDCR_DIGBYP) 307 308 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 309 ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIG)) 310 /** 311 * @} 312 */ 313 314 /** @defgroup RCC_HSI_Config RCC_HSI_Config 315 * @{ 316 */ 317 #define RCC_HSI_OFF ((uint32_t)0x00000000) 318 #define RCC_HSI_ON RCC_OCENSETR_HSION 319 320 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) 321 /** 322 * @} 323 */ 324 325 /** @defgroup RCC_HSI_Clock_Prescaler RCC_HSI_Clock_Prescaler 326 * @{ 327 */ 328 #define RCC_HSI_DIV1 RCC_HSICFGR_HSIDIV_0 /* Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)*/ 329 #define RCC_HSI_DIV2 RCC_HSICFGR_HSIDIV_1 /* Division by 2, ck_hsi(_ker) = 32 MHz*/ 330 #define RCC_HSI_DIV4 RCC_HSICFGR_HSIDIV_2 /* Division by 4, ck_hsi(_ker) = 16 MHz*/ 331 #define RCC_HSI_DIV8 RCC_HSICFGR_HSIDIV_3 /* Division by 8, ck_hsi(_ker) = 8 MHz*/ 332 333 #define IS_RCC_HSIDIV(DIV) (((DIV) == RCC_HSI_DIV1) || ((DIV) == RCC_HSI_DIV2) || \ 334 ((DIV) == RCC_HSI_DIV4) || ((DIV) == RCC_HSI_DIV8) ) 335 /** 336 * @} 337 */ 338 339 340 /** @defgroup RCC_LSI_Config RCC_LSI_Config 341 * @{ 342 */ 343 #define RCC_LSI_OFF ((uint32_t)0x00000000) 344 #define RCC_LSI_ON RCC_RDLSICR_LSION 345 346 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 347 /** 348 * @} 349 */ 350 351 /** @defgroup RCC_CSI_Config RCC_CSI_Config 352 * @{ 353 */ 354 #define RCC_CSI_OFF ((uint32_t)0x00000000) 355 #define RCC_CSI_ON RCC_OCENSETR_CSION 356 357 #define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) 358 /** 359 * @} 360 */ 361 362 363 /** @defgroup RCC_MCO_Index RCC_MCO_Index 364 * @{ 365 */ 366 #define RCC_MCO1 ((uint32_t)0x00000000) 367 #define RCC_MCO2 ((uint32_t)0x00000001) 368 369 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 370 /** 371 * @} 372 */ 373 374 /** @defgroup RCC_MCO1_Clock_Source RCC_MCO1_Clock_Source 375 * @{ 376 */ 377 #define RCC_MCO1SOURCE_HSI RCC_MCO1CFGR_MCO1SEL_0 378 #define RCC_MCO1SOURCE_HSE RCC_MCO1CFGR_MCO1SEL_1 379 #define RCC_MCO1SOURCE_CSI RCC_MCO1CFGR_MCO1SEL_2 380 #define RCC_MCO1SOURCE_LSI RCC_MCO1CFGR_MCO1SEL_3 381 #define RCC_MCO1SOURCE_LSE RCC_MCO1CFGR_MCO1SEL_4 382 383 384 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ 385 ((SOURCE) == RCC_MCO1SOURCE_CSI) || ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ 386 ((SOURCE) == RCC_MCO1SOURCE_LSE) ) 387 /** 388 * @} 389 */ 390 391 /** @defgroup RCC_MCO2_Clock_Source RCC_MCO2_Clock_Source 392 * @{ 393 */ 394 #define RCC_MCO2SOURCE_MPU RCC_MCO2CFGR_MCO2SEL_0 395 #define RCC_MCO2SOURCE_AXI RCC_MCO2CFGR_MCO2SEL_1 396 #define RCC_MCO2SOURCE_MCU RCC_MCO2CFGR_MCO2SEL_2 397 #define RCC_MCO2SOURCE_PLL4 RCC_MCO2CFGR_MCO2SEL_3 398 #define RCC_MCO2SOURCE_HSE RCC_MCO2CFGR_MCO2SEL_4 399 #define RCC_MCO2SOURCE_HSI RCC_MCO2CFGR_MCO2SEL_5 400 401 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_MPU) || ((SOURCE) == RCC_MCO2SOURCE_AXI) || \ 402 ((SOURCE) == RCC_MCO2SOURCE_MCU) || ((SOURCE) == RCC_MCO2SOURCE_PLL4) || \ 403 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_HSI)) 404 /** 405 * @} 406 */ 407 408 /** @defgroup RCC_MCOx_Clock_Prescaler RCC_MCOx_Clock_Prescaler 409 * @{ 410 * @note: MCO1 division factors are used for MCODIV values as they are the same for MCO2 411 */ 412 #define RCC_MCODIV_1 RCC_MCO1CFGR_MCO1DIV_0 413 #define RCC_MCODIV_2 RCC_MCO1CFGR_MCO1DIV_1 414 #define RCC_MCODIV_3 RCC_MCO1CFGR_MCO1DIV_2 415 #define RCC_MCODIV_4 RCC_MCO1CFGR_MCO1DIV_3 416 #define RCC_MCODIV_5 RCC_MCO1CFGR_MCO1DIV_4 417 #define RCC_MCODIV_6 RCC_MCO1CFGR_MCO1DIV_5 418 #define RCC_MCODIV_7 RCC_MCO1CFGR_MCO1DIV_6 419 #define RCC_MCODIV_8 RCC_MCO1CFGR_MCO1DIV_7 420 #define RCC_MCODIV_9 RCC_MCO1CFGR_MCO1DIV_8 421 #define RCC_MCODIV_10 RCC_MCO1CFGR_MCO1DIV_9 422 #define RCC_MCODIV_11 RCC_MCO1CFGR_MCO1DIV_10 423 #define RCC_MCODIV_12 RCC_MCO1CFGR_MCO1DIV_11 424 #define RCC_MCODIV_13 RCC_MCO1CFGR_MCO1DIV_12 425 #define RCC_MCODIV_14 RCC_MCO1CFGR_MCO1DIV_13 426 #define RCC_MCODIV_15 RCC_MCO1CFGR_MCO1DIV_14 427 #define RCC_MCODIV_16 RCC_MCO1CFGR_MCO1DIV_15 428 429 430 431 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 432 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 433 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ 434 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ 435 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ 436 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ 437 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ 438 ((DIV) == RCC_MCODIV_15) || ((DIV) == RCC_MCODIV_16) ) 439 /** 440 * @} 441 */ 442 443 444 /** @defgroup RCC_MPU_Clock_Source RCC_MPU_Clock_Source 445 * @{ 446 */ 447 #define RCC_MPUSOURCE_HSI RCC_MPCKSELR_MPUSRC_0 448 #define RCC_MPUSOURCE_HSE RCC_MPCKSELR_MPUSRC_1 449 #define RCC_MPUSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_2 450 #define RCC_MPUSOURCE_MPUDIV RCC_MPCKSELR_MPUSRC_3 451 452 #define IS_RCC_MPUSOURCE(SOURCE) (((SOURCE) == RCC_MPUSOURCE_HSI) || \ 453 ((SOURCE) == RCC_MPUSOURCE_HSE) || \ 454 ((SOURCE) == RCC_MPUSOURCE_PLL1) || \ 455 ((SOURCE) == RCC_MPUSOURCE_MPUDIV)) 456 /** 457 * @} 458 */ 459 460 /** @defgroup RCC_AXISS_Clock_Source RCC_AXISS_Clock_Source 461 * @{ 462 */ 463 #define RCC_AXISSOURCE_HSI RCC_ASSCKSELR_AXISSRC_0 464 #define RCC_AXISSOURCE_HSE RCC_ASSCKSELR_AXISSRC_1 465 #define RCC_AXISSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_2 466 #define RCC_AXISSOURCE_OFF RCC_ASSCKSELR_AXISSRC_3 467 468 #define IS_RCC_AXISSOURCE(SOURCE) (((SOURCE) == RCC_AXISSOURCE_HSI) || \ 469 ((SOURCE) == RCC_AXISSOURCE_HSE) || \ 470 ((SOURCE) == RCC_AXISSOURCE_PLL2) || \ 471 ((SOURCE) == RCC_AXISSOURCE_OFF)) 472 /** 473 * @} 474 */ 475 476 /** @defgroup RCC_MCU_Clock_Source RCC_MCU_Clock_Source 477 * @{ 478 */ 479 #define RCC_MCUSSOURCE_HSI RCC_MSSCKSELR_MCUSSRC_0 480 #define RCC_MCUSSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_1 481 #define RCC_MCUSSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_2 482 #define RCC_MCUSSOURCE_PLL3 RCC_MSSCKSELR_MCUSSRC_3 483 484 #define IS_RCC_MCUSSOURCE(SOURCE) (((SOURCE) == RCC_MCUSSOURCE_HSI) || \ 485 ((SOURCE) == RCC_MCUSSOURCE_HSE) || \ 486 ((SOURCE) == RCC_MCUSSOURCE_CSI) || \ 487 ((SOURCE) == RCC_MCUSSOURCE_PLL3)) 488 /** 489 * @} 490 */ 491 492 493 /** @defgroup RCC_RTC_Division_Factor RCC_RTC_Division_Factor 494 * @{ 495 */ 496 #define RCC_RTCDIV(x) RCC_RTCDIVR_RTCDIV_(y) 497 498 #define IS_RCC_RTC_HSEDIV(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 499 /** 500 * @} 501 */ 502 503 /** @defgroup RCC_MPU_Clock_Divider RCC_MPU_Clock_Divider 504 * @{ 505 */ 506 #define RCC_MPU_DIV_OFF RCC_MPCKDIVR_MPUDIV_0 507 #define RCC_MPU_DIV2 RCC_MPCKDIVR_MPUDIV_1 508 #define RCC_MPU_DIV4 RCC_MPCKDIVR_MPUDIV_2 509 #define RCC_MPU_DIV8 RCC_MPCKDIVR_MPUDIV_3 510 #define RCC_MPU_DIV16 RCC_MPCKDIVR_MPUDIV_4 511 512 #define IS_RCC_MPUDIV(DIVIDER) ( ((DIVIDER) == RCC_MPU_DIV2) || \ 513 ((DIVIDER) == RCC_MPU_DIV4) || \ 514 ((DIVIDER) == RCC_MPU_DIV8) || \ 515 ((DIVIDER) == RCC_MPU_DIV16)) 516 /** 517 * @} 518 */ 519 520 /** @defgroup RCC_AXI_Clock_Divider RCC_AXI_Clock_Divider 521 * @{ 522 */ 523 #define RCC_AXI_DIV1 RCC_AXIDIVR_AXIDIV_0 524 #define RCC_AXI_DIV2 RCC_AXIDIVR_AXIDIV_1 525 #define RCC_AXI_DIV3 RCC_AXIDIVR_AXIDIV_2 526 #define RCC_AXI_DIV4 RCC_AXIDIVR_AXIDIV_3 527 528 #define IS_RCC_AXIDIV(DIVIDER) (((DIVIDER) == RCC_AXI_DIV1) || \ 529 ((DIVIDER) == RCC_AXI_DIV2) || \ 530 ((DIVIDER) == RCC_AXI_DIV3) || \ 531 ((DIVIDER) == RCC_AXI_DIV4)) 532 /** 533 * @} 534 */ 535 536 /** @defgroup RCC_APB4_Clock_Divider RCC_APB4_Clock_Divider 537 * @{ 538 */ 539 #define RCC_APB4_DIV1 RCC_APB4DIVR_APB4DIV_0 540 #define RCC_APB4_DIV2 RCC_APB4DIVR_APB4DIV_1 541 #define RCC_APB4_DIV4 RCC_APB4DIVR_APB4DIV_2 542 #define RCC_APB4_DIV8 RCC_APB4DIVR_APB4DIV_3 543 #define RCC_APB4_DIV16 RCC_APB4DIVR_APB4DIV_4 544 545 #define IS_RCC_APB4DIV(DIVIDER) (((DIVIDER) == RCC_APB4_DIV1) || \ 546 ((DIVIDER) == RCC_APB4_DIV2) || \ 547 ((DIVIDER) == RCC_APB4_DIV4) || \ 548 ((DIVIDER) == RCC_APB4_DIV8) || \ 549 ((DIVIDER) == RCC_APB4_DIV16)) 550 /** 551 * @} 552 */ 553 554 /** @defgroup RCC_APB5_Clock_Divider RCC_APB5_Clock_Divider 555 * @{ 556 */ 557 #define RCC_APB5_DIV1 RCC_APB5DIVR_APB5DIV_0 558 #define RCC_APB5_DIV2 RCC_APB5DIVR_APB5DIV_1 559 #define RCC_APB5_DIV4 RCC_APB5DIVR_APB5DIV_2 560 #define RCC_APB5_DIV8 RCC_APB5DIVR_APB5DIV_3 561 #define RCC_APB5_DIV16 RCC_APB5DIVR_APB5DIV_4 562 563 #define IS_RCC_APB5DIV(DIVIDER) (((DIVIDER) == RCC_APB5_DIV1) || \ 564 ((DIVIDER) == RCC_APB5_DIV2) || \ 565 ((DIVIDER) == RCC_APB5_DIV4) || \ 566 ((DIVIDER) == RCC_APB5_DIV8) || \ 567 ((DIVIDER) == RCC_APB5_DIV16)) 568 /** 569 * @} 570 */ 571 572 /** @defgroup RCC_MCU_Clock_Divider RCC_MCU_Clock_Divider 573 * @{ 574 */ 575 #define RCC_MCU_DIV1 RCC_MCUDIVR_MCUDIV_0 576 #define RCC_MCU_DIV2 RCC_MCUDIVR_MCUDIV_1 577 #define RCC_MCU_DIV4 RCC_MCUDIVR_MCUDIV_2 578 #define RCC_MCU_DIV8 RCC_MCUDIVR_MCUDIV_3 579 #define RCC_MCU_DIV16 RCC_MCUDIVR_MCUDIV_4 580 #define RCC_MCU_DIV32 RCC_MCUDIVR_MCUDIV_5 581 #define RCC_MCU_DIV64 RCC_MCUDIVR_MCUDIV_6 582 #define RCC_MCU_DIV128 RCC_MCUDIVR_MCUDIV_7 583 #define RCC_MCU_DIV256 RCC_MCUDIVR_MCUDIV_8 584 #define RCC_MCU_DIV512 RCC_MCUDIVR_MCUDIV_9 585 586 #define IS_RCC_MCUDIV(DIVIDER) (((DIVIDER) == RCC_MCU_DIV1) || \ 587 ((DIVIDER) == RCC_MCU_DIV2) || \ 588 ((DIVIDER) == RCC_MCU_DIV4) || \ 589 ((DIVIDER) == RCC_MCU_DIV8) || \ 590 ((DIVIDER) == RCC_MCU_DIV16) || \ 591 ((DIVIDER) == RCC_MCU_DIV32) || \ 592 ((DIVIDER) == RCC_MCU_DIV64) || \ 593 ((DIVIDER) == RCC_MCU_DIV128) || \ 594 ((DIVIDER) == RCC_MCU_DIV256) || \ 595 ((DIVIDER) == RCC_MCU_DIV512)) 596 /** 597 * @} 598 */ 599 600 /** @defgroup RCC_APB1_Clock_Divider RCC_APB1_Clock_Divider 601 * @{ 602 */ 603 #define RCC_APB1_DIV1 RCC_APB1DIVR_APB1DIV_0 604 #define RCC_APB1_DIV2 RCC_APB1DIVR_APB1DIV_1 605 #define RCC_APB1_DIV4 RCC_APB1DIVR_APB1DIV_2 606 #define RCC_APB1_DIV8 RCC_APB1DIVR_APB1DIV_3 607 #define RCC_APB1_DIV16 RCC_APB1DIVR_APB1DIV_4 608 609 #define IS_RCC_APB1DIV(DIVIDER) (((DIVIDER) == RCC_APB1_DIV1) || \ 610 ((DIVIDER) == RCC_APB1_DIV2) || \ 611 ((DIVIDER) == RCC_APB1_DIV4) || \ 612 ((DIVIDER) == RCC_APB1_DIV8) || \ 613 ((DIVIDER) == RCC_APB1_DIV16)) 614 /** 615 * @} 616 */ 617 618 /** @defgroup RCC_APB2_Clock_Divider RCC_APB2_Clock_Divider 619 * @{ 620 */ 621 #define RCC_APB2_DIV1 RCC_APB2DIVR_APB2DIV_0 622 #define RCC_APB2_DIV2 RCC_APB2DIVR_APB2DIV_1 623 #define RCC_APB2_DIV4 RCC_APB2DIVR_APB2DIV_2 624 #define RCC_APB2_DIV8 RCC_APB2DIVR_APB2DIV_3 625 #define RCC_APB2_DIV16 RCC_APB2DIVR_APB2DIV_4 626 627 #define IS_RCC_APB2DIV(DIVIDER) (((DIVIDER) == RCC_APB2_DIV1) || \ 628 ((DIVIDER) == RCC_APB2_DIV2) || \ 629 ((DIVIDER) == RCC_APB2_DIV4) || \ 630 ((DIVIDER) == RCC_APB2_DIV8) || \ 631 ((DIVIDER) == RCC_APB2_DIV16)) 632 /** 633 * @} 634 */ 635 636 /** @defgroup RCC_APB3_Clock_Divider RCC_APB3_Clock_Divider 637 * @{ 638 */ 639 #define RCC_APB3_DIV1 RCC_APB3DIVR_APB3DIV_0 640 #define RCC_APB3_DIV2 RCC_APB3DIVR_APB3DIV_1 641 #define RCC_APB3_DIV4 RCC_APB3DIVR_APB3DIV_2 642 #define RCC_APB3_DIV8 RCC_APB3DIVR_APB3DIV_3 643 #define RCC_APB3_DIV16 RCC_APB3DIVR_APB3DIV_4 644 645 #define IS_RCC_APB3DIV(DIVIDER) (((DIVIDER) == RCC_APB3_DIV1) || \ 646 ((DIVIDER) == RCC_APB3_DIV2) || \ 647 ((DIVIDER) == RCC_APB3_DIV4) || \ 648 ((DIVIDER) == RCC_APB3_DIV8) || \ 649 ((DIVIDER) == RCC_APB3_DIV16)) 650 /** 651 * @} 652 */ 653 654 /** @defgroup RCC_PLL_Config RCC_PLL_Config 655 * @{ 656 */ 657 #define RCC_PLL_NONE ((uint32_t)0x00000000) 658 #define RCC_PLL_OFF ((uint32_t)0x00000001) 659 #define RCC_PLL_ON ((uint32_t)0x00000002) 660 661 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ 662 ((PLL) == RCC_PLL_ON)) 663 /** 664 * @} 665 */ 666 667 /** @defgroup RCC_PLL_Mode RCC_PLL_Mode 668 * @{ 669 */ 670 #define RCC_PLL_INTEGER ((uint32_t)0x00000000) 671 #define RCC_PLL_FRACTIONAL ((uint32_t)0x00000001) 672 #define RCC_PLL_SPREAD_SPECTRUM ((uint32_t)0x00000002) 673 674 #define IS_RCC_PLLMODE(MODE) (((MODE) == RCC_PLL_FRACTIONAL) || \ 675 ((MODE) == RCC_PLL_INTEGER) || \ 676 ((MODE) == RCC_PLL_SPREAD_SPECTRUM)) 677 /** 678 * @} 679 */ 680 681 682 /** @defgroup RCC_SSCG_MODE RCC_SSCG_MODE 683 * @{ 684 */ 685 #define RCC_SSCG_CENTER_SPREAD ((uint32_t)0x00000000) 686 #define RCC_SSCG_DOWN_SPREAD ((uint32_t)RCC_PLL1CSGR_SSCG_MODE) 687 688 #define IS_RCC_SSCG_MODE(MODE) (((MODE) == RCC_SSCG_CENTER_SPREAD) || \ 689 ((MODE) == RCC_SSCG_DOWN_SPREAD)) 690 /** 691 * @} 692 */ 693 694 /** @defgroup RCC_MOD_PER RCC_MOD_PER 695 * @{ 696 */ 697 #define RCC_MOD_PER_MIN ((uint32_t)0x00000001) 698 #define RCC_MOD_PER_MAX ((uint32_t)RCC_PLL1CSGR_MOD_PER) /* 8191 */ 699 700 #define IS_RCC_MOD_PER(ADJ) ((RCC_MOD_PER_MIN <= (ADJ)) && \ 701 ((ADJ) <= RCC_MOD_PER_MAX)) 702 /** 703 * @} 704 */ 705 706 /** @defgroup RCC_INC_STEP RCC_INC_STEP 707 * @{ 708 */ 709 #define RCC_INC_STEP_MIN ((uint32_t)0x00000001) 710 #define RCC_INC_STEP_MAX ((uint32_t)0x7FFF) /* 32767 */ 711 712 #define IS_RCC_INC_STEP(ADJ) ((RCC_INC_STEP_MIN <= (ADJ)) && \ 713 ((ADJ) <= RCC_INC_STEP_MAX)) 714 /** 715 * @} 716 */ 717 718 /** @defgroup RCC_RPDFN_DIS RCC_RPDFN_DIS 719 * @{ 720 */ 721 #define RCC_RPDFN_DIS_ENABLED ((uint32_t)0x00000000) 722 #define RCC_RPDFN_DIS_DISABLED ((uint32_t)RCC_PLL1CSGR_RPDFN_DIS) 723 724 #define IS_RCC_RPDFN_DIS(STATE) (((STATE) == RCC_RPDFN_DIS_DISABLED) || \ 725 ((STATE) == RCC_RPDFN_DIS_ENABLED)) 726 /** 727 * @} 728 */ 729 730 731 /** @defgroup RCC_TPDFN_DIS RCC_TPDFN_DIS 732 * @{ 733 */ 734 #define RCC_TPDFN_DIS_ENABLED ((uint32_t)0x00000000) 735 #define RCC_TPDFN_DIS_DISABLED ((uint32_t)RCC_PLL1CSGR_TPDFN_DIS) 736 737 #define IS_RCC_TPDFN_DIS(STATE) (((STATE) == RCC_TPDFN_DIS_DISABLED) || \ 738 ((STATE) == RCC_TPDFN_DIS_ENABLED)) 739 /** 740 * @} 741 */ 742 743 744 /** @defgroup RCC_PLL12_Clock_Source RCC_PLL12_Clock_Source 745 * @{ 746 */ 747 #define RCC_PLL12SOURCE_HSI RCC_RCK12SELR_PLL12SRC_0 748 #define RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_1 749 #define RCC_PLL12SOURCE_OFF RCC_RCK12SELR_PLL12SRC_2 750 751 #define IS_RCC_PLL12SOURCE(SOURCE) (((SOURCE) == RCC_PLL12SOURCE_HSI) || \ 752 ((SOURCE) == RCC_PLL12SOURCE_HSE) || \ 753 ((SOURCE) == RCC_PLL12SOURCE_OFF)) 754 /** 755 * @} 756 */ 757 758 759 /** @defgroup RCC_PLL3_Clock_Source RCC_PLL3_Clock_Source 760 * @{ 761 */ 762 #define RCC_PLL3SOURCE_HSI RCC_RCK3SELR_PLL3SRC_0 763 #define RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_1 764 #define RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_2 765 #define RCC_PLL3SOURCE_OFF RCC_RCK3SELR_PLL3SRC_3 766 767 768 #define IS_RCC_PLL3SOURCE(SOURCE) (((SOURCE) == RCC_PLL3SOURCE_HSI) || \ 769 ((SOURCE) == RCC_PLL3SOURCE_HSE) || \ 770 ((SOURCE) == RCC_PLL3SOURCE_CSI) || \ 771 ((SOURCE) == RCC_PLL3SOURCE_OFF)) 772 773 /** 774 * @} 775 */ 776 777 778 /** @defgroup RCC_PLL4_Clock_Source RCC_PLL4_Clock_Source 779 * @{ 780 */ 781 #define RCC_PLL4SOURCE_HSI RCC_RCK4SELR_PLL4SRC_0 782 #define RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_1 783 #define RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_2 784 #define RCC_PLL4SOURCE_I2S_CKIN RCC_RCK4SELR_PLL4SRC_3 785 786 787 #define IS_RCC_PLL4SOURCE(SOURCE) (((SOURCE) == RCC_PLL4SOURCE_HSI) || \ 788 ((SOURCE) == RCC_PLL4SOURCE_HSE) || \ 789 ((SOURCE) == RCC_PLL4SOURCE_CSI) || \ 790 ((SOURCE) == RCC_PLL4SOURCE_I2S_CKIN)) 791 /** 792 * @} 793 */ 794 795 /** @defgroup RCC_PLL1_MUL_DIV_Factors RCC_PLL1_MUL_DIV_Factors 796 * @{ 797 */ 798 #define IS_RCC_PLLM1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 799 /* @note DIVN limits are different depending if using integer or fractional mode */ 800 #define IS_RCC_PLLN1_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 100)) 801 #define IS_RCC_PLLN1_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) 802 #define IS_RCC_PLLP1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 803 #define IS_RCC_PLLQ1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 804 #define IS_RCC_PLLR1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 805 /** 806 * @} 807 */ 808 809 /** @defgroup RCC_PLL2_MUL_DIV_Factors RCC_PLL2_MUL_DIV_Factors 810 * @{ 811 */ 812 #define IS_RCC_PLLM2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 813 /* @note DIVN limits are different depending if using integer or fractional mode */ 814 #define IS_RCC_PLLN2_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 100)) 815 #define IS_RCC_PLLN2_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) 816 #define IS_RCC_PLLP2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 817 #define IS_RCC_PLLQ2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 818 #define IS_RCC_PLLR2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 819 /** 820 * @} 821 */ 822 823 /** @defgroup RCC_PLL3_MUL_DIV_Factors RCC_PLL3_MUL_DIV_Factors 824 * @{ 825 */ 826 #define IS_RCC_PLLM3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 827 /* @note DIVN limits are different depending if using integer or fractional mode */ 828 #define IS_RCC_PLLN3_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 200)) 829 #define IS_RCC_PLLN3_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) 830 #define IS_RCC_PLLP3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 831 #define IS_RCC_PLLQ3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 832 #define IS_RCC_PLLR3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 833 /** 834 * @} 835 */ 836 837 /** @defgroup RCC_PLL4_MUL_DIV_Factors RCC_PLL4_MUL_DIV_Factors 838 * @{ 839 */ 840 #define IS_RCC_PLLM4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) 841 /* @note DIVN limits are different depending if using integer or fractional mode */ 842 #define IS_RCC_PLLN4_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 200)) 843 #define IS_RCC_PLLN4_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) 844 #define IS_RCC_PLLP4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 845 #define IS_RCC_PLLQ4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 846 #define IS_RCC_PLLR4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) 847 /** 848 * @} 849 */ 850 851 /** @defgroup RCC_PLL1_Clock_Output RCC_PLL1_Clock_Output 852 * @{ 853 */ 854 #define RCC_PLL1_DIVP RCC_PLL1CR_DIVPEN 855 #define RCC_PLL1_DIVQ RCC_PLL1CR_DIVQEN 856 #define RCC_PLL1_DIVR RCC_PLL1CR_DIVREN 857 858 #define IS_RCC_PLL1CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ 859 ((VALUE) == RCC_PLL1_DIVQ) || \ 860 ((VALUE) == RCC_PLL1_DIVR)) 861 /** 862 * @} 863 */ 864 865 866 /** @defgroup RCC_PLL2_Clock_Output RCC_PLL2_Clock_Output 867 * @{ 868 */ 869 #define RCC_PLL2_DIVP RCC_PLL2CR_DIVPEN 870 #define RCC_PLL2_DIVQ RCC_PLL2CR_DIVQEN 871 #define RCC_PLL2_DIVR RCC_PLL2CR_DIVREN 872 873 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2CR_DIVPEN) || \ 874 ((VALUE) == RCC_PLL2CR_DIVQEN) || \ 875 ((VALUE) == RCC_PLL2CR_DIVREN)) 876 /** 877 * @} 878 */ 879 880 /** @defgroup RCC_PLL3_Clock_Output RCC_PLL3_Clock_Output 881 * @{ 882 */ 883 884 #define RCC_PLL3_DIVP RCC_PLL3CR_DIVPEN 885 #define RCC_PLL3_DIVQ RCC_PLL3CR_DIVQEN 886 #define RCC_PLL3_DIVR RCC_PLL3CR_DIVREN 887 888 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ 889 ((VALUE) == RCC_PLL3_DIVQ) || \ 890 ((VALUE) == RCC_PLL3_DIVR)) 891 /** 892 * @} 893 */ 894 895 /** @defgroup RCC_PLL4_Clock_Output RCC_PLL4_Clock_Output 896 * @{ 897 */ 898 #define RCC_PLL4_DIVP RCC_PLL4CR_DIVPEN 899 #define RCC_PLL4_DIVQ RCC_PLL4CR_DIVQEN 900 #define RCC_PLL4_DIVR RCC_PLL4CR_DIVREN 901 902 #define IS_RCC_PLL4CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL4_DIVP) || \ 903 ((VALUE) == RCC_PLL4_DIVQ) || \ 904 ((VALUE) == RCC_PLL4_DIVR)) 905 906 907 /** 908 * @} 909 */ 910 911 /** @defgroup RCC_PLL3_IF_Range RCC_PLL3_IF_Range 912 * @{ 913 */ 914 #define RCC_PLL3IFRANGE_0 RCC_PLL3CFGR1_IFRGE_0 915 #define RCC_PLL3IFRANGE_1 RCC_PLL3CFGR1_IFRGE_1 916 /** 917 * @} 918 */ 919 920 /** @defgroup RCC_PLL4_IF_Range RCC_PLL4_IF_Range 921 * @{ 922 */ 923 #define RCC_PLL4IFRANGE_0 RCC_PLL4CFGR1_IFRGE_0 924 #define RCC_PLL4IFRANGE_1 RCC_PLL4CFGR1_IFRGE_1 925 /** 926 * @} 927 */ 928 929 930 /** @defgroup RCC_RTC_Clock_Source RCC_RTC_Clock_Source 931 * @{ 932 */ 933 #define RCC_RTCCLKSOURCE_OFF RCC_BDCR_RTCSRC_0 /* No clock (default after backup domain reset)*/ 934 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSRC_1 935 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSRC_2 936 #define RCC_RTCCLKSOURCE_HSE_DIV RCC_BDCR_RTCSRC_3 /* HSE clock divided by RTCDIV value is used as RTC clock*/ 937 938 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_OFF) || ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ 939 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV)) 940 /** 941 * @} 942 */ 943 944 /** @defgroup RCC_Flag RCC_Flag 945 * @{ 946 */ 947 /* Flags in the OCRDYR register */ 948 #define RCC_FLAG_HSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIRDY) == RCC_OCRDYR_HSIRDY ) 949 #define RCC_FLAG_HSIDIVRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIDIVRDY) == RCC_OCRDYR_HSIDIVRDY ) 950 #define RCC_FLAG_CSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_CSIRDY) == RCC_OCRDYR_CSIRDY ) 951 #define RCC_FLAG_HSERDY ( (RCC->OCRDYR & RCC_OCRDYR_HSERDY) == RCC_OCRDYR_HSERDY ) 952 #define RCC_FLAG_AXICKRDY ( (RCC->OCRDYR & RCC_OCRDYR_AXICKRDY) == RCC_OCRDYR_AXICKRDY ) 953 #define RCC_FLAG_CKREST ( (RCC->OCRDYR & RCC_OCRDYR_CKREST) == RCC_OCRDYR_CKREST ) 954 955 /* Flags in the MPCKSELR register */ 956 #define RCC_FLAG_MPUSRCRDY ( (RCC->MPCKSELR & RCC_MPCKSELR_MPUSRCRDY) == RCC_MPCKSELR_MPUSRCRDY ) 957 958 /* Flags in the ASSCKSELR register */ 959 #define RCC_FLAG_AXISSRCRDY ( (RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRCRDY) == RCC_ASSCKSELR_AXISSRCRDY ) 960 961 /* Flags in the MSSCKSELR register */ 962 #define RCC_FLAG_MCUSSRCRDY ( (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY) == RCC_MSSCKSELR_MCUSSRCRDY ) 963 964 /* Flags in the RCK12SELR register */ 965 #define RCC_FLAG_PLL12SRCRDY ( (RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRCRDY) == RCC_RCK12SELR_PLL12SRCRDY ) 966 967 /* Flags in the RCK3SELR */ 968 #define RCC_FLAG_PLL3SRCRDY ( (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRCRDY) == RCC_RCK3SELR_PLL3SRCRDY ) 969 970 /* Flags in the RCK4SELR register */ 971 #define RCC_FLAG_PLL4SRCRDY ( (RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRCRDY) == RCC_RCK4SELR_PLL4SRCRDY ) 972 973 /* Flags in the TIMG1PRER register */ 974 #define RCC_FLAG_TIMG1PRERDY ( (RCC->TIMG1PRER & RCC_TIMG1PRER_TIMG1PRERDY) == RCC_TIMG1PRER_TIMG1PRERDY ) 975 976 /* Flags in the TIMG2PRER register */ 977 #define RCC_FLAG_TIMG2PRERDY ( (RCC->TIMG2PRER & RCC_TIMG2PRER_TIMG2PRERDY) == RCC_TIMG2PRER_TIMG2PRERDY ) 978 979 /* Flags in the MPCKDIVR register */ 980 #define RCC_FLAG_MPUDIVRDY ( (RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIVRDY) == RCC_MPCKDIVR_MPUDIVRDY ) 981 982 /* Flags in the AXIDIVR register */ 983 #define RCC_FLAG_AXIDIVRDY ( (RCC->AXIDIVR & RCC_AXIDIVR_AXIDIVRDY) == RCC_AXIDIVR_AXIDIVRDY ) 984 985 /* Flags in the APB4DIVR register */ 986 #define RCC_FLAG_APB4DIVRDY ( (RCC->APB4DIVR & RCC_APB4DIVR_APB4DIVRDY) == RCC_APB4DIVR_APB4DIVRDY ) 987 988 /* Flags in the APB5DIVR register */ 989 #define RCC_FLAG_APB5DIVRDY ( (RCC->APB5DIVR & RCC_APB5DIVR_APB5DIVRDY) == RCC_APB5DIVR_APB5DIVRDY ) 990 991 /* Flags in the MCUDIVR register */ 992 #define RCC_FLAG_MCUDIVRDY ( (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIVRDY) == RCC_MCUDIVR_MCUDIVRDY ) 993 994 /* Flags in the APB1DIVR register */ 995 #define RCC_FLAG_APB1DIVRDY ((RCC->APB1DIVR & RCC_APB1DIVR_APB1DIVRDY) == RCC_APB1DIVR_APB1DIVRDY ) 996 997 /* Flags in the APB2DIVR register */ 998 #define RCC_FLAG_APB2DIVRDY ((RCC->APB2DIVR & RCC_APB2DIVR_APB2DIVRDY) == RCC_APB2DIVR_APB2DIVRDY ) 999 1000 /* Flags in the APB3DIVR register */ 1001 #define RCC_FLAG_APB3DIVRDY ((RCC->APB3DIVR & RCC_APB3DIVR_APB3DIVRDY) == RCC_APB3DIVR_APB3DIVRDY ) 1002 1003 /* Flags in the PLL1CR register */ 1004 #define RCC_FLAG_PLL1RDY ((RCC->PLL1CR & RCC_PLL1CR_PLL1RDY) == RCC_PLL1CR_PLL1RDY ) 1005 1006 /* Flags in the PLL2CR register */ 1007 #define RCC_FLAG_PLL2RDY ((RCC->PLL2CR & RCC_PLL2CR_PLL2RDY) == RCC_PLL2CR_PLL2RDY ) 1008 1009 /* Flags in the PLL3CR register */ 1010 #define RCC_FLAG_PLL3RDY ((RCC->PLL3CR & RCC_PLL3CR_PLL3RDY) == RCC_PLL3CR_PLL3RDY ) 1011 1012 /* Flags in the PLL4CR register */ 1013 #define RCC_FLAG_PLL4RDY ((RCC->PLL4CR & RCC_PLL4CR_PLL4RDY) == RCC_PLL4CR_PLL4RDY ) 1014 1015 /* Flags in the DDRCKSELR register */ 1016 #define RCC_FLAG_DDRPHYCSRCRDY ((RCC->DDRCKSELR & RCC_DDRCKSELR_DDRPHYCSRCRDY) == RCC_DDRCKSELR_DDRPHYCSRCRDY ) 1017 1018 /* Flags in the BDCR register */ 1019 #define RCC_FLAG_LSERDY ((RCC->BDCR & RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY ) 1020 1021 /* Flags in the RDLSICR register */ 1022 #define RCC_FLAG_LSIRDY ((RCC->RDLSICR & RCC_RDLSICR_LSIRDY) == RCC_RDLSICR_LSIRDY ) 1023 1024 #if defined(CORE_CA7) 1025 /* Flags in the RCC_MP_RSTSCLRR */ 1026 #define RCC_MASK_ALL_RESET_FLAGS (0x00001BDFU) 1027 #define RCC_FLAG_PORRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_PORRSTF) == RCC_MP_RSTSCLRR_PORRSTF) 1028 #define RCC_FLAG_BORRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_BORRSTF) == RCC_MP_RSTSCLRR_BORRSTF) 1029 #define RCC_FLAG_PADRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_PADRSTF) == RCC_MP_RSTSCLRR_PADRSTF) 1030 #define RCC_FLAG_HCSSRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_HCSSRSTF) == RCC_MP_RSTSCLRR_HCSSRSTF) 1031 #define RCC_FLAG_VCORERST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_VCORERSTF) == RCC_MP_RSTSCLRR_VCORERSTF) 1032 #define RCC_FLAG_MPSYSRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPSYSRSTF) == RCC_MP_RSTSCLRR_MPSYSRSTF) 1033 #define RCC_FLAG_MCSYSRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MCSYSRSTF) == RCC_MP_RSTSCLRR_MCSYSRSTF) 1034 #define RCC_FLAG_IWDG1RST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_IWDG1RSTF) == RCC_MP_RSTSCLRR_IWDG1RSTF) 1035 #define RCC_FLAG_IWDG2RST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_IWDG2RSTF) == RCC_MP_RSTSCLRR_IWDG2RSTF) 1036 #define RCC_FLAG_STDBYRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_STDBYRSTF) == RCC_MP_RSTSCLRR_STDBYRSTF) 1037 #define RCC_FLAG_CSTDBYRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_CSTDBYRSTF) == RCC_MP_RSTSCLRR_CSTDBYRSTF) 1038 #define RCC_FLAG_MPUP0RSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPUP0RSTF) == RCC_MP_RSTSCLRR_MPUP0RSTF) 1039 #define RCC_FLAG_MPUP1RSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPUP1RSTF) == RCC_MP_RSTSCLRR_MPUP1RSTF) 1040 #elif defined(CORE_CM4) 1041 /* Flags in the RCC_MC_RSTSCLRR */ 1042 #define RCC_MASK_ALL_RESET_FLAGS (0x000007FFU) 1043 #define RCC_FLAG_PORRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_PORRSTF) == RCC_MC_RSTSCLRR_PORRSTF) 1044 #define RCC_FLAG_BORRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_BORRSTF) == RCC_MC_RSTSCLRR_BORRSTF) 1045 #define RCC_FLAG_PADRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_PADRSTF) == RCC_MC_RSTSCLRR_PADRSTF) 1046 #define RCC_FLAG_HCSSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_HCSSRSTF) == RCC_MC_RSTSCLRR_HCSSRSTF) 1047 #define RCC_FLAG_VCORERST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_VCORERSTF) == RCC_MC_RSTSCLRR_VCORERSTF) 1048 #define RCC_FLAG_MCURST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MCURSTF) == RCC_MC_RSTSCLRR_MCURSTF) 1049 #define RCC_FLAG_MPSYSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MPSYSRSTF) == RCC_MC_RSTSCLRR_MPSYSRSTF) 1050 #define RCC_FLAG_MCSYSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MCSYSRSTF) == RCC_MC_RSTSCLRR_MCSYSRSTF) 1051 #define RCC_FLAG_IWDG1RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_IWDG1RSTF) == RCC_MC_RSTSCLRR_IWDG1RSTF) 1052 #define RCC_FLAG_IWDG2RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_IWDG2RSTF) == RCC_MC_RSTSCLRR_IWDG2RSTF) 1053 #define RCC_FLAG_WWDG1RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_WWDG1RSTF) == RCC_MC_RSTSCLRR_WWDG1RSTF) 1054 #endif 1055 1056 /** @brief Clear all the reset flags 1057 * @note Writing a '1' clears the corresponding bit to '0' 1058 */ 1059 #if defined(CORE_CA7) 1060 #define __HAL_RCC_CLEAR_RESET_FLAGS() WRITE_REG(RCC->MP_RSTSCLRR, RCC_MASK_ALL_RESET_FLAGS) 1061 #elif defined(CORE_CM4) 1062 #define __HAL_RCC_CLEAR_RESET_FLAGS() WRITE_REG(RCC->MC_RSTSCLRR, RCC_MASK_ALL_RESET_FLAGS) 1063 #endif /* CORE_CA7 */ 1064 1065 #if defined(CORE_CA7) 1066 /** @brief Check RCC flag is set or not. 1067 * @param __FLAG__: specifies the flag to check. 1068 * This parameter can be one of the following values: 1069 * @arg RCC_FLAG_PORRST 1070 * @arg RCC_FLAG_BORRST 1071 * @arg RCC_FLAG_PADRST 1072 * @arg RCC_FLAG_HCSSRST 1073 * @arg RCC_FLAG_VCORERST 1074 * @arg RCC_FLAG_MPSYSRSTF 1075 * @arg RCC_FLAG_MCSYSRSTF 1076 * @arg RCC_FLAG_IWDG1RST 1077 * @arg RCC_FLAG_IWDG2RST 1078 * @arg RCC_FLAG_STDBYRSTF 1079 * @arg RCC_FLAG_CSTDBYRSTF 1080 * @arg RCC_FLAG_MPUP0RSTF 1081 * @arg RCC_FLAG_MPUP1RSTF 1082 * @retval The state of __FLAG__ (TRUE or FALSE). 1083 */ 1084 #elif defined(CORE_CM4) 1085 /** @brief Check RCC flag is set or not. 1086 * @param __FLAG__: specifies the flag to check. 1087 * This parameter can be one of the following values: 1088 * @arg RCC_FLAG_PORRST 1089 * @arg RCC_FLAG_BORRST 1090 * @arg RCC_FLAG_PADRST 1091 * @arg RCC_FLAG_HCSSRST 1092 * @arg RCC_FLAG_VCORERST 1093 * @arg RCC_FLAG_MCURST 1094 * @arg RCC_FLAG_MPSYSRST 1095 * @arg RCC_FLAG_MCSYSRST 1096 * @arg RCC_FLAG_IWDG1RST 1097 * @arg RCC_FLAG_IWDG2RST 1098 * @arg RCC_FLAG_WWDG1RST 1099 * @retval The state of __FLAG__ (TRUE or FALSE). 1100 */ 1101 #endif /* CORE_CA7 */ 1102 #define __HAL_RCC_GET_FLAG(__FLAG__) ( __FLAG__ ? 1:0 ) 1103 /** 1104 * @} 1105 */ 1106 1107 /** @defgroup RCC_Calibration RCC_Calibration limits 1108 * @{ 1109 */ 1110 /** RCC_Calibration limits*/ 1111 #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) 1112 #define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 1113 /** 1114 * @} 1115 */ 1116 1117 /** @defgroup RCC_LSEDrive_Config RCC_LSEDrive_Config 1118 * @{ 1119 */ 1120 #define RCC_LSEDRIVE_LOW RCC_BDCR_LSEDRV_0 /*!< LSE low drive capability */ 1121 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< LSE medium low drive capability */ 1122 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_2 /*!< LSE medium high drive capability */ 1123 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV_3 /*!< LSE high drive capability */ 1124 1125 #define IS_RCC_LSEDRIVE(VALUE) (((VALUE) == RCC_LSEDRIVE_LOW) || ((VALUE) == RCC_LSEDRIVE_MEDIUMLOW) || \ 1126 ((VALUE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((VALUE) == RCC_LSEDRIVE_HIGH)) 1127 /** 1128 * @} 1129 */ 1130 1131 1132 /** @defgroup RCC_Interrupt RCC_Interrupt 1133 * @{ 1134 */ 1135 #ifdef CORE_CM4 1136 #define RCC_IT_LSIRDY RCC_MC_CIFR_LSIRDYF 1137 #define RCC_IT_LSERDY RCC_MC_CIFR_LSERDYF 1138 #define RCC_IT_HSIRDY RCC_MC_CIFR_HSIRDYF 1139 #define RCC_IT_HSERDY RCC_MC_CIFR_HSERDYF 1140 #define RCC_IT_CSIRDY RCC_MC_CIFR_CSIRDYF 1141 #define RCC_IT_PLLRDY RCC_MC_CIFR_PLL1DYF 1142 #define RCC_IT_PLL2RDY RCC_MC_CIFR_PLL2DYF 1143 #define RCC_IT_PLL3RDY RCC_MC_CIFR_PLL3DYF 1144 #define RCC_IT_PLL4RDY RCC_MC_CIFR_PLL4DYF 1145 #define RCC_IT_LSECSS RCC_MC_CIFR_LSECSSF 1146 #define RCC_IT_WKUP RCC_MC_CIFR_WKUPF 1147 #endif /* CORE_CM4*/ 1148 1149 #ifdef CORE_CA7 1150 #define RCC_IT_LSIRDY RCC_MP_CIFR_LSIRDYF 1151 #define RCC_IT_LSERDY RCC_MP_CIFR_LSERDYF 1152 #define RCC_IT_HSIRDY RCC_MP_CIFR_HSIRDYF 1153 #define RCC_IT_HSERDY RCC_MP_CIFR_HSERDYF 1154 #define RCC_IT_CSIRDY RCC_MP_CIFR_CSIRDYF 1155 #define RCC_IT_PLLRDY RCC_MP_CIFR_PLL1DYF 1156 #define RCC_IT_PLL2RDY RCC_MP_CIFR_PLL2DYF 1157 #define RCC_IT_PLL3RDY RCC_MP_CIFR_PLL3DYF 1158 #define RCC_IT_PLL4RDY RCC_MP_CIFR_PLL4DYF 1159 #define RCC_IT_LSECSS RCC_MP_CIFR_LSECSSF 1160 #define RCC_IT_WKUP RCC_MP_CIFR_WKUPF 1161 #endif /* CORE_CA7 */ 1162 1163 #define RCC_IT_ALL (RCC_IT_LSIRDY | RCC_IT_LSERDY | RCC_IT_HSIRDY | \ 1164 RCC_IT_HSERDY | RCC_IT_CSIRDY | RCC_IT_PLLRDY | \ 1165 RCC_IT_PLL2RDY | RCC_IT_PLL3RDY | RCC_IT_PLL4RDY | \ 1166 RCC_IT_LSECSS | RCC_IT_WKUP) 1167 1168 #define IS_RCC_IT(VALUE) (((VALUE) == RCC_IT_LSIRDY) || ((VALUE) == RCC_IT_LSERDY) || \ 1169 ((VALUE) == RCC_IT_HSIRDY) || ((VALUE) == RCC_IT_HSERDY) || \ 1170 ((VALUE) == RCC_IT_CSIRDY) || ((VALUE) == RCC_IT_PLLRDY) || \ 1171 ((VALUE) == RCC_IT_PLL2RDY) || ((VALUE) == RCC_IT_PLL3RDY) || \ 1172 ((VALUE) == RCC_IT_PLL4RDY) || ((VALUE) == RCC_IT_LSECSS) || \ 1173 ((VALUE) == RCC_IT_WKUP)) 1174 1175 /** 1176 * @} 1177 */ 1178 1179 /** 1180 * @} 1181 */ 1182 1183 /* Exported macros -----------------------------------------------------------*/ 1184 1185 /** @defgroup RCC_Exported_Macros RCC_Exported_Macros 1186 * @{ 1187 */ 1188 /** @brief Force or release the APB1 peripheral reset */ 1189 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTSETR = 0xADEFDBFFU) 1190 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM2RST) 1191 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM3RST) 1192 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM4RST) 1193 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM5RST) 1194 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM6RST) 1195 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM7RST) 1196 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM12RST) 1197 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM13RST) 1198 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM14RST) 1199 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_LPTIM1RST) 1200 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPI2RST) 1201 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPI3RST) 1202 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_USART2RST) 1203 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_USART3RST) 1204 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART4RST) 1205 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART5RST) 1206 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART7RST) 1207 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART8RST) 1208 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C1RST) 1209 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C2RST) 1210 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C3RST) 1211 #define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C5RST) 1212 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPDIFRST) 1213 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_CECRST) 1214 #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_DAC12RST) 1215 #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_MDIOSRST) 1216 1217 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTCLRR = 0xADEFDBFFU) 1218 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM2RST) 1219 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM3RST) 1220 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM4RST) 1221 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM5RST) 1222 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM6RST) 1223 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM7RST) 1224 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM12RST) 1225 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM13RST) 1226 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM14RST) 1227 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_LPTIM1RST) 1228 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPI2RST) 1229 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPI3RST) 1230 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_USART2RST) 1231 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_USART3RST) 1232 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART4RST) 1233 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART5RST) 1234 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART7RST) 1235 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART8RST) 1236 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C1RST) 1237 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C2RST) 1238 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C3RST) 1239 #define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C5RST) 1240 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPDIFRST) 1241 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_CECRST) 1242 #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_DAC12RST) 1243 #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_MDIOSRST) 1244 1245 /** @brief Force or release the APB2 peripheral reset. */ 1246 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTSETR = 0x117271FU) 1247 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM1RST) 1248 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM8RST) 1249 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM15RST) 1250 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM16RST) 1251 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM17RST) 1252 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI1RST) 1253 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI4RST) 1254 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI5RST) 1255 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_USART6RST) 1256 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI1RST) 1257 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI2RST) 1258 #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI3RST) 1259 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_DFSDMRST) 1260 #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_FDCANRST) 1261 1262 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTCLRR = 0x117271FU) 1263 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM1RST) 1264 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM8RST) 1265 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM15RST) 1266 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM16RST) 1267 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM17RST) 1268 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI1RST) 1269 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI4RST) 1270 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI5RST) 1271 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_USART6RST) 1272 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI1RST) 1273 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI2RST) 1274 #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI3RST) 1275 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_DFSDMRST) 1276 #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_FDCANRST) 1277 1278 /** @brief Force or release the APB3 peripheral reset. */ 1279 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTSETR = 0x0003290FU) 1280 #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM2RST) 1281 #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM3RST) 1282 #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM4RST) 1283 #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM5RST) 1284 #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SAI4RST) 1285 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SYSCFGRST) 1286 #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_VREFRST) 1287 #define __HAL_RCC_TMPSENS_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_TMPSENSRST) 1288 #define __HAL_RCC_PMBCTRL_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_PMBCTRLRST) 1289 1290 #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTCLRR = 0x0003290FU) 1291 #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM2RST) 1292 #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM3RST) 1293 #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM4RST) 1294 #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM5RST) 1295 #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SAI4RST) 1296 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SYSCFGRST) 1297 #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_VREFRST) 1298 #define __HAL_RCC_TMPSENS_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_TMPSENSRST) 1299 #define __HAL_RCC_PMBCTRL_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_PMBCTRLRST) 1300 1301 /** @brief Force or release the AHB2 peripheral reset. */ 1302 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTSETR = 0x00010127U) 1303 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMA1RST) 1304 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMA2RST) 1305 #define __HAL_RCC_DMAMUX_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMAMUXRST) 1306 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_ADC12RST) 1307 #define __HAL_RCC_USBO_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_USBORST) 1308 #define __HAL_RCC_SDMMC3_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_SDMMC3RST) 1309 1310 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTCLRR = 0x00010127U) 1311 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMA1RST) 1312 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMA2RST) 1313 #define __HAL_RCC_DMAMUX_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMAMUXRST) 1314 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_ADC12RST) 1315 #define __HAL_RCC_USBO_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_USBORST) 1316 #define __HAL_RCC_SDMMC3_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_SDMMC3RST) 1317 1318 /** @brief Force or release the AHB3 peripheral reset. */ 1319 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_DCMIRST) 1320 #if defined(CRYP2) 1321 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTSETR = 0x000018F1U) 1322 #define __HAL_RCC_CRYP2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_CRYP2RST) 1323 #else 1324 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTSETR = 0x000018E1U) 1325 #endif /* CRYP2 */ 1326 #define __HAL_RCC_HASH2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_HASH2RST) 1327 #define __HAL_RCC_RNG2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_RNG2RST) 1328 #define __HAL_RCC_CRC2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_CRC2RST) 1329 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_HSEMRST) 1330 #define __HAL_RCC_IPCC_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_IPCCRST) 1331 1332 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_DCMIRST) 1333 #if defined(CRYP2) 1334 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTCLRR = 0x000018F1U) 1335 #define __HAL_RCC_CRYP2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_CRYP2RST) 1336 #else 1337 #define __HAL_RCC_AHB3_REALEASE_RESET() (RCC->AHB3RSTCLRR = 0x000018E1U) 1338 #endif /* CRYP2 */ 1339 #define __HAL_RCC_HASH2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_HASH2RST) 1340 #define __HAL_RCC_RNG2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_RNG2RST) 1341 #define __HAL_RCC_CRC2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_CRC2RST) 1342 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_HSEMRST) 1343 #define __HAL_RCC_IPCC_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_IPCCRST) 1344 1345 /** @brief Force or release the AHB4 peripheral reset. */ 1346 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTSETR = 0x000007FFU) 1347 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOARST) 1348 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOBRST) 1349 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOCRST) 1350 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIODRST) 1351 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOERST) 1352 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOFRST) 1353 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOGRST) 1354 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOHRST) 1355 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOIRST) 1356 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOJRST) 1357 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOKRST) 1358 1359 #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTCLRR = 0x000007FFU) 1360 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOARST) 1361 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOBRST) 1362 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOCRST) 1363 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIODRST) 1364 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOERST) 1365 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOFRST) 1366 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOGRST) 1367 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOHRST) 1368 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOIRST) 1369 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOJRST) 1370 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOKRST) 1371 1372 /** @brief Force or release the APB4 peripheral reset. */ 1373 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTSETR = 0x00010111U) 1374 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_LTDCRST) 1375 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_DSIRST) 1376 #define __HAL_RCC_DDRPERFM_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_DDRPERFMRST) 1377 #define __HAL_RCC_USBPHY_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_USBPHYRST) 1378 1379 #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTCLRR = 0x00010111U) 1380 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_LTDCRST) 1381 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_DSIRST) 1382 #define __HAL_RCC_DDRPERFM_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_DDRPERFMRST) 1383 #define __HAL_RCC_USBPHY_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_USBPHYRST) 1384 1385 /** @brief Force or release the APB5 peripheral reset. */ 1386 /** @note Note that when the secure mode is enabled, only secure accesses can 1387 * reset the peripherals connected to APB5. 1388 */ 1389 #define __HAL_RCC_APB5_FORCE_RESET() (RCC->APB5RSTSETR = 0x0010001DU) 1390 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_SPI6RST) 1391 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_I2C4RST) 1392 #define __HAL_RCC_I2C6_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_I2C6RST) 1393 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_USART1RST) 1394 #define __HAL_RCC_STGEN_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_STGENRST) 1395 1396 #define __HAL_RCC_APB5_RELEASE_RESET() (RCC->APB5RSTCLRR = 0x0010001DU) 1397 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_SPI6RST) 1398 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_I2C4RST) 1399 #define __HAL_RCC_I2C6_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_I2C6RST) 1400 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_USART1RST) 1401 #define __HAL_RCC_STGEN_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_STGENRST) 1402 1403 /** @brief Force or release the AHB5 peripheral reset. */ 1404 #define __HAL_RCC_GPIOZ_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_GPIOZRST) 1405 #if defined(CRYP1) 1406 #define __HAL_RCC_CRYP1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_CRYP1RST) 1407 #define __HAL_RCC_AHB5_FORCE_RESET() (RCC->AHB5RSTSETR = 0x00010071U) 1408 #else 1409 #define __HAL_RCC_AHB5_FORCE_RESET() (RCC->AHB5RSTSETR = 0x00010061U) 1410 #endif /* CRYP1 */ 1411 #define __HAL_RCC_HASH1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_HASH1RST) 1412 #define __HAL_RCC_RNG1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_RNG1RST) 1413 #define __HAL_RCC_AXIMC_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_AXIMCRST) 1414 1415 #define __HAL_RCC_GPIOZ_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_GPIOZRST) 1416 #if defined(CRYP1) 1417 #define __HAL_RCC_CRYP1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_CRYP1RST) 1418 #define __HAL_RCC_AHB5_RELEASE_RESET() (RCC->AHB5RSTCLRR = 0x00010071U) 1419 #else 1420 #define __HAL_RCC_AHB5_RELEASE_RESET() (RCC->AHB5RSTCLRR = 0x00010061U) 1421 #endif /* CRYP1 */ 1422 #define __HAL_RCC_HASH1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_HASH1RST) 1423 #define __HAL_RCC_RNG1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_RNG1RST) 1424 #define __HAL_RCC_AXIMC_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_AXIMCRST) 1425 1426 /** @brief Force or release the AHB6 peripheral reset. */ 1427 #define __HAL_RCC_AHB6_FORCE_RESET() (RCC->AHB6RSTSETR = 0x01135420U) 1428 #define __HAL_RCC_GPU_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_GPURST) 1429 #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_ETHMACRST) 1430 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_FMCRST) 1431 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_QSPIRST) 1432 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_SDMMC1RST) 1433 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_SDMMC2RST) 1434 #define __HAL_RCC_CRC1_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_CRC1RST) 1435 #define __HAL_RCC_USBH_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_USBHRST) 1436 1437 /** @note __HAL_RCC_GPU_RELEASE_RESET does not exist as GPU reset process may 1438 * take several clock cycles, for that purpose, the application can 1439 * read-back the reset bit RCC_AHB6RSTSETR_GPURST in order to check if 1440 * the reset process is on-going or completed after setting 1441 * RCC_AHB6RSTSETR_GPURST 1442 */ 1443 #define __HAL_RCC_AHB6_RELEASE_RESET() (RCC->AHB6RSTCLRR = 0x01135400U) 1444 #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_ETHMACRST) 1445 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_FMCRST) 1446 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_QSPIRST) 1447 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_SDMMC1RST) 1448 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_SDMMC2RST) 1449 #define __HAL_RCC_CRC1_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_CRC1RST) 1450 #define __HAL_RCC_USBH_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_USBHRST) 1451 1452 /** @brief Force or release the TZAHB6 peripheral reset. */ 1453 #define __HAL_RCC_TZAHB6_FORCE_RESET() (RCC->TZAHB6RSTSETR = 0x00000001U) 1454 #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->TZAHB6RSTSETR = RCC_TZAHB6RSTSETR_MDMARST) 1455 1456 #define __HAL_RCC_TZAHB6_RELEASE_RESET() (RCC->TZAHB6RSTCLRR = 0x00000001U) 1457 #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->TZAHB6RSTCLRR = RCC_TZAHB6RSTCLRR_MDMARST) 1458 1459 #ifdef CORE_CA7 1460 /** @brief Enable or disable the APB1 peripheral clock. 1461 * @note After reset, the peripheral clock (used for registers read/write access) 1462 * is disabled and the application software has to enable this clock before 1463 * using it. It shall be used to allocate a peripheral to the MCU. 1464 */ 1465 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM2EN) 1466 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM3EN) 1467 #define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM4EN) 1468 #define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM5EN) 1469 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM6EN) 1470 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM7EN) 1471 #define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM12EN) 1472 #define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM13EN) 1473 #define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM14EN) 1474 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_LPTIM1EN) 1475 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPI2EN) 1476 #define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPI3EN) 1477 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_USART2EN) 1478 #define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_USART3EN) 1479 #define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART4EN) 1480 #define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART5EN) 1481 #define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART7EN) 1482 #define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART8EN) 1483 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C1EN) 1484 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C2EN) 1485 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C3EN) 1486 #define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C5EN) 1487 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPDIFEN) 1488 #define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_CECEN) 1489 #define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_DAC12EN) 1490 #define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_MDIOSEN) 1491 1492 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM2EN) 1493 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM3EN) 1494 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM4EN) 1495 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM5EN) 1496 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM6EN) 1497 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM7EN) 1498 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM12EN) 1499 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM13EN) 1500 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM14EN) 1501 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_LPTIM1EN) 1502 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI2EN) 1503 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI3EN) 1504 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART2EN) 1505 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART3EN) 1506 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN) 1507 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN) 1508 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART5EN) 1509 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART7EN) 1510 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART8EN) 1511 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C1EN) 1512 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C2EN) 1513 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C3EN) 1514 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C5EN) 1515 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPDIFEN) 1516 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_CECEN) 1517 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_DAC12EN) 1518 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_MDIOSEN) 1519 1520 /** @brief Enable or disable the APB2 peripheral clock. 1521 * @note After reset, the peripheral clock (used for registers read/write access) 1522 * is disabled and the application software has to enable this clock before 1523 * using it. It shall be used to allocate a peripheral to the MCU. 1524 */ 1525 #define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM1EN) 1526 #define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM8EN) 1527 #define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM15EN) 1528 #define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM16EN) 1529 #define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM17EN) 1530 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI1EN) 1531 #define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI4EN) 1532 #define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI5EN) 1533 #define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_USART6EN) 1534 #define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI1EN) 1535 #define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI2EN) 1536 #define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI3EN) 1537 #define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_DFSDMEN) 1538 #define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_ADFSDMEN) 1539 #define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_FDCANEN) 1540 1541 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM1EN) 1542 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM8EN) 1543 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM15EN) 1544 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM16EN) 1545 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM17EN) 1546 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI1EN) 1547 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI4EN) 1548 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI5EN) 1549 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_USART6EN) 1550 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI1EN) 1551 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI2EN) 1552 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI3EN) 1553 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_DFSDMEN) 1554 #define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_ADFSDMEN) 1555 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_FDCANEN) 1556 1557 /** @brief Enable or disable the APB3 peripheral clock. 1558 * @note After reset, the peripheral clock (used for registers read/write access) 1559 * is disabled and the application software has to enable this clock before 1560 * using it. It shall be used to allocate a peripheral to the MCU. 1561 */ 1562 #define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM2EN) 1563 #define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM3EN) 1564 #define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM4EN) 1565 #define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM5EN) 1566 #define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_SAI4EN) 1567 #define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN) 1568 #define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN) 1569 #define __HAL_RCC_TMPSENS_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_TMPSENSEN) 1570 #define __HAL_RCC_PMBCTRL_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_PMBCTRLEN) 1571 #define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN) 1572 1573 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN) 1574 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM3EN) 1575 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM4EN) 1576 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM5EN) 1577 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_SAI4EN) 1578 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN) 1579 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN) 1580 #define __HAL_RCC_TMPSENS_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_TMPSENSEN) 1581 #define __HAL_RCC_PMBCTRL_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_PMBCTRLEN) 1582 #define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN) 1583 1584 /** @brief Enable or disable the APB4 peripheral clock. 1585 * @note After reset, the peripheral clock (used for registers read/write access) 1586 * is disabled and the application software has to enable this clock before 1587 * using it. It shall be used to allocate a peripheral to the MCU. 1588 */ 1589 #define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_LTDCEN) 1590 #define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_DSIEN) 1591 #define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_DDRPERFMEN) 1592 #define __HAL_RCC_IWDG2APB_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_IWDG2APBEN) 1593 #define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_USBPHYEN) 1594 #define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_STGENROEN) 1595 1596 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_LTDCEN) 1597 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_DSIEN) 1598 #define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_DDRPERFMEN) 1599 #define __HAL_RCC_IWDG2APB_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_IWDG2APBEN) 1600 #define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_USBPHYEN) 1601 #define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_STGENROEN) 1602 1603 /** @brief Enable or disable the APB5 peripheral clock. 1604 * @note After reset, the peripheral clock (used for registers read/write access) 1605 * is disabled and the application software has to enable this clock before 1606 * using it. It shall be used to allocate a peripheral to the MCU. 1607 */ 1608 #define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_SPI6EN) 1609 #define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_I2C4EN) 1610 #define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_I2C6EN) 1611 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_USART1EN) 1612 #define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_RTCAPBEN) 1613 #define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZC1EN) 1614 #define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZC2EN) 1615 #define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZPCEN) 1616 #define __HAL_RCC_IWDG1APB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_IWDG1APBEN) 1617 #define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_BSECEN) 1618 #define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_STGENEN) 1619 1620 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_SPI6EN) 1621 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C4EN) 1622 #define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C6EN) 1623 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_USART1EN) 1624 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_RTCAPBEN) 1625 #define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC1EN) 1626 #define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC2EN) 1627 #define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZPCEN) 1628 #define __HAL_RCC_IWDG1APB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_IWDG1APBEN) 1629 #define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENSETR_BSECEN) 1630 #define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENSETR_STGENEN) 1631 1632 /** @brief Enable or disable the AHB5 peripheral clock. 1633 * @note After reset, the peripheral clock (used for registers read/write access) 1634 * is disabled and the application software has to enable this clock before 1635 * using it. It shall be used to allocate a peripheral to the MCU. 1636 */ 1637 #define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_GPIOZEN) 1638 #if defined(CRYP1) 1639 #define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_CRYP1EN) 1640 #endif 1641 #define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_HASH1EN) 1642 #define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_RNG1EN) 1643 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_BKPSRAMEN) 1644 1645 #define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN) 1646 #if defined(CRYP1) 1647 #define __HAL_RCC_CRYP1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_CRYP1EN) 1648 #endif 1649 #define __HAL_RCC_HASH1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_HASH1EN) 1650 #define __HAL_RCC_RNG1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_RNG1EN) 1651 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_BKPSRAMEN) 1652 1653 /** @brief Enable or disable the AHB6 peripheral clock. 1654 * @note After reset, the peripheral clock (used for registers read/write access) 1655 * is disabled and the application software has to enable this clock before 1656 * using it. It shall be used to allocate a peripheral to the MCU. 1657 */ 1658 #define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_MDMAEN) 1659 #define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_GPUEN) 1660 #define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHCKEN) 1661 #define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHTXEN) 1662 #define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHRXEN) 1663 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHMACEN) 1664 #define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_FMCEN) 1665 #define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_QSPIEN) 1666 #define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC1EN) 1667 #define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC2EN) 1668 #define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_CRC1EN) 1669 #define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_USBHEN) 1670 1671 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_MDMAEN) 1672 #define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_GPUEN) 1673 #define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHCKEN) 1674 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHTXEN) 1675 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHRXEN) 1676 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHMACEN) 1677 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_FMCEN) 1678 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_QSPIEN) 1679 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC1EN) 1680 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC2EN) 1681 #define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_CRC1EN) 1682 #define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_USBHEN) 1683 1684 /** @brief Enable or disable the AHB2 peripheral clock. 1685 * @note After reset, the peripheral clock (used for registers read/write access) 1686 * is disabled and the application software has to enable this clock before 1687 * using it. It shall be used to allocate a peripheral to the MCU. 1688 */ 1689 #define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA1EN) 1690 #define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA2EN) 1691 #define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMAMUXEN) 1692 #define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_ADC12EN) 1693 #define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_USBOEN) 1694 #define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_SDMMC3EN) 1695 1696 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA1EN) 1697 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA2EN) 1698 #define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMAMUXEN) 1699 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_ADC12EN) 1700 #define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_USBOEN) 1701 #define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_SDMMC3EN) 1702 1703 /** @brief Enable or disable the AHB3 peripheral clock. 1704 * @note After reset, the peripheral clock (used for registers read/write access) 1705 * is disabled and the application software has to enable this clock before 1706 * using it. It shall be used to allocate a peripheral to the MCU. 1707 */ 1708 #define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_DCMIEN) 1709 #if defined(CRYP2) 1710 #define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRYP2EN) 1711 #endif 1712 #define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_HASH2EN) 1713 #define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_RNG2EN) 1714 #define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRC2EN) 1715 #define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_HSEMEN) 1716 #define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_IPCCEN) 1717 1718 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_DCMIEN) 1719 #if defined(CRYP2) 1720 #define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRYP2EN) 1721 #endif 1722 #define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HASH2EN) 1723 #define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_RNG2EN) 1724 #define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRC2EN) 1725 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HSEMEN) 1726 #define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_IPCCEN) 1727 1728 /** @brief Enable or disable the AHB4 peripheral clock. 1729 * @note After reset, the peripheral clock (used for registers read/write access) 1730 * is disabled and the application software has to enable this clock before 1731 * using it. It shall be used to allocate a peripheral to the MCU. 1732 */ 1733 #define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOAEN) 1734 #define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOBEN) 1735 #define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOCEN) 1736 #define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIODEN) 1737 #define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOEEN) 1738 #define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOFEN) 1739 #define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOGEN) 1740 #define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOHEN) 1741 #define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOIEN) 1742 #define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOJEN) 1743 #define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOKEN) 1744 1745 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOAEN) 1746 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOBEN) 1747 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOCEN) 1748 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIODEN) 1749 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOEEN) 1750 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOFEN) 1751 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOGEN) 1752 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOHEN) 1753 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOIEN) 1754 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOJEN) 1755 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOKEN) 1756 1757 1758 /** @brief Enable or disable the MLAHB peripheral clock. 1759 * @note After reset, the peripheral clock (used for registers read/write access) 1760 * is disabled and the application software has to enable this clock before 1761 * using it. It shall be used to allocate a peripheral to the MCU. 1762 */ 1763 #define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MP_MLAHBENSETR = RCC_MC_MLAHBENSETR_RETRAMEN) 1764 1765 #define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MP_MLAHBENCLRR = RCC_MC_MLAHBENCLRR_RETRAMEN) 1766 1767 /** @brief MCU reset 1768 * @note It generates a reset of the MCU core 1769 * MCURST bit is set by software, cleared by hardware when the reset 1770 * command is executed. 1771 */ 1772 #define __HAL_RCC_MCU_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MCURST) 1773 1774 /** @brief System reset 1775 * @note It generates a system reset 1776 * MPSYSRST bit is set by software, cleared by hardware. 1777 */ 1778 #define __HAL_RCC_SYS_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MPSYSRST) 1779 1780 1781 1782 1783 /** @brief Enable or disable the APB1 peripheral clock during CSLEEP mode. 1784 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1785 * power consumption. 1786 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1787 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1788 */ 1789 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM2LPEN) 1790 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM3LPEN) 1791 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM4LPEN) 1792 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM5LPEN) 1793 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM6LPEN) 1794 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM7LPEN) 1795 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM12LPEN) 1796 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM13LPEN) 1797 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM14LPEN) 1798 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_LPTIM1LPEN) 1799 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI2LPEN) 1800 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI3LPEN) 1801 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART2LPEN) 1802 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART3LPEN) 1803 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART4LPEN) 1804 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART5LPEN) 1805 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART7LPEN) 1806 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART8LPEN) 1807 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C1LPEN) 1808 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C2LPEN) 1809 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C3LPEN) 1810 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C5LPEN) 1811 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPDIFLPEN) 1812 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_CECLPEN) 1813 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_DAC12LPEN) 1814 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_MDIOSLPEN) 1815 1816 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM2LPEN) 1817 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM3LPEN) 1818 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM4LPEN) 1819 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM5LPEN) 1820 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM6LPEN) 1821 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM7LPEN) 1822 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM12LPEN) 1823 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM13LPEN) 1824 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM14LPEN) 1825 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_LPTIM1LPEN) 1826 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI2LPEN) 1827 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI3LPEN) 1828 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART2LPEN) 1829 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART3LPEN) 1830 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART4LPEN) 1831 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART5LPEN) 1832 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART7LPEN) 1833 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART8LPEN) 1834 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C1LPEN) 1835 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C2LPEN) 1836 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C3LPEN) 1837 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C5LPEN) 1838 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPDIFLPEN) 1839 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_CECLPEN) 1840 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_DAC12LPEN) 1841 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_MDIOSLPEN) 1842 1843 1844 /** @brief Enable or disable the APB2 peripheral clock during CSLEEP mode. 1845 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1846 * power consumption. 1847 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1848 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1849 */ 1850 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM1LPEN) 1851 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM8LPEN) 1852 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM15LPEN) 1853 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM16LPEN) 1854 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM17LPEN) 1855 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI1LPEN) 1856 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI4LPEN) 1857 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI5LPEN) 1858 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_USART6LPEN) 1859 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI1LPEN) 1860 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI2LPEN) 1861 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI3LPEN) 1862 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_DFSDMLPEN) 1863 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_ADFSDMLPEN) 1864 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_FDCANLPEN) 1865 1866 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM1LPEN) 1867 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM8LPEN) 1868 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM15LPEN) 1869 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM16LPEN) 1870 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM17LPEN) 1871 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI1LPEN) 1872 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI4LPEN) 1873 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI5LPEN) 1874 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_USART6LPEN) 1875 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI1LPEN) 1876 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI2LPEN) 1877 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI3LPEN) 1878 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_DFSDMLPEN) 1879 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_ADFSDMLPEN) 1880 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_FDCANLPEN) 1881 1882 1883 /** @brief Enable or disable the APB3 peripheral clock during CSLEEP mode. 1884 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1885 * power consumption. 1886 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1887 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1888 */ 1889 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM2LPEN) 1890 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM3LPEN) 1891 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM4LPEN) 1892 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM5LPEN) 1893 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_SAI4LPEN) 1894 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN) 1895 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN) 1896 #define __HAL_RCC_TMPSENS_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_TMPSENSLPEN) 1897 #define __HAL_RCC_PMBCTRL_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_PMBCTRLLPEN) 1898 1899 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN) 1900 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN) 1901 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM4LPEN) 1902 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM5LPEN) 1903 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SAI4LPEN) 1904 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN) 1905 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN) 1906 #define __HAL_RCC_TMPSENS_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_TMPSENSLPEN) 1907 #define __HAL_RCC_PMBCTRL_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_PMBCTRLLPEN) 1908 1909 /** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode. 1910 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1911 * power consumption. 1912 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1913 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1914 */ 1915 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_LTDCLPEN) 1916 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_DSILPEN) 1917 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_DDRPERFMLPEN) 1918 #define __HAL_RCC_IWDG2APB_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_IWDG2APBLPEN) 1919 #define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_USBPHYLPEN) 1920 #define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROLPEN) 1921 #define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROSTPEN) 1922 1923 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_LTDCLPEN) 1924 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DSILPEN) 1925 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DDRPERFMLPEN) 1926 #define __HAL_RCC_IWDG2APB_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_IWDG2APBLPEN) 1927 #define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_USBPHYLPEN) 1928 #define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROLPEN) 1929 #define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROSTPEN) 1930 1931 /** @brief Enable or disable the APB5 peripheral clock during CSLEEP mode. 1932 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1933 * power consumption. 1934 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1935 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1936 */ 1937 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_SPI6LPEN) 1938 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C4LPEN) 1939 #define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C6LPEN) 1940 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_USART1LPEN) 1941 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_RTCAPBLPEN) 1942 #define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC1LPEN) 1943 #define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC2LPEN) 1944 #define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZPCLPEN) 1945 #define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_BSECLPEN) 1946 #define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_STGENLPEN) 1947 1948 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_SPI6LPEN) 1949 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C4LPEN) 1950 #define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C6LPEN) 1951 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_USART1LPEN) 1952 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_RTCAPBLPEN) 1953 #define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC1LPEN) 1954 #define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC2LPEN) 1955 #define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZPCLPEN) 1956 #define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENSETR_BSECLPEN) 1957 #define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENSETR_STGENLPEN) 1958 1959 1960 /** @brief Enable or disable the AHB5 peripheral clock during CSLEEP mode. 1961 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1962 * power consumption. 1963 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1964 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1965 */ 1966 #define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_GPIOZLPEN) 1967 #if defined(CRYP1) 1968 #define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_CRYP1LPEN) 1969 #endif 1970 #define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_HASH1LPEN) 1971 #define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_RNG1LPEN) 1972 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_BKPSRAMLPEN) 1973 1974 #define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_GPIOZLPEN) 1975 #if defined(CRYP1) 1976 #define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_CRYP1LPEN) 1977 #endif 1978 #define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_HASH1LPEN) 1979 #define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_RNG1LPEN) 1980 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN) 1981 1982 1983 /** @brief Enable or disable the AHB6 peripheral clock during CSLEEP mode. 1984 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1985 * power consumption. 1986 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1987 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 1988 */ 1989 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_MDMALPEN) 1990 #define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_GPULPEN) 1991 #define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHCKLPEN) 1992 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHTXLPEN) 1993 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHRXLPEN) 1994 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHMACLPEN) 1995 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_FMCLPEN) 1996 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_QSPILPEN) 1997 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC1LPEN) 1998 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC2LPEN) 1999 #define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_CRC1LPEN) 2000 #define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_USBHLPEN) 2001 2002 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_MDMALPEN) 2003 #define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_GPULPEN) 2004 #define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHCKLPEN) 2005 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHTXLPEN) 2006 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHRXLPEN) 2007 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHMACLPEN) 2008 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_FMCLPEN) 2009 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_QSPILPEN) 2010 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC1LPEN) 2011 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC2LPEN) 2012 #define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_CRC1LPEN) 2013 #define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_USBHLPEN) 2014 2015 2016 /** @brief Enable or disable the AHB2 peripheral clock during CSLEEP mode. 2017 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2018 * power consumption. 2019 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2020 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2021 */ 2022 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA1LPEN) 2023 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA2LPEN) 2024 #define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMAMUXLPEN) 2025 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_ADC12LPEN) 2026 #define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_USBOLPEN) 2027 #define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_SDMMC3LPEN) 2028 2029 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA1LPEN) 2030 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA2LPEN) 2031 #define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMAMUXLPEN) 2032 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_ADC12LPEN) 2033 #define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_USBOLPEN) 2034 #define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_SDMMC3LPEN) 2035 2036 /** @brief Enable or disable the AHB3 peripheral clock during CSLEEP mode. 2037 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2038 * power consumption. 2039 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2040 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2041 */ 2042 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_DCMILPEN) 2043 #if defined(CRYP2) 2044 #define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRYP2LPEN) 2045 #endif 2046 #define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HASH2LPEN) 2047 #define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_RNG2LPEN) 2048 #define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRC2LPEN) 2049 #define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HSEMLPEN) 2050 #define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_IPCCLPEN) 2051 2052 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_DCMILPEN) 2053 #if defined(CRYP2) 2054 #define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRYP2LPEN) 2055 #endif 2056 #define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HASH2LPEN) 2057 #define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_RNG2LPEN) 2058 #define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRC2LPEN) 2059 #define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HSEMLPEN) 2060 #define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_IPCCLPEN) 2061 2062 2063 /** @brief Enable or disable the AHB4 peripheral clock during CSLEEP mode. 2064 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2065 * power consumption. 2066 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2067 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2068 */ 2069 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOALPEN) 2070 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOBLPEN) 2071 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOCLPEN) 2072 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIODLPEN) 2073 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOELPEN) 2074 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOFLPEN) 2075 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOGLPEN) 2076 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOHLPEN) 2077 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOILPEN) 2078 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOJLPEN) 2079 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOKLPEN) 2080 2081 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOALPEN) 2082 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOBLPEN) 2083 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOCLPEN) 2084 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIODLPEN) 2085 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOELPEN) 2086 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOFLPEN) 2087 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOGLPEN) 2088 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOHLPEN) 2089 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOILPEN) 2090 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOJLPEN) 2091 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOKLPEN) 2092 2093 /** @brief Enable or disable the AXI peripheral clock during CSLEEP mode. 2094 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2095 * power consumption. 2096 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2097 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2098 */ 2099 #define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AXIMLPENSETR = RCC_MC_AXIMLPENSETR_SYSRAMLPEN) 2100 2101 #define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AXIMLPENCLRR = RCC_MC_AXIMLPENCLRR_SYSRAMLPEN) 2102 2103 2104 /** @brief Enable or disable the MLAHB peripheral clock during CSLEEP mode. 2105 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2106 * power consumption. 2107 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2108 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2109 */ 2110 #define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MP_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_RETRAMLPEN) 2111 2112 #define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MP_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_RETRAMLPEN) 2113 2114 2115 2116 2117 2118 #else /* CORE_CA7 */ 2119 2120 2121 2122 2123 /** @brief Enable or disable the APB1 peripheral clock. 2124 * @note After reset, the peripheral clock (used for registers read/write access) 2125 * is disabled and the application software has to enable this clock before 2126 * using it. It shall be used to allocate a peripheral to the MCU. 2127 */ 2128 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM2EN) 2129 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM3EN) 2130 #define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM4EN) 2131 #define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM5EN) 2132 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM6EN) 2133 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM7EN) 2134 #define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM12EN) 2135 #define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM13EN) 2136 #define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM14EN) 2137 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_LPTIM1EN) 2138 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPI2EN) 2139 #define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPI3EN) 2140 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_USART2EN) 2141 #define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_USART3EN) 2142 #define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART4EN) 2143 #define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART5EN) 2144 #define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART7EN) 2145 #define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART8EN) 2146 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C1EN) 2147 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C2EN) 2148 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C3EN) 2149 #define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C5EN) 2150 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPDIFEN) 2151 #define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_CECEN) 2152 #define __HAL_RCC_WWDG1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_WWDG1EN) 2153 #define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_DAC12EN) 2154 #define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_MDIOSEN) 2155 2156 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM2EN) 2157 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM3EN) 2158 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM4EN) 2159 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM5EN) 2160 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM6EN) 2161 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM7EN) 2162 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM12EN) 2163 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM13EN) 2164 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM14EN) 2165 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_LPTIM1EN) 2166 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI2EN) 2167 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI3EN) 2168 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART2EN) 2169 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART3EN) 2170 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN) 2171 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART5EN) 2172 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART7EN) 2173 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART8EN) 2174 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C1EN) 2175 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C2EN) 2176 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C3EN) 2177 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C5EN) 2178 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPDIFEN) 2179 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_CECEN) 2180 #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_WWDG1EN) 2181 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_DAC12EN) 2182 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_MDIOSEN) 2183 2184 /** @brief Enable or disable the APB2 peripheral clock. 2185 * @note After reset, the peripheral clock (used for registers read/write access) 2186 * is disabled and the application software has to enable this clock before 2187 * using it. It shall be used to allocate a peripheral to the MCU. 2188 */ 2189 #define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM1EN) 2190 #define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM8EN) 2191 #define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM15EN) 2192 #define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM16EN) 2193 #define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM17EN) 2194 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI1EN) 2195 #define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI4EN) 2196 #define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI5EN) 2197 #define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_USART6EN) 2198 #define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI1EN) 2199 #define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI2EN) 2200 #define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI3EN) 2201 #define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_DFSDMEN) 2202 #define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_ADFSDMEN) 2203 #define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_FDCANEN) 2204 2205 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM1EN) 2206 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM8EN) 2207 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM15EN) 2208 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM16EN) 2209 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM17EN) 2210 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI1EN) 2211 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI4EN) 2212 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI5EN) 2213 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_USART6EN) 2214 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI1EN) 2215 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI2EN) 2216 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI3EN) 2217 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_DFSDMEN) 2218 #define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_ADFSDMEN) 2219 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_FDCANEN) 2220 2221 /** @brief Enable or disable the APB3 peripheral clock. 2222 * @note After reset, the peripheral clock (used for registers read/write access) 2223 * is disabled and the application software has to enable this clock before 2224 * using it. It shall be used to allocate a peripheral to the MCU. 2225 */ 2226 #define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM2EN) 2227 #define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM3EN) 2228 #define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM4EN) 2229 #define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM5EN) 2230 #define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SAI4EN) 2231 #define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN) 2232 #define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN) 2233 #define __HAL_RCC_TMPSENS_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_TMPSENSEN) 2234 #define __HAL_RCC_PMBCTRL_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_PMBCTRLEN) 2235 #define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN) 2236 2237 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN) 2238 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM3EN) 2239 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM4EN) 2240 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM5EN) 2241 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SAI4EN) 2242 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN) 2243 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN) 2244 #define __HAL_RCC_TMPSENS_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_TMPSENSEN) 2245 #define __HAL_RCC_PMBCTRL_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_PMBCTRLEN) 2246 #define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN) 2247 2248 /** @brief Enable or disable the APB4 peripheral clock. 2249 * @note After reset, the peripheral clock (used for registers read/write access) 2250 * is disabled and the application software has to enable this clock before 2251 * using it. It shall be used to allocate a peripheral to the MCU. 2252 */ 2253 #define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_LTDCEN) 2254 #define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_DSIEN) 2255 #define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_DDRPERFMEN) 2256 #define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_USBPHYEN) 2257 #define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_STGENROEN) 2258 2259 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_LTDCEN) 2260 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_DSIEN) 2261 #define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_DDRPERFMEN) 2262 #define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_USBPHYEN) 2263 #define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_STGENROEN) 2264 2265 /** @brief Enable or disable the APB5 peripheral clock. 2266 * @note After reset, the peripheral clock (used for registers read/write access) 2267 * is disabled and the application software has to enable this clock before 2268 * using it. It shall be used to allocate a peripheral to the MCU. 2269 */ 2270 #define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_SPI6EN) 2271 #define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_I2C4EN) 2272 #define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_I2C6EN) 2273 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_USART1EN) 2274 #define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_RTCAPBEN) 2275 #define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZC1EN) 2276 #define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZC2EN) 2277 #define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZPCEN) 2278 #define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_BSECEN) 2279 #define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_STGENEN) 2280 2281 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_SPI6EN) 2282 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C4EN) 2283 #define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C6EN) 2284 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_USART1EN) 2285 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_RTCAPBEN) 2286 #define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC1EN) 2287 #define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC2EN) 2288 #define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZPCEN) 2289 #define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENSETR_BSECEN) 2290 #define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENSETR_STGENEN) 2291 2292 /** @brief Enable or disable the AHB5 peripheral clock. 2293 * @note After reset, the peripheral clock (used for registers read/write access) 2294 * is disabled and the application software has to enable this clock before 2295 * using it. It shall be used to allocate a peripheral to the MCU. 2296 */ 2297 #define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_GPIOZEN) 2298 #if defined(CRYP1) 2299 #define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_CRYP1EN) 2300 #endif 2301 #define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_HASH1EN) 2302 #define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_RNG1EN) 2303 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_BKPSRAMEN) 2304 2305 #define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN) 2306 #if defined(CRYP1) 2307 #define __HAL_RCC_CRYP1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_CRYP1EN) 2308 #endif 2309 #define __HAL_RCC_HASH1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_HASH1EN) 2310 #define __HAL_RCC_RNG1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_RNG1EN) 2311 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_BKPSRAMEN) 2312 2313 /** @brief Enable or disable the AHB6 peripheral clock. 2314 * @note After reset, the peripheral clock (used for registers read/write access) 2315 * is disabled and the application software has to enable this clock before 2316 * using it. It shall be used to allocate a peripheral to the MCU. 2317 */ 2318 #define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_MDMAEN) 2319 #define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_GPUEN) 2320 #define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHCKEN) 2321 #define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHTXEN) 2322 #define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHRXEN) 2323 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHMACEN) 2324 #define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_FMCEN) 2325 #define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_QSPIEN) 2326 #define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC1EN) 2327 #define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC2EN) 2328 #define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_CRC1EN) 2329 #define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_USBHEN) 2330 2331 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_MDMAEN) 2332 #define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_GPUEN) 2333 #define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHCKEN) 2334 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHTXEN) 2335 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHRXEN) 2336 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHMACEN) 2337 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_FMCEN) 2338 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_QSPIEN) 2339 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC1EN) 2340 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC2EN) 2341 #define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_CRC1EN) 2342 #define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_USBHEN) 2343 2344 /** @brief Enable or disable the AHB2 peripheral clock. 2345 * @note After reset, the peripheral clock (used for registers read/write access) 2346 * is disabled and the application software has to enable this clock before 2347 * using it. It shall be used to allocate a peripheral to the MCU. 2348 */ 2349 #define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA1EN) 2350 #define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA2EN) 2351 #define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMAMUXEN) 2352 #define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_ADC12EN) 2353 #define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_USBOEN) 2354 #define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_SDMMC3EN) 2355 2356 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA1EN) 2357 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA2EN) 2358 #define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMAMUXEN) 2359 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_ADC12EN) 2360 #define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_USBOEN) 2361 #define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_SDMMC3EN) 2362 2363 /** @brief Enable or disable the AHB3 peripheral clock. 2364 * @note After reset, the peripheral clock (used for registers read/write access) 2365 * is disabled and the application software has to enable this clock before 2366 * using it. It shall be used to allocate a peripheral to the MCU. 2367 */ 2368 #define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_DCMIEN) 2369 #if defined(CRYP2) 2370 #define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRYP2EN) 2371 #endif 2372 #define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_HASH2EN) 2373 #define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_RNG2EN) 2374 #define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRC2EN) 2375 #define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_HSEMEN) 2376 #define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_IPCCEN) 2377 2378 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_DCMIEN) 2379 #if defined(CRYP2) 2380 #define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRYP2EN) 2381 #endif 2382 #define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HASH2EN) 2383 #define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_RNG2EN) 2384 #define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRC2EN) 2385 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HSEMEN) 2386 #define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_IPCCEN) 2387 2388 /** @brief Enable or disable the AHB4 peripheral clock. 2389 * @note After reset, the peripheral clock (used for registers read/write access) 2390 * is disabled and the application software has to enable this clock before 2391 * using it. It shall be used to allocate a peripheral to the MCU. 2392 */ 2393 #define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOAEN) 2394 #define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOBEN) 2395 #define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOCEN) 2396 #define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIODEN) 2397 #define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOEEN) 2398 #define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOFEN) 2399 #define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOGEN) 2400 #define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOHEN) 2401 #define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOIEN) 2402 #define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOJEN) 2403 #define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOKEN) 2404 2405 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOAEN) 2406 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOBEN) 2407 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOCEN) 2408 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIODEN) 2409 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOEEN) 2410 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOFEN) 2411 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOGEN) 2412 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOHEN) 2413 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOIEN) 2414 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOJEN) 2415 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOKEN) 2416 2417 /** @brief Enable or disable the AXI peripheral clock. 2418 * @note After reset, the peripheral clock (used for registers read/write access) 2419 * is disabled and the application software has to enable this clock before 2420 * using it. It shall be used to allocate a peripheral to the MCU. 2421 */ 2422 #define __HAL_RCC_SYSRAM_CLK_ENABLE() (RCC->MC_AXIMENSETR = RCC_MC_AXIMENSETR_SYSRAMEN) 2423 2424 #define __HAL_RCC_SYSRAM_CLK_DISABLE() (RCC->MC_AXIMENCLRR = RCC_MC_AXIMENCLRR_SYSRAMEN) 2425 2426 /** @brief Enable or disable the MLAHB peripheral clock. 2427 * @note After reset, the peripheral clock (used for registers read/write access) 2428 * is disabled and the application software has to enable this clock before 2429 * using it. It shall be used to allocate a peripheral to the MCU. 2430 */ 2431 #define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MC_MLAHBENSETR = RCC_MC_MLAHBENSETR_RETRAMEN) 2432 2433 #define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MC_MLAHBENCLRR = RCC_MC_MLAHBENCLRR_RETRAMEN) 2434 2435 2436 2437 2438 2439 2440 2441 /** @brief Enable or disable the APB1 peripheral clock during CSLEEP mode. 2442 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2443 * power consumption. 2444 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2445 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2446 */ 2447 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM2LPEN) 2448 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM3LPEN) 2449 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM4LPEN) 2450 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM5LPEN) 2451 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM6LPEN) 2452 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM7LPEN) 2453 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM12LPEN) 2454 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM13LPEN) 2455 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM14LPEN) 2456 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_LPTIM1LPEN) 2457 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI2LPEN) 2458 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI3LPEN) 2459 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART2LPEN) 2460 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART3LPEN) 2461 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART4LPEN) 2462 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART5LPEN) 2463 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART7LPEN) 2464 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART8LPEN) 2465 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C1LPEN) 2466 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C2LPEN) 2467 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C3LPEN) 2468 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C5LPEN) 2469 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPDIFLPEN) 2470 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_CECLPEN) 2471 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_WWDG1LPEN) 2472 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_DAC12LPEN) 2473 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_MDIOSLPEN) 2474 2475 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM2LPEN) 2476 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM3LPEN) 2477 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM4LPEN) 2478 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM5LPEN) 2479 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM6LPEN) 2480 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM7LPEN) 2481 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM12LPEN) 2482 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM13LPEN) 2483 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM14LPEN) 2484 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_LPTIM1LPEN) 2485 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI2LPEN) 2486 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI3LPEN) 2487 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART2LPEN) 2488 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART3LPEN) 2489 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART4LPEN) 2490 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART5LPEN) 2491 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART7LPEN) 2492 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART8LPEN) 2493 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C1LPEN) 2494 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C2LPEN) 2495 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C3LPEN) 2496 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C5LPEN) 2497 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPDIFLPEN) 2498 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_CECLPEN) 2499 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_WWDG1LPEN) 2500 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_DAC12LPEN) 2501 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_MDIOSLPEN) 2502 2503 2504 /** @brief Enable or disable the APB2 peripheral clock during CSLEEP mode. 2505 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2506 * power consumption. 2507 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2508 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2509 */ 2510 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM1LPEN) 2511 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM8LPEN) 2512 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM15LPEN) 2513 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM16LPEN) 2514 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM17LPEN) 2515 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI1LPEN) 2516 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI4LPEN) 2517 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI5LPEN) 2518 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_USART6LPEN) 2519 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI1LPEN) 2520 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI2LPEN) 2521 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI3LPEN) 2522 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_DFSDMLPEN) 2523 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_ADFSDMLPEN) 2524 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_FDCANLPEN) 2525 2526 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM1LPEN) 2527 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM8LPEN) 2528 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM15LPEN) 2529 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM16LPEN) 2530 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM17LPEN) 2531 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI1LPEN) 2532 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI4LPEN) 2533 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI5LPEN) 2534 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_USART6LPEN) 2535 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI1LPEN) 2536 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI2LPEN) 2537 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI3LPEN) 2538 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_DFSDMLPEN) 2539 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_ADFSDMLPEN) 2540 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_FDCANLPEN) 2541 2542 2543 /** @brief Enable or disable the APB3 peripheral clock during CSLEEP mode. 2544 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2545 * power consumption. 2546 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2547 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2548 */ 2549 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM2LPEN) 2550 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM3LPEN) 2551 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM4LPEN) 2552 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM5LPEN) 2553 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SAI4LPEN) 2554 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN) 2555 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN) 2556 #define __HAL_RCC_TMPSENS_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_TMPSENSLPEN) 2557 #define __HAL_RCC_PMBCTRL_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_PMBCTRLLPEN) 2558 2559 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN) 2560 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN) 2561 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM4LPEN) 2562 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM5LPEN) 2563 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SAI4LPEN) 2564 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN) 2565 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN) 2566 #define __HAL_RCC_TMPSENS_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_TMPSENSLPEN) 2567 #define __HAL_RCC_PMBCTRL_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_PMBCTRLLPEN) 2568 2569 /** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode. 2570 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2571 * power consumption. 2572 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2573 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2574 */ 2575 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_LTDCLPEN) 2576 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_DSILPEN) 2577 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_DDRPERFMLPEN) 2578 #define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_USBPHYLPEN) 2579 #define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROLPEN) 2580 #define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROSTPEN) 2581 2582 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_LTDCLPEN) 2583 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DSILPEN) 2584 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DDRPERFMLPEN) 2585 #define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_USBPHYLPEN) 2586 #define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROLPEN) 2587 #define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROSTPEN) 2588 2589 /** @brief Enable or disable the APB5 peripheral clock during CSLEEP mode. 2590 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2591 * power consumption. 2592 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2593 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2594 */ 2595 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_SPI6LPEN) 2596 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C4LPEN) 2597 #define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C6LPEN) 2598 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_USART1LPEN) 2599 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_RTCAPBLPEN) 2600 #define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC1LPEN) 2601 #define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC2LPEN) 2602 #define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZPCLPEN) 2603 #define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_BSECLPEN) 2604 #define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_STGENLPEN) 2605 2606 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_SPI6LPEN) 2607 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C4LPEN) 2608 #define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C6LPEN) 2609 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_USART1LPEN) 2610 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_RTCAPBLPEN) 2611 #define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC1LPEN) 2612 #define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC2LPEN) 2613 #define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZPCLPEN) 2614 #define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENSETR_BSECLPEN) 2615 #define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENSETR_STGENLPEN) 2616 2617 2618 /** @brief Enable or disable the AHB5 peripheral clock during CSLEEP mode. 2619 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2620 * power consumption. 2621 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2622 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2623 */ 2624 #define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_GPIOZLPEN) 2625 #if defined(CRYP1) 2626 #define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_CRYP1LPEN) 2627 #endif 2628 #define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_HASH1LPEN) 2629 #define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_RNG1LPEN) 2630 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_BKPSRAMLPEN) 2631 2632 #define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_GPIOZLPEN) 2633 #if defined(CRYP1) 2634 #define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_CRYP1LPEN) 2635 #endif 2636 #define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_HASH1LPEN) 2637 #define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_RNG1LPEN) 2638 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN) 2639 2640 2641 /** @brief Enable or disable the AHB6 peripheral clock during CSLEEP mode. 2642 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2643 * power consumption. 2644 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2645 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2646 */ 2647 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_MDMALPEN) 2648 #define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_GPULPEN) 2649 #define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHCKLPEN) 2650 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHTXLPEN) 2651 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHRXLPEN) 2652 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHMACLPEN) 2653 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_FMCLPEN) 2654 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_QSPILPEN) 2655 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC1LPEN) 2656 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC2LPEN) 2657 #define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_CRC1LPEN) 2658 #define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_USBHLPEN) 2659 2660 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_MDMALPEN) 2661 #define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_GPULPEN) 2662 #define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHCKLPEN) 2663 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHTXLPEN) 2664 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHRXLPEN) 2665 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHMACLPEN) 2666 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_FMCLPEN) 2667 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_QSPILPEN) 2668 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC1LPEN) 2669 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC2LPEN) 2670 #define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_CRC1LPEN) 2671 #define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_USBHLPEN) 2672 2673 2674 /** @brief Enable or disable the AHB2 peripheral clock during CSLEEP mode. 2675 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2676 * power consumption. 2677 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2678 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2679 */ 2680 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA1LPEN) 2681 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA2LPEN) 2682 #define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMAMUXLPEN) 2683 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_ADC12LPEN) 2684 #define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_USBOLPEN) 2685 #define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_SDMMC3LPEN) 2686 2687 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA1LPEN) 2688 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA2LPEN) 2689 #define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMAMUXLPEN) 2690 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_ADC12LPEN) 2691 #define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_USBOLPEN) 2692 #define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_SDMMC3LPEN) 2693 2694 /** @brief Enable or disable the AHB3 peripheral clock during CSLEEP mode. 2695 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2696 * power consumption. 2697 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2698 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2699 */ 2700 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_DCMILPEN) 2701 #if defined(CRYP2) 2702 #define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRYP2LPEN) 2703 #endif 2704 #define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HASH2LPEN) 2705 #define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_RNG2LPEN) 2706 #define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRC2LPEN) 2707 #define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HSEMLPEN) 2708 #define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_IPCCLPEN) 2709 2710 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_DCMILPEN) 2711 #if defined(CRYP2) 2712 #define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRYP2LPEN) 2713 #endif 2714 #define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HASH2LPEN) 2715 #define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_RNG2LPEN) 2716 #define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRC2LPEN) 2717 #define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HSEMLPEN) 2718 #define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_IPCCLPEN) 2719 2720 2721 /** @brief Enable or disable the AHB4 peripheral clock during CSLEEP mode. 2722 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2723 * power consumption. 2724 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2725 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2726 */ 2727 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOALPEN) 2728 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOBLPEN) 2729 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOCLPEN) 2730 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIODLPEN) 2731 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOELPEN) 2732 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOFLPEN) 2733 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOGLPEN) 2734 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOHLPEN) 2735 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOILPEN) 2736 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOJLPEN) 2737 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOKLPEN) 2738 2739 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOALPEN) 2740 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOBLPEN) 2741 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOCLPEN) 2742 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIODLPEN) 2743 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOELPEN) 2744 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOFLPEN) 2745 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOGLPEN) 2746 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOHLPEN) 2747 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOILPEN) 2748 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOJLPEN) 2749 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOKLPEN) 2750 2751 /** @brief Enable or disable the AXI peripheral clock during CSLEEP mode. 2752 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2753 * power consumption. 2754 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2755 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2756 */ 2757 #define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MC_AXIMLPENSETR = RCC_MC_AXIMLPENSETR_SYSRAMLPEN) 2758 2759 #define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MC_AXIMLPENCLRR = RCC_MC_AXIMLPENCLRR_SYSRAMLPEN) 2760 2761 2762 /** @brief Enable or disable the MLAHB peripheral clock during CSLEEP mode. 2763 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2764 * power consumption. 2765 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2766 * @note By default, all peripheral clocks are enabled during CSLEEP mode. 2767 */ 2768 #define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_RETRAMLPEN) 2769 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM1LPEN) 2770 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM2LPEN) 2771 #define __HAL_RCC_SRAM34_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM34LPEN) 2772 2773 #define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_RETRAMLPEN) 2774 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM1LPEN) 2775 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM2LPEN) 2776 #define __HAL_RCC_SRAM34_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM3LPEN) 2777 2778 /** @brief Enable or disable the AHB6 peripheral clock during (C)STOP mode. 2779 * @note Peripheral clock gating in (C)STOP mode can be used to further reduce 2780 * power consumption. 2781 * @note It is possible to control the gating of clocks coming from PADs ETH_RX_CLK and ETH_TX_CLK 2782 * in CSTOP and STOP modes via the ETHSTPEN bit 2783 */ 2784 #define __HAL_RCC_ETH1CK_CLK_STOP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHSTPEN) 2785 2786 #define __HAL_RCC_ETH1CK_CLK_STOP_DISABLE() (RCC->MC_AHB6LPENSETR) = (RCC_MC_AHB6LPENCLRR_ETHSTPEN) 2787 2788 #endif /* !CORE_CA7 */ 2789 2790 /** @brief Macro to test if HSE oscillator is used somewhere in the core system 2791 * @note HAL driver does not ensure these clocks are used by peripherals, it's 2792 * up to user code 2793 */ 2794 #define IS_HSE_IN_USE() \ 2795 (( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) ) || \ 2796 ((__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY)) || \ 2797 ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY)) || \ 2798 \ 2799 ((__HAL_RCC_GET_PLL12_SOURCE() == RCC_PLL12SOURCE_HSE) && \ 2800 ( __HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) || __HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) )) || \ 2801 \ 2802 ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_HSE) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \ 2803 \ 2804 ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_HSE) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) ))? 1 : 0) 2805 2806 /** @brief Macro to test if HSI oscillator is used somewhere in the core system 2807 * @note HAL driver does not ensure these clocks are used by peripherals, it's 2808 * up to user code 2809 */ 2810 #define IS_HSI_IN_USE() \ 2811 (( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) ) || \ 2812 ((__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) ) || \ 2813 ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) ) || \ 2814 \ 2815 ((__HAL_RCC_GET_PLL12_SOURCE() == RCC_PLL12SOURCE_HSI) && \ 2816 ( __HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) || __HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) )) || \ 2817 \ 2818 ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_HSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \ 2819 \ 2820 ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_HSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) ))? 1 : 0) 2821 2822 2823 /** @brief Macro to test if CSI oscillator is used somewhere in the core system 2824 * @note HAL driver does not ensure these clocks are used by peripherals, it's 2825 * up to user code 2826 */ 2827 #define IS_CSI_IN_USE() \ 2828 (( ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \ 2829 ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY)) || \ 2830 \ 2831 ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY)))? 1 : 0) 2832 2833 /** @brief Macros to test if PLLx are used on the Core and buses clock generation system (MPU, MCU or AXIS blocks) 2834 * @note HAL driver does not ensure these clocks are used by peripherals, it's up to user code */ 2835 #define __IS_PLL1_IN_USE() \ 2836 ( ( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_PLL1) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY)) || \ 2837 ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_MPUDIV) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY)) ) ? 1:0) 2838 2839 #define __IS_PLL2_IN_USE() \ 2840 ( ( (__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_PLL2) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) )? 1:0) 2841 2842 #define __IS_PLL3_IN_USE() \ 2843 ( ( (__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_PLL3) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) )? 1:0) 2844 2845 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 2846 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 2847 * It is used (enabled by hardware) as system clock source after startup 2848 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 2849 * of the HSE used directly or indirectly as system clock (if the Clock 2850 * Security System CSS is enabled). 2851 * @note HSI can not be stopped if it is used as system clock source. In this case, 2852 * you have to select another source of the system clock then stop the HSI. 2853 * @note After enabling the HSI, the application software should wait on HSIRDY 2854 * flag to be set indicating that HSI clock is stable and can be used as 2855 * system clock source. 2856 * This parameter can be: ENABLE or DISABLE. 2857 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2858 * clock cycles. 2859 */ 2860 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSION) 2861 #define __HAL_RCC_HSI_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSION) 2862 2863 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 2864 * @note The calibration is used to compensate for the variations in voltage 2865 * and temperature that influence the frequency of the internal HSI RC. 2866 * @param __HSICalibrationValue__: specifies the calibration trimming value 2867 * HSITRIM. HSITRIM represents a signed value. HSITRIM field is added 2868 * to the engineering Option Bytes loaded during reset phase 2869 * (bsec_hsi_cal[11:0]) in order to form the calibration trimming value. 2870 * HSICAL[11:0] = bsec_hsi_cal[11:0] + HSITRIM[6:0] 2871 * This parameter must be a number between 0 and 0x7F: 2872 * 0x40: bsec_hsi_cal[11:0] - 64 2873 * 0x41: bsec_hsi_cal[11:0] - 63 2874 * ... 2875 * 0x0: bsec_hsi_cal[11:0] (default after reset) 2876 * ... 2877 * 0x3E: bsec_hsi_cal[11:0] + 62 2878 * 0x3F: bsec_hsi_cal[11:0] + 63 2879 */ 2880 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ 2881 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, \ 2882 (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos) 2883 2884 2885 /** 2886 * @brief Macro to configure HSI clock divider 2887 * @note Set and reset by software to control the HSI clock division factor. 2888 * @note It is not allowed to change HSIDIV, if the HSI is currently used as 2889 * reference clock for a PLL. 2890 * @note If TZEN = 1, this parameter can only be modified in secure mode. 2891 * @note Write access to this register is not allowed during the clock restore sequence 2892 * @note The application can check if the new division factor is taken into 2893 * account by reading back the HSIDIVRDY flag 2894 * 2895 * @param __RCC_HSIDIV__: specifies the HSI division factor 2896 * This parameter can be one of the following values: 2897 * @arg RCC_HSI_DIV1: Division by 1, ck_hsi(_ker) = 64 MHz (default after reset) 2898 * @arg RCC_HSI_DIV2: Division by 2, ck_hsi(_ker) = 32 MHz 2899 * @arg RCC_HSI_DIV4: Division by 4, ck_hsi(_ker) = 16 MHz 2900 * @arg RCC_HSI_DIV8: Division by 8, ck_hsi(_ker) = 8 MHz 2901 */ 2902 #define __HAL_RCC_HSI_DIV(__RCC_HSIDIV__) \ 2903 do{ MODIFY_REG( RCC->HSICFGR, RCC_HSICFGR_HSIDIV , __RCC_HSIDIV__ );\ 2904 } while(0) 2905 2906 /** @brief Macro to get the HSI clock division factor. 2907 * @retval The HSI clock division factor. The returned value can be one 2908 * of the following: 2909 * - RCC_HSI_DIV1: Division by 1, ck_hsi(_ker) = 64 MHz (default after reset) 2910 * - RCC_HSI_DIV2: Division by 2, ck_hsi(_ker) = 32 MHz 2911 * - RCC_HSI_DIV4: Division by 4, ck_hsi(_ker) = 16 MHz 2912 * - RCC_HSI_DIV8: Division by 8, ck_hsi(_ker) = 8 MHz 2913 */ 2914 #define __HAL_RCC_GET_HSI_DIV() ((uint32_t)(RCC->HSICFGR & RCC_HSICFGR_HSIDIV )) 2915 2916 2917 /** 2918 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2919 * in STOP mode to be quickly available as kernel clock. 2920 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2921 * speed because of the HSI startup time. 2922 * @note The enable of this function has not effect on the HSION bit. 2923 * This parameter can be: ENABLE or DISABLE. 2924 * @retval None 2925 */ 2926 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSIKERON) 2927 #define __HAL_RCC_HSISTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSIKERON) 2928 2929 2930 /** 2931 * @brief Macros to enable or disable the Internal oscillator (CSI). 2932 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. 2933 * It is used (enabled by hardware) as system clock source after 2934 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 2935 * of failure of the HSE used directly or indirectly as system clock 2936 * (if the Clock Security System CSS is enabled). 2937 * @note CSI can not be stopped if it is used as system clock source. 2938 * In this case, you have to select another source of the system 2939 * clock then stop the CSI. 2940 * @note After enabling the CSI, the application software should wait on 2941 * CSIRDY flag to be set indicating that CSI clock is stable and can 2942 * be used as system clock source. 2943 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator 2944 * clock cycles. 2945 */ 2946 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_CSION) 2947 #define __HAL_RCC_CSI_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENSETR_CSION) 2948 2949 /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. 2950 * @note The calibration is used to compensate for the variations in voltage 2951 * and temperature that influence the frequency of the internal CSI RC. 2952 * Please refer to the datasheet of the product for for more details on how to 2953 * calibrate the CSI. 2954 * @param __CSICalibrationValue__: specifies the calibration trimming value. 2955 * This parameter must be a number between 0 and 0x1F. 2956 */ 2957 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 2958 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, \ 2959 (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos) 2960 2961 /** 2962 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (CSI) 2963 * in STOP mode to be quickly available as kernel clock. 2964 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication 2965 * speed because of the CSI startup time. 2966 * @note The enable of this function has not effect on the CSION bit. 2967 * This parameter can be: ENABLE or DISABLE. 2968 * @retval None 2969 */ 2970 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_CSIKERON) 2971 #define __HAL_RCC_CSISTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_CSIKERON) 2972 2973 2974 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 2975 * @note After enabling the LSI, the application software should wait on 2976 * LSIRDY flag to be set indicating that LSI clock is stable and can 2977 * be used to clock the IWDG and/or the RTC. 2978 * @note LSI can not be disabled if the IWDG is running. 2979 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 2980 * clock cycles. 2981 */ 2982 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION) 2983 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION) 2984 2985 2986 2987 2988 /** @brief Macro to configure the Minimum Reset Duration 2989 * @note Set and reset by software. They define the minimum guaranteed 2990 * duration of the NRST low pulse. The LSI oscillator is automatically 2991 * enabled when needed by the RPCTL. 2992 * @note 00000: NRST low pulse duration is guaranteed by the pulse stretcher 2993 * of the PAD. The RPCTL is bypassed (default after reset) 2994 * 00010: The guaranteed NRST low pulse duration is about 2 ms (2 x 32 ck_lsi cycles), 2995 * ... 2996 * 11111: The guaranteed NRST low pulse duration is about 31 ms (31 x 32 ck_lsi cycles). 2997 */ 2998 #define __HAL_RCC_MRD_CONFIG(__DURATION__) \ 2999 do { MODIFY_REG(RCC->RDLSICR, RCC_RDLSICR_MRD, \ 3000 (uint32_t)(__DURATION__) << RCC_RDLSICR_MRD_Pos) \ 3001 HAL_Delay(1); \ 3002 } while(0) 3003 3004 3005 3006 /** 3007 * @brief Macro (depricated) to configure the External High Speed oscillator (HSE). 3008 * @note Macro name is kept to mantain compatibility and it is mapped on 3009 * HAL_RCC_HSEConfig function which replaces macro and should be used 3010 * instead. 3011 * @note HSE state can not be changed if it is used directly or through the 3012 * PLL as system clock. In this case, you have to select another source 3013 * of the system clock then change the HSE state (ex. disable it). 3014 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 3015 * @note This function reset the CSSON bit, so if the clock security system(CSS) 3016 * was previously enabled you have to enable it again after calling this 3017 * function. 3018 * @param __STATE__: specifies the new state of the HSE. 3019 * This parameter can be one of the following values: 3020 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator 3021 * @arg RCC_HSE_ON: turn ON the HSE oscillator using an external 3022 * crystal/ceramic resonator 3023 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock 3024 * using a low-swing analog signal provided to OSC_IN 3025 * @arg RCC_HSE_BYPASS_DIG: HSE oscillator bypassed with external 3026 * clock using a full-swing digital signal provided to OSC_IN 3027 */ 3028 #define __HAL_RCC_HSE_CONFIG(__STATE__) HAL_RCC_HSEConfig(__STATE__) 3029 3030 3031 /** 3032 * @brief Macros to enable or disable the force of the External High Speed oscillator (HSE) 3033 * in STOP mode to be quickly available as kernel clock. 3034 * @note Keeping the HSE ON in STOP mode allows to avoid slowing down the communication 3035 * speed because of the HSE startup time. 3036 * @note The enable of this function has not effect on the HSION bit. 3037 * This parameter can be: ENABLE or DISABLE. 3038 * @retval None 3039 */ 3040 #define __HAL_RCC_HSESTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEKERON) 3041 #define __HAL_RCC_HSESTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEKERON) 3042 3043 3044 /** 3045 * @brief Macro (depricated) to configure the External Low Speed oscillator (LSE). 3046 * @note Macro name is kept to mantain compatibility and it is mapped on 3047 * HAL_RCC_LSEConfig function which replaces macro and should be used 3048 * instead. 3049 * @note As the LSE is in the Backup domain and write access is denied to 3050 * this domain after reset, you have to enable write access using 3051 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3052 * (to be done once after reset). 3053 * @param __STATE__: specifies the new state of the LSE. 3054 * This parameter can be a value of @ref RCC_LSE_Config 3055 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator 3056 * @arg RCC_LSE_ON: turn ON the LSE oscillator using an external 3057 * crystal/ceramic resonator 3058 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock 3059 * using a low-swing analog signal provided to OSC32_IN 3060 * @arg RCC_LSE_BYPASS_DIG: LSE oscillator bypassed with external clock using 3061 * a full-swing digital signal provided to OSC32_IN 3062 */ 3063 #define __HAL_RCC_LSE_CONFIG(__STATE__) HAL_RCC_LSEConfig(__STATE__) 3064 3065 3066 /** 3067 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. 3068 * @note As the LSE is in the Backup domain and write access is denied to 3069 * this domain after reset, you have to enable write access using 3070 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3071 * (to be done once after reset). 3072 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 3073 * This parameter can be one of the following values: 3074 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability (default after backup domain reset) 3075 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. 3076 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. 3077 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. 3078 * @retval None 3079 */ 3080 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 3081 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 3082 3083 3084 /** @brief Macro to get the LSE driving capability. 3085 * @retval The LSE Driving capability . The returned value can be one 3086 * of the following: 3087 * - RCC_LSEDRIVE_LOW: LSE oscillator low drive capability (default after backup domain reset) 3088 * - RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. 3089 * - RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. 3090 * - RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. 3091 */ 3092 #define __HAL_RCC_GET_LSEDRIVE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV))) 3093 3094 /** @brief Macros to enable or disable the the RTC clock. 3095 * @note These macros must be used only after the RTC clock source was selected. 3096 */ 3097 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN) 3098 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN) 3099 3100 /** @brief Macros to configure the RTC clock (RTCCLK). 3101 * @note As the RTC clock configuration bits are in the Backup domain and write 3102 * access is protected to this domain after reset, you have to enable write 3103 * access using the Power Backup Access macro ( DBP bit in the PWR control 3104 * register 1 PWR_CR1 has to be set to 1) before to configure 3105 * the RTC clock source (to be done once after reset). 3106 * @note Once the RTC clock is configured it can't be changed unless the 3107 * Backup domain is reset using __HAL_RCC_BACKUPRESET_RELEASE() macro, or by 3108 * a Power On Reset (POR). 3109 * @param __RTCCLKSource__: specifies the RTC clock source. 3110 * This parameter can be one of the following values: 3111 * @arg RCC_RTCCLKSOURCE_OFF: No clock (default after backup domain reset) 3112 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 3113 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 3114 * @arg RCC_RTCCLKSOURCE_HSE_DIV: HSE clock divided by RTCDIV value is used as RTC clock 3115 * 3116 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 3117 * work in STOP and STANDBY modes, and can be used as wakeup source. 3118 * However, when the HSE clock is used as RTC clock source, the RTC 3119 * cannot be used in STOP and STANDBY modes. 3120 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 3121 * RTC clock source). 3122 */ 3123 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \ 3124 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSRC, (__RTCCLKSource__)) 3125 3126 3127 /** @brief Macro to get the clock source used as RTC clock. 3128 * @retval The clock source used as RTC clock. The returned value can be one 3129 * of the following: 3130 * - RCC_RTCCLKSOURCE_OFF: No clock (default after backup domain reset) 3131 * - RCC_RTCCLKSOURCE_LSE: LSE used as RTC clock. 3132 * - RCC_RTCCLKSOURCE_LSI: LSI used as RTC clock. 3133 * - RCC_RTCCLKSOURCE_HSE_DIV: HSE clock divided by RTCDIV value is used as RTC clock 3134 */ 3135 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSRC))) 3136 3137 3138 /** @brief Macros to force or release the Backup domain reset. 3139 * @note This function resets the RTC peripheral (including the backup registers) 3140 * 3141 * @note The BKPSRAM and RETRAM are not affected 3142 */ 3143 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 3144 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 3145 3146 3147 /** @brief Macros to enable or disable the PLL1. 3148 * @note After enabling the main PLL, the application software should wait on 3149 * PLLRDY flag to be set indicating that PLL clock is stable and can 3150 * be used as system clock source. 3151 * @note The PLL1 can not be disabled if it is used as MPU clock source 3152 * @note The PLL1 is disabled by hardware when entering STOP and STANDBY modes. 3153 */ 3154 3155 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON ) 3156 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON) 3157 3158 /** 3159 * @brief Enables or disables each clock output 3160 * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL, 3161 * with the exception of ck_pll_p cannot be stopped if used as MPU Clock 3162 * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputed 3163 * This parameter can be one of the following values: 3164 * @arg RCC_PLL1_DIVP 3165 * @arg RCC_PLL1_DIVQ 3166 * @arg RCC_PLL1_DIVR 3167 * @retval None 3168 */ 3169 3170 #define __HAL_RCC_PLL1CLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLL1CR, __RCC_PLL1ClockOut__ ) 3171 3172 #define __HAL_RCC_PLL1CLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLL1CR, __RCC_PLL1ClockOut__ ) 3173 3174 3175 /** 3176 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 3177 * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL1 3178 * @retval None 3179 */ 3180 3181 #define __HAL_RCC_PLL1FRACV_ENABLE() SET_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE) 3182 3183 #define __HAL_RCC_PLL1FRACV_DISABLE() CLEAR_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE) 3184 3185 3186 3187 /** 3188 * @brief Macro to configure PLL1 and PLL2 clock source 3189 * @note This function must be used only when the PLLs are disabled. 3190 * 3191 * @param __RCC_PLL12SOURCE__: specifies the PLL1 and PLL2 entry clock source. 3192 * This parameter can be one of the following values: 3193 * @arg RCC_PLL12SOURCE_HSI: HSI oscillator clock selected as PLL1 and PLL2 clock entry 3194 * @arg RCC_PLL12SOURCE_HSE: HSE oscillator clock selected as PLL1 and PLL2 clock entry 3195 * @arg RCC_PLL12SOURCE_OFF: No clock send to DIVMx divider and PLLs 3196 * @note This clock source (__RCC_PLL12Source__) is common for the PLL1 and PLL2 . 3197 * @retval None 3198 */ 3199 #define __HAL_RCC_PLL12_SOURCE(__RCC_PLL12SOURCE__ ) \ 3200 do{ MODIFY_REG( RCC->RCK12SELR, RCC_RCK12SELR_PLL12SRC, __RCC_PLL12SOURCE__ ); \ 3201 } while(0) 3202 3203 /** @brief Macro to get the clock source used as PLL1 and PLL2 clocks. 3204 * @retval The clock source used as PLL1 and PLL1 clocks. The returned value can be one 3205 * of the following: 3206 * - RCC_PLL12SOURCE_HSI: HSI used as PLL12 clock. 3207 * - RCC_PLL12SOURCE_HSE: HSE used as PLL12 clock. 3208 * - RCC_PLL12SOURCE_OFF: PLL1 and PLL2 clock is gated. 3209 */ 3210 #define __HAL_RCC_GET_PLL12_SOURCE() ((uint32_t)(RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRC)) 3211 3212 /** 3213 * @brief Macro to configure PLL1 multiplication and division factors. 3214 * @note This function must be used only when the PLL1 is disabled. 3215 * 3216 * @param __PLLM1__: specifies the division factor for PLL VCO input clock 3217 * This parameter must be a number between 1 and 64 3218 * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input 3219 * frequency ranges from 8 to 16 MHz 3220 * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock 3221 * This parameter must be a number between 25 and 100 3222 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3223 * output frequency is between 800 to 1600 MHz 3224 * @param __PLLP1__: specifies the division factor for the PLL1 P output 3225 * This parameter must be a number in the range 1 to 128 3226 * @param __PLLQ1__: specifies the division factor for for the PLL1 Q output 3227 * This parameter must be in the range 1 to 128 3228 * @param __PLLR1__: specifies the division factor for for the PLL1 R output 3229 * This parameter must be in the range 1 to 128 3230 * @retval None 3231 */ 3232 #define __HAL_RCC_PLL1_CONFIG(__PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \ 3233 do{ MODIFY_REG( RCC->PLL1CFGR1, (RCC_PLL1CFGR1_DIVN | RCC_PLL1CFGR1_DIVM1) , \ 3234 ( (__PLLN1__ - 1U) | ( (__PLLM1__ - 1U) << 16U) ) ); \ 3235 MODIFY_REG( RCC->PLL1CFGR2, (RCC_PLL1CFGR2_DIVP | RCC_PLL1CFGR2_DIVQ | RCC_PLL1CFGR2_DIVR), \ 3236 ( (__PLLP1__ - 1U) | ( (__PLLQ1__ - 1U) <<8U ) | ( (__PLLR1__ - 1U) <<16U) )); \ 3237 } while(0) 3238 3239 3240 3241 /** 3242 * @brief Macro to configure the PLL1 clock Fractional Part Of The Multiplication Factor 3243 * 3244 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 3245 * 3246 * @param __RCC_PLL1FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL1 VCO 3247 * It should be a value between 0 and 8191 ((2^13)-1) 3248 * @note Warning: the software has to set correctly these bits to insure that the VCO 3249 * output frequency is between its valid frequency range, which is: 800 to 1600 MHz 3250 * @retval None 3251 */ 3252 #define __HAL_RCC_PLL1FRACV_CONFIG(__RCC_PLL1FRACV__) \ 3253 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACV,\ 3254 (uint32_t)(__RCC_PLL1FRACV__) << RCC_PLL1FRACR_FRACV_Pos) 3255 3256 3257 /** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL1 3258 */ 3259 #define __HAL_RCC_PLL1_SSMODE_ENABLE() SET_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL) 3260 3261 #define __HAL_RCC_PLL1_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL) 3262 3263 3264 /** @brief Macro to config the PLL1 Clock Spreading Generator 3265 * @param __RCC_PLL1_MOD_PER__: Modulation Period Adjustment for PLL1 3266 * This parameter must have a value between 1 and 8191 3267 * 3268 * @param __RCC_PLL1_TPDFN_DIS__: Dithering TPDF noise control 3269 * This parameter can be one of the following values: 3270 * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3271 * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled 3272 3273 * @param __RCC_PLL1_RPDFN_DIS__: Dithering TPDF noise control 3274 * This parameter can be one of the following values: 3275 * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3276 * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled 3277 * 3278 * 3279 * @param __RCC_PLL1_SSCG_MODE__: Spread spectrum clock generator mode 3280 * This parameter can be one of the following values: 3281 * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset) 3282 * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected 3283 * 3284 * @param __RCC_PLL1_INC_STEP__: Modulation Depth Adjustment for PLL1 3285 * This parameter must have a value between 1 and 32767 3286 * @note MOD_PER x INC_STEP shall not exceed (2^15)-1 3287 * @retval None 3288 */ 3289 #define __HAL_RCC_PLL1CSGCONFIG(__RCC_PLL1_MOD_PER__, __RCC_PLL1_TPDFN_DIS__, __RCC_PLL1_RPDFN_DIS__, \ 3290 __RCC_PLL1_SSCG_MODE__, __RCC_PLL1_INC_STEP__ ) \ 3291 do{ MODIFY_REG( RCC->PLL1CSGR, (RCC_PLL1CSGR_MOD_PER | RCC_PLL1CSGR_TPDFN_DIS | RCC_PLL1CSGR_RPDFN_DIS | \ 3292 RCC_PLL1CSGR_SSCG_MODE | RCC_PLL1CSGR_INC_STEP) , \ 3293 (__RCC_PLL1_MOD_PER__ | __RCC_PLL1_TPDFN_DIS__ | __RCC_PLL1_RPDFN_DIS__ | \ 3294 __RCC_PLL1_SSCG_MODE__ | (__RCC_PLL1_INC_STEP__ << RCC_PLL1CSGR_INC_STEP_Pos)) ) ; \ 3295 } while(0) 3296 3297 3298 3299 /** @brief Macros to enable or disable the PLL2. 3300 * @note After enabling the main PLL, the application software should wait on 3301 * PLLRDY flag to be set indicating that PLL clock is stable and can 3302 * be used as system clock source. 3303 * @note The PLL2 can not be disabled if it is used as MPU clock source 3304 * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. 3305 */ 3306 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON ) 3307 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON) 3308 3309 /** 3310 * @brief Enables or disables each clock output 3311 * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL 3312 * @param __RCC_PLL2ClockOut__: specifies the PLL clock to be outputed 3313 * This parameter can be one of the following values: 3314 * @arg RCC_PLL2_DIVP 3315 * @arg RCC_PLL2_DIVQ 3316 * @arg RCC_PLL2_DIVR 3317 * @retval None 3318 */ 3319 3320 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLL2CR, __RCC_PLL2ClockOut__ ) 3321 3322 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLL2CR, __RCC_PLL2ClockOut__ ) 3323 3324 /** 3325 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 3326 * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL2 3327 * @retval None 3328 */ 3329 3330 #define __HAL_RCC_PLL2FRACV_ENABLE() SET_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE) 3331 3332 #define __HAL_RCC_PLL2FRACV_DISABLE() CLEAR_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE) 3333 3334 /** 3335 * @brief Macro to configure PLL2 multiplication and division factors. 3336 * @note This function must be used only when the PLL2 is disabled. 3337 * 3338 * @param __PLLM2__: specifies the division factor for PLL VCO input clock 3339 * This parameter must be a number between 1 and 64 3340 * @note You have to set the PLLM2 parameter correctly to ensure that the VCO input 3341 * frequency ranges from 8 to 16 MHz 3342 * @param __PLLN2__: specifies the multiplication factor for PLL VCO output clock 3343 * This parameter must be a number between 25 and 100 3344 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3345 * output frequency is between 800 to 1600 MHz 3346 * @param __PLLP2__: specifies the division factor for the PLL2 P output 3347 * This parameter must be a number in the range 1 to 128 3348 * @param __PLLQ2__: specifies the division factor for for the PLL2 Q output 3349 * This parameter must be in the range 1 to 128 3350 * @param __PLLR2__: specifies the division factor for for the PLL2 R output 3351 * This parameter must be in the range 1 to 128 3352 * @retval None 3353 */ 3354 #define __HAL_RCC_PLL2_CONFIG(__PLLM2__, __PLLN2__, __PLLP2__, __PLLQ2__,__PLLR2__ ) \ 3355 do{ MODIFY_REG( RCC->PLL2CFGR1, (RCC_PLL2CFGR1_DIVN | RCC_PLL2CFGR1_DIVM2) , \ 3356 ( (__PLLN2__ - 1U) | ( (__PLLM2__ - 1U) << 16U) ) ); \ 3357 MODIFY_REG( RCC->PLL2CFGR2, (RCC_PLL2CFGR2_DIVP | RCC_PLL2CFGR2_DIVQ | RCC_PLL2CFGR2_DIVR), \ 3358 ( (__PLLP2__ - 1U) | ( (__PLLQ2__ - 1U) <<8U ) | ( (__PLLR2__ - 1U) <<16U) )); \ 3359 } while(0) 3360 3361 /** 3362 * @brief Macro to configure the PLL2 clock Fractional Part Of The Multiplication Factor 3363 * 3364 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 3365 * 3366 * @param __RCC_PLL2FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL2 VCO 3367 * It should be a value between 0 and 8191 ((2^13)-1) 3368 * @note Warning: the software has to set correctly these bits to insure that the VCO 3369 * output frequency is between its valid frequency range, which is: 800 to 1600 MHz 3370 * @retval None 3371 */ 3372 #define __HAL_RCC_PLL2FRACV_CONFIG(__RCC_PLL2FRACV__) \ 3373 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACV, \ 3374 (uint32_t)(__RCC_PLL2FRACV__) << RCC_PLL2FRACR_FRACV_Pos) 3375 3376 3377 /** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL2 3378 */ 3379 #define __HAL_RCC_PLL2_SSMODE_ENABLE() SET_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL) 3380 3381 #define __HAL_RCC_PLL2_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL) 3382 3383 3384 /** @brief Macro to config the PLL2 Clock Spreading Generator 3385 * @param __RCC_PLL2_MOD_PER__: Modulation Period Adjustment for PLL2 3386 * This parameter must have a value between 1 and 8191 3387 * 3388 * @param __RCC_PLL2_TPDFN_DIS__: Dithering TPDF noise control 3389 * This parameter can be one of the following values: 3390 * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3391 * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled 3392 3393 * @param __RCC_PLL2_RPDFN_DIS__: Dithering TPDF noise control 3394 * This parameter can be one of the following values: 3395 * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3396 * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled 3397 * 3398 * 3399 * @param __RCC_PLL2_SSCG_MODE__: Spread spectrum clock generator mode 3400 * This parameter can be one of the following values: 3401 * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset) 3402 * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected 3403 * 3404 * @param __RCC_PLL2_INC_STEP__: Modulation Depth Adjustment for PLL2 3405 * This parameter must have a value between 1 and 32767 3406 * 3407 * @note MOD_PER x INC_STEP shall not exceed (2^15)-1 3408 * @retval None 3409 */ 3410 #define __HAL_RCC_PLL2CSGCONFIG(__RCC_PLL2_MOD_PER__, __RCC_PLL2_TPDFN_DIS__, __RCC_PLL2_RPDFN_DIS__, \ 3411 __RCC_PLL2_SSCG_MODE__, __RCC_PLL2_INC_STEP__ ) \ 3412 do{ MODIFY_REG( RCC->PLL2CSGR, (RCC_PLL2CSGR_MOD_PER | RCC_PLL2CSGR_TPDFN_DIS | RCC_PLL2CSGR_RPDFN_DIS | \ 3413 RCC_PLL2CSGR_SSCG_MODE | RCC_PLL2CSGR_INC_STEP) , \ 3414 (__RCC_PLL2_MOD_PER__ | __RCC_PLL2_TPDFN_DIS__ | __RCC_PLL2_RPDFN_DIS__ | \ 3415 __RCC_PLL2_SSCG_MODE__ | (__RCC_PLL2_INC_STEP__ << RCC_PLL2CSGR_INC_STEP_Pos)) ) ; \ 3416 } while(0) 3417 3418 /** @brief Macros to enable or disable the PLL3. 3419 * @note After enabling the main PLL, the application software should wait on 3420 * PLLRDY flag to be set indicating that PLL clock is stable and can 3421 * be used as system clock source. 3422 * @note The PLL3 can not be disabled if it is used as MPU clock source 3423 * @note The PLL3 is disabled by hardware when entering STOP and STANDBY modes. 3424 */ 3425 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON ) 3426 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON) 3427 3428 /** 3429 * @brief Enables or disables each clock output 3430 * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL, 3431 * with the exception of ck_pll_p cannot be stopped if used as MPU Clock 3432 * @param __RCC_PLL3ClockOut__: specifies the PLL clock to be outputed 3433 * This parameter can be one of the following values: 3434 * @arg RCC_PLL3_DIVP 3435 * @arg RCC_PLL3_DIVQ 3436 * @arg RCC_PLL3_DIVR 3437 * @retval None 3438 */ 3439 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLL3CR, __RCC_PLL3ClockOut__ ) 3440 3441 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLL3CR, __RCC_PLL3ClockOut__ ) 3442 3443 3444 /** 3445 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 3446 * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL3 3447 * @retval None 3448 */ 3449 3450 #define __HAL_RCC_PLL3FRACV_ENABLE() SET_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE) 3451 3452 #define __HAL_RCC_PLL3FRACV_DISABLE() CLEAR_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE) 3453 3454 3455 /** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL3 3456 */ 3457 #define __HAL_RCC_PLL3_SSMODE_ENABLE() SET_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL) 3458 3459 #define __HAL_RCC_PLL3_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL) 3460 3461 3462 /** @brief Macro to config the PLL3 Clock Spreading Generator 3463 * @param __RCC_PLL3_MOD_PER__: Modulation Period Adjustment for PLL3 3464 * This parameter must have a value between 1 and 8191 3465 * 3466 * @param __RCC_PLL3_TPDFN_DIS__: Dithering TPDF noise control 3467 * This parameter can be one of the following values: 3468 * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3469 * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled 3470 3471 * @param __RCC_PLL3_RPDFN_DIS__: Dithering TPDF noise control 3472 * This parameter can be one of the following values: 3473 * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3474 * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled 3475 * 3476 * 3477 * @param __RCC_PLL3_SSCG_MODE__: Spread spectrum clock generator mode 3478 * This parameter can be one of the following values: 3479 * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset) 3480 * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected 3481 * 3482 * @param __RCC_PLL3_INC_STEP__: Modulation Depth Adjustment for PLL3 3483 * This parameter must have a value between 1 and 32767 3484 * 3485 * @note MOD_PER x INC_STEP shall not exceed (2^15)-1 3486 * @retval None 3487 */ 3488 #define __HAL_RCC_PLL3CSGCONFIG(__RCC_PLL3_MOD_PER__, __RCC_PLL3_TPDFN_DIS__, __RCC_PLL3_RPDFN_DIS__, \ 3489 __RCC_PLL3_SSCG_MODE__, __RCC_PLL3_INC_STEP__ ) \ 3490 do{ MODIFY_REG( RCC->PLL3CSGR, (RCC_PLL3CSGR_MOD_PER | RCC_PLL3CSGR_TPDFN_DIS | RCC_PLL3CSGR_RPDFN_DIS | \ 3491 RCC_PLL3CSGR_SSCG_MODE | RCC_PLL3CSGR_INC_STEP) , \ 3492 (__RCC_PLL3_MOD_PER__ | __RCC_PLL3_TPDFN_DIS__ | __RCC_PLL3_RPDFN_DIS__ | \ 3493 __RCC_PLL3_SSCG_MODE__ | (__RCC_PLL3_INC_STEP__ << RCC_PLL3CSGR_INC_STEP_Pos)) ) ; \ 3494 } while(0) 3495 3496 3497 /** 3498 * @brief Macro to configure PLL3 clock source 3499 * @note This function must be used only when the PLL is disabled. 3500 * 3501 * @param __RCC_PLL3SOURCE__: specifies the PLL3 entry clock source. 3502 * This parameter can be one of the following values: 3503 * @arg RCC_PLL3SOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry 3504 * @arg RCC_PLL3SOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry 3505 * @arg RCC_PLL3SOURCE_CSI: HSE oscillator clock selected as PLL3 clock entry 3506 * @arg RCC_PLL3SOURCE_OFF: No clock send to DIVMx divider and PLL 3507 * @retval None 3508 */ 3509 #define __HAL_RCC_PLL3_SOURCE(__RCC_PLL3SOURCE__ ) \ 3510 do{ MODIFY_REG( RCC->RCK3SELR, RCC_RCK3SELR_PLL3SRC, __RCC_PLL3SOURCE__ ); \ 3511 } while(0) 3512 3513 /** @brief Macro to get the clock source used as PLL3 clock. 3514 * @retval The clock source used as PLL3 clock. The returned value can be one 3515 * of the following: 3516 * - RCC_PLL3SOURCE_HSI: HSI used as PLL3 clock. 3517 * - RCC_PLL3SOURCE_HSE: HSE used as PLL3 clock. 3518 * - RCC_PLL3SOURCE_CSI: CSI used as PLL3 clock. 3519 * - RCC_PLL3SOURCE_OFF: PLL3 clock is gated. 3520 */ 3521 #define __HAL_RCC_GET_PLL3_SOURCE() ((uint32_t)(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC)) 3522 3523 /** 3524 * @brief Macro to configure PLL3 multiplication and division factors. 3525 * @note This function must be used only when the PLL3 is disabled. 3526 * 3527 * @param __PLLM3__: specifies the division factor for PLL VCO input clock 3528 * This parameter must be a number between 1 and 64 3529 * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input 3530 * frequency ranges from 4 to 16 MHz 3531 * @param __PLLN3__: specifies the multiplication factor for PLL VCO output clock 3532 * This parameter must be a number between 25 and 200 3533 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3534 * output frequency is between 400 to 800 MHz 3535 * @param __PLLP3__: specifies the division factor for the PLL3 P output 3536 * This parameter must be a number in the range 1 to 128 3537 * @param __PLLQ3__: specifies the division factor for for the PLL3 Q output 3538 * This parameter must be in the range 1 to 128 3539 * @param __PLLR3__: specifies the division factor for for the PLL3 R output 3540 * This parameter must be in the range 1 to 128 3541 * @retval None 3542 */ 3543 #define __HAL_RCC_PLL3_CONFIG(__PLLM3__, __PLLN3__, __PLLP3__, __PLLQ3__,__PLLR3__ ) \ 3544 do{ MODIFY_REG( RCC->PLL3CFGR1, (RCC_PLL3CFGR1_DIVN | RCC_PLL3CFGR1_DIVM3) , \ 3545 ( (__PLLN3__ - 1U) | ( (__PLLM3__ - 1U) << 16U) ) ); \ 3546 MODIFY_REG( RCC->PLL3CFGR2, (RCC_PLL3CFGR2_DIVP | RCC_PLL3CFGR2_DIVQ | RCC_PLL3CFGR2_DIVR), \ 3547 ( (__PLLP3__ - 1U) | ( (__PLLQ3__ - 1U) <<8U ) | ( (__PLLR3__ - 1U) <<16U) )); \ 3548 } while(0) 3549 3550 /** 3551 * @brief Macro to configure the PLL3 clock Fractional Part Of The Multiplication Factor 3552 * 3553 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 3554 * 3555 * @param __RCC_PLL3FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL3 VCO 3556 * It should be a value between 0 and 8191 ((2^13)-1) 3557 * @note Warning: the software has to set correctly these bits to insure that the VCO 3558 * output frequency is between its valid frequency range, which is: 400 to 800 MHz 3559 * @retval None 3560 */ 3561 #define __HAL_RCC_PLL3FRACV_CONFIG(__RCC_PLL3FRACV__) \ 3562 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACV, \ 3563 (uint32_t)(__RCC_PLL3FRACV__) << RCC_PLL3FRACR_FRACV_Pos) 3564 3565 3566 /** @brief Macro to select the PLL3 input frequency range. 3567 * @param __RCC_PLL3IFRange__: specifies the PLL3 input frequency range 3568 * This parameter can be one of the following values: 3569 * @arg RCC_PLL3IFRANGE_0: Range frequency is between 4 and 8 MHz (default after reset) 3570 * @arg RCC_PLL3IFRANGE_1: Range frequency is between 8 and 16 MHz 3571 * @retval None 3572 */ 3573 #define __HAL_RCC_PLL3_IFRANGE(__RCC_PLL3IFRange__) \ 3574 MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_IFRGE, (__RCC_PLL3IFRange__)) 3575 3576 3577 /** @brief Macros to enable or disable the PLL4. 3578 * @note After enabling the main PLL, the application software should wait on 3579 * PLLRDY flag to be set indicating that PLL clock is stable and can 3580 * be used as system clock source. 3581 * @note The PLL4 can not be disabled if it is used as MPU clock source 3582 * @note The PLL4 is disabled by hardware when entering STOP and STANDBY modes. 3583 */ 3584 #define __HAL_RCC_PLL4_ENABLE() SET_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON ) 3585 #define __HAL_RCC_PLL4_DISABLE() CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON) 3586 3587 /** 3588 * @brief Enables or disables each clock output 3589 * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL, 3590 * with the exception of ck_pll_p cannot be stopped if used as MPU Clock 3591 * @param __RCC_PLL4ClockOut__: specifies the PLL clock to be outputed 3592 * This parameter can be one of the following values: 3593 * @arg RCC_PLL4_DIVP 3594 * @arg RCC_PLL4_DIVQ 3595 * @arg RCC_PLL4_DIVR 3596 * @retval None 3597 */ 3598 #define __HAL_RCC_PLL4CLKOUT_ENABLE(__RCC_PLL4ClockOut__) SET_BIT(RCC->PLL4CR, __RCC_PLL4ClockOut__ ) 3599 3600 #define __HAL_RCC_PLL4CLKOUT_DISABLE(__RCC_PLL4ClockOut__) CLEAR_BIT(RCC->PLL4CR, __RCC_PLL4ClockOut__ ) 3601 3602 3603 /** 3604 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL4 VCO 3605 * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL4 3606 * @retval None 3607 */ 3608 3609 #define __HAL_RCC_PLL4FRACV_ENABLE() SET_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE) 3610 3611 #define __HAL_RCC_PLL4FRACV_DISABLE() CLEAR_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE) 3612 3613 3614 /** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL4 3615 */ 3616 #define __HAL_RCC_PLL4_SSMODE_ENABLE() SET_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL) 3617 3618 #define __HAL_RCC_PLL4_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL) 3619 3620 3621 /** @brief Macro to config the PLL4 Clock Spreading Generator 3622 * @param __RCC_PLL4_MOD_PER__: Modulation Period Adjustment for PLL4 3623 * This parameter must have a value between 1 and 8191 3624 * 3625 * @param __RCC_PLL4_TPDFN_DIS__: Dithering TPDF noise control 3626 * This parameter can be one of the following values: 3627 * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3628 * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled 3629 3630 * @param __RCC_PLL4_RPDFN_DIS__: Dithering TPDF noise control 3631 * This parameter can be one of the following values: 3632 * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset) 3633 * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled 3634 * 3635 * 3636 * @param __RCC_PLL4_SSCG_MODE__: Spread spectrum clock generator mode 3637 * This parameter can be one of the following values: 3638 * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset) 3639 * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected 3640 * 3641 * @param __RCC_PLL4_INC_STEP__: Modulation Depth Adjustment for PLL4 3642 * This parameter must have a value between 1 and 32767 3643 * 3644 * @note MOD_PER x INC_STEP shall not exceed (2^15)-1 3645 * @retval None 3646 */ 3647 #define __HAL_RCC_PLL4CSGCONFIG(__RCC_PLL4_MOD_PER__, __RCC_PLL4_TPDFN_DIS__, __RCC_PLL4_RPDFN_DIS__, \ 3648 __RCC_PLL4_SSCG_MODE__, __RCC_PLL4_INC_STEP__ ) \ 3649 do{ MODIFY_REG( RCC->PLL4CSGR, (RCC_PLL4CSGR_MOD_PER | RCC_PLL4CSGR_TPDFN_DIS | RCC_PLL4CSGR_RPDFN_DIS | \ 3650 RCC_PLL4CSGR_SSCG_MODE | RCC_PLL4CSGR_INC_STEP) , \ 3651 (__RCC_PLL4_MOD_PER__ | __RCC_PLL4_TPDFN_DIS__ | __RCC_PLL4_RPDFN_DIS__ | \ 3652 __RCC_PLL4_SSCG_MODE__ | (__RCC_PLL4_INC_STEP__ << RCC_PLL4CSGR_INC_STEP_Pos)) ) ; \ 3653 } while(0) 3654 3655 3656 /** 3657 * @brief Macro to configure PLL4 clock source 3658 * @note This function must be used only when the PLL is disabled. 3659 * 3660 * @param __RCC_PLL4SOURCE__: specifies the PLL4 entry clock source. 3661 * This parameter can be one of the following values: 3662 * @arg RCC_PLL4SOURCE_HSI: HSI oscillator clock selected as PLL4 clock entry 3663 * @arg RCC_PLL4SOURCE_HSE: HSE oscillator clock selected as PLL4 clock entry 3664 * @arg RCC_PLL4SOURCE_CSI: HSE oscillator clock selected as PLL4 clock entry 3665 * @arg RCC_PLL4SOURCE_I2S_CKIN: Signal I2S_CKIN used as reference clock 3666 * @retval None 3667 */ 3668 #define __HAL_RCC_PLL4_SOURCE(__RCC_PLL4SOURCE__ ) \ 3669 do{ MODIFY_REG( RCC->RCK4SELR, RCC_RCK4SELR_PLL4SRC, __RCC_PLL4SOURCE__ ); \ 3670 } while(0) 3671 3672 /** @brief Macro to get the clock source used as PLL4 clock. 3673 * @retval The clock source used as PLL4 clock. The returned value can be one 3674 * of the following: 3675 * - RCC_PLL4SOURCE_HSI: HSI used as PLL4 clock. 3676 * - RCC_PLL4SOURCE_HSE: HSE used as PLL4 clock. 3677 * - RCC_PLL4SOURCE_CSI: CSI used as PLL4 clock. 3678 * - RCC_PLL4SOURCE_I2S_CKIN: I2S_CKIN used as PLL4 clock. 3679 */ 3680 #define __HAL_RCC_GET_PLL4_SOURCE() ((uint32_t)(RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRC)) 3681 3682 3683 /** 3684 * @brief Macro to configure PLL4 multiplication and division factors. 3685 * @note This function must be used only when the PLL4 is disabled. 3686 * 3687 * @param __PLLM4__: specifies the division factor for PLL VCO input clock 3688 * This parameter must be a number between 1 and 64 3689 * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input 3690 * frequency ranges from 4 to 16 MHz 3691 * @param __PLLN4__: specifies the multiplication factor for PLL VCO output clock 3692 * This parameter must be a number between 25 and 200 3693 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3694 * output frequency is between 400 to 800 MHz 3695 * @param __PLLP4__: specifies the division factor for the PLL4 P output 3696 * This parameter must be a number in the range 1 to 128 3697 * @param __PLLQ4__: specifies the division factor for for the PLL4 Q output 3698 * This parameter must be in the range 1 to 128 3699 * @param __PLLR4__: specifies the division factor for for the PLL4 R output 3700 * This parameter must be in the range 1 to 128 3701 * @retval None 3702 */ 3703 #define __HAL_RCC_PLL4_CONFIG(__PLLM4__, __PLLN4__, __PLLP4__, __PLLQ4__,__PLLR4__ ) \ 3704 do{ MODIFY_REG( RCC->PLL4CFGR1, (RCC_PLL4CFGR1_DIVN | RCC_PLL4CFGR1_DIVM4) , \ 3705 ( (__PLLN4__ - 1U) | ( (__PLLM4__ - 1U) << 16U) ) ); \ 3706 MODIFY_REG( RCC->PLL4CFGR2, (RCC_PLL4CFGR2_DIVP | RCC_PLL4CFGR2_DIVQ | RCC_PLL4CFGR2_DIVR), \ 3707 ( (__PLLP4__ - 1U) | ( (__PLLQ4__ - 1U) <<8U ) | ( (__PLLR4__ - 1U) <<16U) )); \ 3708 } while(0) 3709 3710 3711 /** 3712 * @brief Macro to configure the PLL4 clock Fractional Part Of The Multiplication Factor 3713 * 3714 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL4 VCO 3715 * 3716 * @param __RCC_PLL4FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL4 VCO 3717 * It should be a value between 0 and 8191 ((2^13)-1) 3718 * @note Warning: the software has to set correctly these bits to insure that the VCO 3719 * output frequency is between its valid frequency range, which is: 400 to 800 MHz 3720 * @retval None 3721 */ 3722 #define __HAL_RCC_PLL4FRACV_CONFIG(__RCC_PLL4FRACV__) \ 3723 MODIFY_REG(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACV, \ 3724 (uint32_t)(__RCC_PLL4FRACV__) << RCC_PLL4FRACR_FRACV_Pos) 3725 3726 3727 /** @brief Macro to select the PLL4 input frequency range. 3728 * @param __RCC_PLL4IFRange__: specifies the PLL4 input frequency range 3729 * This parameter can be one of the following values: 3730 * @arg RCC_PLL4IFRANGE_0: Range frequency is between 4 and 8 MHz (default after reset) 3731 * @arg RCC_PLL4IFRANGE_1: Range frequency is between 8 and 16 MHz 3732 * @retval None 3733 */ 3734 #define __HAL_RCC_PLL4_IFRANGE(__RCC_PLL4IFRange__) \ 3735 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE, (__RCC_PLL4IFRange__)) 3736 3737 3738 /** @brief Macros to enable or disable the MCO1 output. 3739 * 3740 */ 3741 #define __HAL_RCC_MCO1_ENABLE() SET_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON) 3742 #define __HAL_RCC_MCO1_DISABLE() CLEAR_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON) 3743 3744 /** 3745 * @brief Macro to configure MCO1 prescaler 3746 * @note Set and cleared by software to configure the prescaler of the MCO1. 3747 * @note Modification of this prescaler may generate glitches on MCO1. 3748 * @note It is highly recommended to change this prescaler only after reset, 3749 * before enabling the external oscillators and the PLLs. 3750 * 3751 * @param __RCC_MCO1SOURCE__: specifies the MCO1 entry clock source. 3752 * This parameter can be one of the following values: 3753 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 clock entry (default after reset) 3754 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 clock entry 3755 * @arg RCC_MCO1SOURCE_CSI: CSI clock selected as MCO1 clock entry 3756 * @arg RCC_MCO1SOURCE_LSI: LSI clock selected as MCO1 clock entry 3757 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 clock entry 3758 * 3759 * @param __RCC_MCO1PRESCALER__: specifies the MCO1 prescaler value. 3760 * This parameter can be one of the following values: 3761 * @arg RCC_MCODIV_1: bypass (default after reset) 3762 * @arg RCC_MCODIV_2: division by 2 3763 * @arg RCC_MCODIV_3: division by 3 3764 * @arg RCC_MCODIV_4: division by 4 3765 * @arg RCC_MCODIV_5: division by 5 3766 * @arg RCC_MCODIV_6: division by 6 3767 * @arg RCC_MCODIV_7: division by 7 3768 * @arg RCC_MCODIV_8: division by 8 3769 * @arg RCC_MCODIV_9: division by 9 3770 * @arg RCC_MCODIV_10: division by 10 3771 * @arg RCC_MCODIV_11: division by 11 3772 * @arg RCC_MCODIV_12: division by 12 3773 * @arg RCC_MCODIV_13: division by 13 3774 * @arg RCC_MCODIV_14: division by 14 3775 * @arg RCC_MCODIV_15: division by 15 3776 * @arg RCC_MCODIV_16: division by 16 3777 * @retval None 3778 */ 3779 #define __HAL_RCC_MCO1_CONFIGURE(__RCC_MCO1SOURCE__ , __RCC_MCO1PRESCALER__ ) \ 3780 do{ MODIFY_REG( RCC->MCO1CFGR, (RCC_MCO1CFGR_MCO1SEL | RCC_MCO1CFGR_MCO1DIV) , \ 3781 (__RCC_MCO1SOURCE__ | __RCC_MCO1PRESCALER__) );\ 3782 } while(0) 3783 3784 3785 /** @brief Macro to get the clock source used as MCO1 clock. 3786 * @retval The clock source used as MCO1 clock. The returned value can be one 3787 * of the following: 3788 * - RCC_MCO1SOURCE_HSI: HSI used as MCO1 clock (default after reset). 3789 * - RCC_MCO1SOURCE_HSE: HSE used as MCO1 clock. 3790 * - RCC_MCO1SOURCE_CSI: CSI used as MCO1 clock. 3791 * - RCC_MCO1SOURCE_LSI: LSI used as MCO1 clock. 3792 * - RCC_MCO1SOURCE_LSE: LSE used as MCO1 clock. 3793 */ 3794 #define __HAL_RCC_GET_MCO1_SOURCE() ((uint32_t)(RCC->MCO1CFGR & RCC_MCO1CFGR_MCO1SEL)) 3795 3796 /** @brief Macro to get the MCO1 prescaler value 3797 * @retval The MCO1 prescaler value. The returned value can be one 3798 * of the following: 3799 * - RCC_MCODIV_1: bypass (default after reset) 3800 * - RCC_MCODIV_2: division by 2 3801 * - RCC_MCODIV_3: division by 3 3802 * - RCC_MCODIV_4: division by 4 3803 * - RCC_MCODIV_5: division by 5 3804 * - RCC_MCODIV_6: division by 6 3805 * - RCC_MCODIV_7: division by 7 3806 * - RCC_MCODIV_8: division by 8 3807 * - RCC_MCODIV_9: division by 9 3808 * - RCC_MCODIV_10: division by 10 3809 * - RCC_MCODIV_11: division by 11 3810 * - RCC_MCODIV_12: division by 12 3811 * - RCC_MCODIV_13: division by 13 3812 * - RCC_MCODIV_14: division by 14 3813 * - RCC_MCODIV_15: division by 15 3814 * - RCC_MCODIV_16: division by 16 3815 */ 3816 #define __HAL_RCC_GET_MCO1_DIV() ((uint32_t)(RCC->MCO1CFGR & RCC_MCO1CFGR_MCO1DIV)) 3817 3818 3819 /** @brief Macros to enable or disable the MCO2 output. 3820 * 3821 */ 3822 #define __HAL_RCC_MCO2_ENABLE() SET_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON) 3823 #define __HAL_RCC_MCO2_DISABLE() CLEAR_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON) 3824 3825 /** 3826 * @brief Macro to configure MCO2 prescaler 3827 * @note Set and cleared by software to configure the prescaler of the MCO2. 3828 * @note Modification of this prescaler may generate glitches on MCO2. 3829 * @note It is highly recommended to change this prescaler only after reset, 3830 * before enabling the external oscillators and the PLLs. 3831 * 3832 * @param __RCC_MCO2SOURCE__: specifies the MCO2 entry clock source. 3833 * This parameter can be one of the following values: 3834 * @arg RCC_MCO2SOURCE_MPU: MPU clock selected as MCO2 clock entry (default after reset) 3835 * @arg RCC_MCO2SOURCE_AXI: AXI clock selected as MCO2 clock entry 3836 * @arg RCC_MCO2SOURCE_MCU: MCU clock selected as MCO2 clock entry 3837 * @arg RCC_MCO2SOURCE_PLL4: PLL4 clock selected as MCO2 clock entry 3838 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 clock entry 3839 * @arg RCC_MCO2SOURCE_HSI: HSI clock selected as MCO2 clock entry 3840 * 3841 * @param __RCC_MCO2PRESCALER__: specifies the MCO2 prescaler value. 3842 * This parameter can be one of the following values: 3843 * @arg RCC_MCODIV_1: bypass (default after reset) 3844 * @arg RCC_MCODIV_2: division by 2 3845 * @arg RCC_MCODIV_3: division by 3 3846 * @arg RCC_MCODIV_4: division by 4 3847 * @arg RCC_MCODIV_5: division by 5 3848 * @arg RCC_MCODIV_6: division by 6 3849 * @arg RCC_MCODIV_7: division by 7 3850 * @arg RCC_MCODIV_8: division by 8 3851 * @arg RCC_MCODIV_9: division by 9 3852 * @arg RCC_MCODIV_10: division by 10 3853 * @arg RCC_MCODIV_11: division by 11 3854 * @arg RCC_MCODIV_12: division by 12 3855 * @arg RCC_MCODIV_13: division by 13 3856 * @arg RCC_MCODIV_14: division by 14 3857 * @arg RCC_MCODIV_15: division by 15 3858 * @arg RCC_MCODIV_16: division by 16 3859 * @retval None 3860 */ 3861 #define __HAL_RCC_MCO2_CONFIGURE(__RCC_MCO2SOURCE__ , __RCC_MCO2PRESCALER__ ) \ 3862 do{ MODIFY_REG( RCC->MCO2CFGR, (RCC_MCO2CFGR_MCO2SEL | RCC_MCO2CFGR_MCO2DIV) , \ 3863 (__RCC_MCO2SOURCE__ | __RCC_MCO2PRESCALER__) );\ 3864 } while(0) 3865 3866 3867 /** @brief Macro to get the clock source used as MCO2 clock. 3868 * @retval The clock source used as MCO2 clock. The returned value can be one 3869 * of the following: 3870 * - RCC_MCO2SOURCE_MPU: MPU used as MCO2 clock (default after reset). 3871 * - RCC_MCO2SOURCE_AXI: AXI used as MCO2 clock. 3872 * - RCC_MCO2SOURCE_MCU: MCU used as MCO2 clock. 3873 * - RCC_MCO2SOURCE_PLL4: PLL4 used as MCO2 clock. 3874 * - RCC_MCO2SOURCE_HSE: HSE used as MCO2 clock. 3875 * - RCC_MCO2SOURCE_HSI: HSI used as MCO2 clock. 3876 */ 3877 #define __HAL_RCC_GET_MCO2_SOURCE() ((uint32_t)(RCC->MCO2CFGR & RCC_MCO2CFGR_MCO2SEL)) 3878 3879 /** @brief Macro to get the MCO2 prescaler value 3880 * @retval The MCO2 prescaler value. The returned value can be one 3881 * of the following: 3882 * - RCC_MCODIV_1: bypass (default after reset) 3883 * - RCC_MCODIV_2: division by 2 3884 * - RCC_MCODIV_3: division by 3 3885 * - RCC_MCODIV_4: division by 4 3886 * - RCC_MCODIV_5: division by 5 3887 * - RCC_MCODIV_6: division by 6 3888 * - RCC_MCODIV_7: division by 7 3889 * - RCC_MCODIV_8: division by 8 3890 * - RCC_MCODIV_9: division by 9 3891 * - RCC_MCODIV_10: division by 10 3892 * - RCC_MCODIV_11: division by 11 3893 * - RCC_MCODIV_12: division by 12 3894 * - RCC_MCODIV_13: division by 13 3895 * - RCC_MCODIV_14: division by 14 3896 * - RCC_MCODIV_15: division by 15 3897 * - RCC_MCODIV_16: division by 16 3898 */ 3899 #define __HAL_RCC_GET_MCO2_DIV() ((uint32_t)(RCC->MCO2CFGR & RCC_MCO2CFGR_MCO2DIV)) 3900 3901 3902 /** 3903 * @brief Macro to configure MPU sub-system clock source 3904 * @note Set and reset by software to select the MPU sub-system clock source (ck_mpuss) 3905 * @note If TZEN = 1, it is only possible to modify this parameter in secure mode 3906 * @note Write access is not allowed during the clock restore sequence 3907 * 3908 * @param __RCC_MPUSOURCE__: specifies the MPU entry clock source. 3909 * This parameter can be one of the following values: 3910 * @arg RCC_MPUSOURCE_HSI: HSI used as MPU clock (default after reset). 3911 * @arg RCC_MPUSOURCE_HSE: HSE used as MPU clock. 3912 * @arg RCC_MPUSOURCE_PLL1: PLL1 used as MPU clock. 3913 * @arg RCC_MPUSOURCE_MPUDIV: MPUDIV used as MPU clock. 3914 */ 3915 #define __HAL_RCC_MPU_SOURCE(__RCC_MPUSOURCE__) \ 3916 do{ MODIFY_REG( RCC->MPCKSELR, RCC_MPCKSELR_MPUSRC , __RCC_MPUSOURCE__ );\ 3917 } while(0) 3918 3919 /** @brief Macro to get the clock source used as MPU clock. 3920 * @retval The clock source used as MPU clock. The returned value can be one 3921 * of the following: 3922 * - RCC_MPUSOURCE_HSI: HSI used as MPU clock (default after reset). 3923 * - RCC_MPUSOURCE_HSE: HSE used as MPU clock. 3924 * - RCC_MPUSOURCE_PLL1: PLL1 used as MPU clock. 3925 * - RCC_MPUSOURCE_MPUDIV: MPU used as MPU clock. 3926 */ 3927 #define __HAL_RCC_GET_MPU_SOURCE() ((uint32_t)(RCC->MPCKSELR & RCC_MPCKSELR_MPUSRC)) 3928 3929 3930 /** 3931 * @brief Macro to configure AXISS clock source 3932 * @note Set and reset by software to select the AXI sub-system clock source (ck_axiss) 3933 * @note If TZEN = 1, it is only possible to modify this parameter in secure mode 3934 * @note Write access is not allowed during the clock restore sequence 3935 * 3936 * @param __RCC_AXISSOURCE__: specifies the AXISS entry clock source. 3937 * This parameter can be one of the following values: 3938 * @arg RCC_AXISSOURCE_HSI: HSI used as AXISS clock (default after reset). 3939 * @arg RCC_AXISSOURCE_HSE: HSE used as AXISS clock. 3940 * @arg RCC_AXISSOURCE_PLL2: PLL2 used as AXISS clock. 3941 * @arg RCC_AXISSOURCE_OFF: AXISS clock is gated. 3942 */ 3943 #define __HAL_RCC_AXISS_SOURCE(__RCC_AXISSOURCE__) \ 3944 do{ MODIFY_REG( RCC->ASSCKSELR, RCC_ASSCKSELR_AXISSRC , __RCC_AXISSOURCE__ );\ 3945 } while(0) 3946 3947 /** @brief Macro to get the clock source used as AXIS clock. 3948 * @retval The clock source used as AXIS clock. The returned value can be one 3949 * of the following: 3950 * - RCC_AXISSOURCE_HSI: HSI used as AXIS clock (default after reset). 3951 * - RCC_AXISSOURCE_HSE: HSE used as AXIS clock. 3952 * - RCC_AXISSOURCE_PLL2: PLL2 used as AXIS clock. 3953 * - RCC_AXISSOURCE_OFF: AXIS clock is gated. 3954 */ 3955 #define __HAL_RCC_GET_AXIS_SOURCE() ((uint32_t)(RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRC)) 3956 3957 3958 /** 3959 * @brief Macro to configure MCU sub-system clock source 3960 * @note Set and reset by software to select the mcu sub-system clock source (ck_mcuss) 3961 * @note If TZEN = 1, it is only possible to modify this parameter in secure mode 3962 * @note Write access is not allowed during the clock restore sequence 3963 * 3964 * @param __RCC_MCUSSOURCE__: specifies the MCU entry clock source. 3965 * This parameter can be one of the following values: 3966 * @arg RCC_MCUSSOURCE_HSI: HSI used as MCU clock (default after reset). 3967 * @arg RCC_MCUSSOURCE_HSE: HSE used as MCU clock. 3968 * @arg RCC_MCUSSOURCE_PLL3: PLL3 used as MCU clock. 3969 */ 3970 #define __HAL_RCC_MCU_SOURCE(__RCC_MCUSSOURCE__) \ 3971 do{ MODIFY_REG( RCC->MSSCKSELR, RCC_MSSCKSELR_MCUSSRC , __RCC_MCUSSOURCE__ );\ 3972 } while(0) 3973 3974 /** @brief Macro to get the clock source used as MCU clock. 3975 * @retval The clock source used as MCU clock. The returned value can be one 3976 * of the following: 3977 * - RCC_MCUSSOURCE_HSI: HSI used as MCU clock (default after reset). 3978 * - RCC_MCUSSOURCE_HSE: HSE used as MCU clock. 3979 * - RCC_MCUSSOURCE_CSI: CSI used as MCU clock. 3980 * - RCC_MCUSSOURCE_PLL3: PLL3 used as MCU clock. 3981 */ 3982 #define __HAL_RCC_GET_MCU_SOURCE() ((uint32_t)(RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)) 3983 3984 3985 3986 /** 3987 * @brief Macro to set the HSE division factor for RTC clock 3988 * @note Set and cleared by software to divide the HSE to generate a clock for RTC. 3989 * @note If TZEN = 1, this parameter can only be modified in secure mode 3990 * @note Caution: The software has to set these bits correctly to ensure that the clock supplied to the RTC is lower than 4 MHz. 3991 * @note These bits must be configured if needed before selecting the RTC clock source 3992 * 3993 * @param __HSEDIV__: Specifies the HSE division factor for RTC clock 3994 * This parameter must be a number between 1 and 64. Eg.: 3995 * 1: HSE (default after reset) 3996 * 2: HSE/2 3997 * 64: HSE/64 3998 * @retval None 3999 */ 4000 #define __HAL_RCC_RTC_HSEDIV(__HSEDIV__) \ 4001 do{ MODIFY_REG( RCC->RTCDIVR, RCC_RTCDIVR_RTCDIV , (__HSEDIV__ -1U )); \ 4002 } while(0) 4003 4004 /** @brief Macro to get the HSE division factor for RTC clock. 4005 * @retval The HSE division factor for RTC clock. The returned value can be a number between 1 and 64 Eg.: 4006 * 1: HSE (default after reset) 4007 * 2: HSE/2 4008 * 64: HSE/64 4009 */ 4010 #define __HAL_RCC_GET_RTC_HSEDIV() ((uint32_t)((RCC->RTCDIVR & RCC_RTCDIVR_RTCDIV) + 1U )) 4011 4012 /** 4013 * @brief Macro to configure MPU Core clock divider 4014 * @note Set and reset by software to control the MPU clock division factor. 4015 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4016 * @note It is possible to change this division ratio on-the-fly. It impacts only the frequency of MPU clock. 4017 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_mpuss cycles after MPUDIV update. 4018 * @note The application can check if the new division factor is taken into account by reading back the MPUDIVRDY flag 4019 * 4020 * @param __RCC_MPUDIV__: specifies the MPU division factor 4021 * This parameter can be one of the following values: 4022 * @arg RCC_MPU_DIV_OFF: The MPUDIV is disabled (default after reset) 4023 * @arg RCC_MPU_DIV2: ck_mpuss divided by 2 4024 * @arg RCC_MPU_DIV4: ck_mpuss divided by 4 4025 * @arg RCC_MPU_DIV8: ck_mpuss divided by 8 4026 * @arg RCC_MPU_DIV16: ck_mpuss divided by 16 4027 * 4028 * @note Warning: Do not set RCC_MPU_DIV_OFF if the MPUSRC = RCC_MPUSOURCE_MPUDIV, 4029 * otherwise the processor will no longer be clocked 4030 */ 4031 #define __HAL_RCC_MPU_DIV(__RCC_MPUDIV__) \ 4032 do{ MODIFY_REG( RCC->MPCKDIVR, RCC_MPCKDIVR_MPUDIV , __RCC_MPUDIV__ );\ 4033 } while(0) 4034 4035 /** @brief Macro to get the MPU clock division factor. 4036 * @retval The MPU clock division factor. The returned value can be one 4037 * of the following: 4038 * - RCC_MPU_DIV_OFF: The MPUDIV is disabled (default after reset) 4039 * - RCC_MPU_DIV2: ck_mpuss divided by 2 4040 * - RCC_MPU_DIV4: ck_mpuss divided by 4 4041 * - RCC_MPU_DIV8: ck_mpuss divided by 8 4042 * - RCC_MPU_DIV16: ck_mpuss divided by 16 4043 */ 4044 #define __HAL_RCC_GET_MPU_DIV() ((uint32_t)(RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIV )) 4045 4046 4047 /** 4048 * @brief Macro to configure AXI Core clock divider 4049 * @note Set and reset by software to control the AXI, AHB5 and AHB6 clock division factor. 4050 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4051 * @note It is possible to change this division ratio on-the-fly. It impacts the frequency 4052 * of AXI, APB4, APB5 AHB5 and AHB6 clocks. 4053 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_axiss cycles after AXIDIV update. 4054 * @note The application can check if the new division factor is taken into account by reading back the AXIDIVRDY flag 4055 * 4056 * @param __RCC_AXIDIV__: specifies the AXI division factor 4057 * This parameter can be one of the following values: 4058 * @arg RCC_AXI_DIV1: ck_axiss not divided (default after reset) 4059 * @arg RCC_AXI_DIV2: ck_axiss divided by 2 4060 * @arg RCC_AXI_DIV3: ck_axiss divided by 3 4061 * @arg RCC_AXI_DIV4: ck_axiss divided by 4 4062 */ 4063 #define __HAL_RCC_AXI_DIV(__RCC_AXIDIV__) \ 4064 do{ MODIFY_REG( RCC->AXIDIVR, RCC_AXIDIVR_AXIDIV , __RCC_AXIDIV__ );\ 4065 } while(0) 4066 4067 /** @brief Macro to get the AXI, AHB5 and AHB6 clock division factor. 4068 * @retval The AXI clock division factor. The returned value can be one 4069 * of the following: 4070 * - RCC_AXI_DIV1: ck_axiss not divided (default after reset) 4071 * - RCC_AXI_DIV2: ck_axiss divided by 2 4072 * - RCC_AXI_DIV3: ck_axiss divided by 3 4073 * - RCC_AXI_DIV4: ck_axiss divided by 4 4074 */ 4075 #define __HAL_RCC_GET_AXI_DIV() ((uint32_t)(RCC->AXIDIVR & RCC_AXIDIVR_AXIDIV )) 4076 4077 4078 /** 4079 * @brief Macro to configure APB4 clock divider 4080 * @note Set and reset by software to control the APB4 clock division factor. 4081 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4082 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB4 clock. 4083 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_aclk cycles after APB4DIV update. 4084 * @note The application can check if the new division factor is taken into account by reading back the APB4DIVRDY flag 4085 * 4086 * @param __RCC_APB4DIV__: specifies the APB4 division factor 4087 * This parameter can be one of the following values: 4088 * @arg RCC_APB4_DIV1: ck_aclk not divided (default after reset) 4089 * @arg RCC_APB4_DIV2: ck_aclk divided by 2 4090 * @arg RCC_APB4_DIV4: ck_aclk divided by 4 4091 * @arg RCC_APB4_DIV8: ck_aclk divided by 8 4092 * @arg RCC_APB4_DIV16: ck_aclk divided by 16 4093 */ 4094 #define __HAL_RCC_APB4_DIV(__RCC_APB4DIV__) \ 4095 do{ MODIFY_REG( RCC->APB4DIVR, RCC_APB4DIVR_APB4DIV , __RCC_APB4DIV__ );\ 4096 } while(0) 4097 4098 /** @brief Macro to get the APB4 clock division factor. 4099 * @retval The APB4 clock division factor. The returned value can be one 4100 * of the following: 4101 * - RCC_APB4_DIV1: ck_aclk not divided (default after reset) 4102 * - RCC_APB4_DIV2: ck_aclk divided by 2 4103 * - RCC_APB4_DIV4: ck_aclk divided by 4 4104 * - RCC_APB4_DIV8: ck_aclk divided by 8 4105 * - RCC_APB4_DIV16: ck_aclk divided by 16 4106 */ 4107 #define __HAL_RCC_GET_APB4_DIV() ((uint32_t)(RCC->APB4DIVR & RCC_APB4DIVR_APB4DIV )) 4108 4109 4110 /** 4111 * @brief Macro to configure APB5 clock divider 4112 * @note Set and reset by software to control the APB5 clock division factor. 4113 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4114 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB5 clock. 4115 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_aclk cycles after APB5DIV update. 4116 * @note The application can check if the new division factor is taken into account by reading back the APB5DIVRDY flag 4117 * 4118 * @param __RCC_APB5DIV__: specifies the APB5 division factor 4119 * This parameter can be one of the following values: 4120 * @arg RCC_APB5_DIV1: ck_aclk not divided (default after reset) 4121 * @arg RCC_APB5_DIV2: ck_aclk divided by 2 4122 * @arg RCC_APB5_DIV4: ck_aclk divided by 4 4123 * @arg RCC_APB5_DIV8: ck_aclk divided by 8 4124 * @arg RCC_APB5_DIV16: ck_aclk divided by 16 4125 */ 4126 #define __HAL_RCC_APB5_DIV(__RCC_APB5DIV__) \ 4127 do{ MODIFY_REG( RCC->APB5DIVR, RCC_APB5DIVR_APB5DIV , __RCC_APB5DIV__ );\ 4128 } while(0) 4129 4130 /** @brief Macro to get the APB5 clock division factor. 4131 * @retval The APB5 clock division factor. The returned value can be one 4132 * of the following: 4133 * - RCC_APB5_DIV1: ck_aclk not divided (default after reset) 4134 * - RCC_APB5_DIV2: ck_aclk divided by 2 4135 * - RCC_APB5_DIV4: ck_aclk divided by 4 4136 * - RCC_APB5_DIV8: ck_aclk divided by 8 4137 * - RCC_APB5_DIV16: ck_aclk divided by 16 4138 */ 4139 #define __HAL_RCC_GET_APB5_DIV() ((uint32_t)(RCC->APB5DIVR & RCC_APB5DIVR_APB5DIV )) 4140 4141 4142 /** 4143 * @brief Macro to configure MCU clock divider 4144 * @note Set and reset by software to control the MCU clock division factor. 4145 * @note If TZEN = 1, this parameter can only be modified in secure mode. 4146 * @note Changing this division ratio has an impact on the frequency of MCU clock, and all bus matrix clocks. 4147 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_mcuss cycles after MCUDIV update. 4148 * @note The application can check if the new division factor is taken into account by reading back the MCUDIVRDY flag 4149 * 4150 * @param __RCC_MCUDIV__: specifies the MCU division factor 4151 * This parameter can be one of the following values: 4152 * @arg RCC_MCU_DIV1: ck_mcuss not divided (default after reset) 4153 * @arg RCC_MCU_DIV2: ck_mcuss divided by 2 4154 * @arg RCC_MCU_DIV4: ck_mcuss divided by 4 4155 * @arg RCC_MCU_DIV8: ck_mcuss divided by 8 4156 * @arg RCC_MCU_DIV16: ck_mcuss divided by 16 4157 * @arg RCC_MCU_DIV32: ck_mcuss divided by 32 4158 * @arg RCC_MCU_DIV64: ck_mcuss divided by 64 4159 * @arg RCC_MCU_DIV128: ck_mcuss divided by 128 4160 * @arg RCC_MCU_DIV256: ck_mcuss divided by 256 4161 * @arg RCC_MCU_DIV512: ck_mcuss divided by 512 4162 */ 4163 #define __HAL_RCC_MCU_DIV(__RCC_MCUDIV__) \ 4164 do{ MODIFY_REG( RCC->MCUDIVR, RCC_MCUDIVR_MCUDIV , __RCC_MCUDIV__ );\ 4165 } while(0) 4166 4167 /** @brief Macro to get the MCU clock division factor. 4168 * @retval The MCU clock division factor. The returned value can be one 4169 * of the following: 4170 * - RCC_MCU_DIV1: ck_mcuss not divided (default after reset) 4171 * - RCC_MCU_DIV2: ck_mcuss divided by 2 4172 * - RCC_MCU_DIV4: ck_mcuss divided by 4 4173 * - RCC_MCU_DIV8: ck_mcuss divided by 8 4174 * - RCC_MCU_DIV16: ck_mcuss divided by 16 4175 * - RCC_MCU_DIV32: ck_mcuss divided by 32 4176 * - RCC_MCU_DIV64: ck_mcuss divided by 64 4177 * - RCC_MCU_DIV128: ck_mcuss divided by 128 4178 * - RCC_MCU_DIV256: ck_mcuss divided by 256 4179 * - RCC_MCU_DIV512: ck_mcuss divided by 512 4180 */ 4181 #define __HAL_RCC_GET_MCU_DIV() ((uint32_t)(RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV )) 4182 4183 /** 4184 * @brief Macro to configure APB1 clock divider 4185 * @note Set and reset by software to control the APB1 clock division factor. 4186 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB1 clock. 4187 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB1DIV update. 4188 * @note The application can check if the new division factor is taken into account by reading back the APB1DIVRDY flag 4189 * 4190 * @param __RCC_APB1DIV__: specifies the APB1 division factor 4191 * This parameter can be one of the following values: 4192 * @arg RCC_APB1_DIV1: ck_hclk not divided (default after reset) 4193 * @arg RCC_APB1_DIV2: ck_hclk divided by 2 4194 * @arg RCC_APB1_DIV4: ck_hclk divided by 4 4195 * @arg RCC_APB1_DIV8: ck_hclk divided by 8 4196 * @arg RCC_APB1_DIV16: ck_hclk divided by 16 4197 */ 4198 #define __HAL_RCC_APB1_DIV(__RCC_APB1DIV__) \ 4199 do{ MODIFY_REG( RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV , __RCC_APB1DIV__ );\ 4200 } while(0) 4201 4202 /** @brief Macro to get the APB1 clock division factor. 4203 * @retval The APB1 clock division factor. The returned value can be one 4204 * of the following: 4205 * - RCC_APB1_DIV1: ck_hclk not divided (default after reset) 4206 * - RCC_APB1_DIV2: ck_hclk divided by 2 4207 * - RCC_APB1_DIV4: ck_hclk divided by 4 4208 * - RCC_APB1_DIV8: ck_hclk divided by 8 4209 * - RCC_APB1_DIV16: ck_hclk divided by 16 4210 */ 4211 #define __HAL_RCC_GET_APB1_DIV() ((uint32_t)(RCC->APB1DIVR & RCC_APB1DIVR_APB1DIV )) 4212 4213 4214 /** 4215 * @brief Macro to configure APB2 clock divider 4216 * @note Set and reset by software to control the APB2 clock division factor. 4217 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB2 clock. 4218 4219 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB2DIV update. 4220 * @note The application can check if the new division factor is taken into account by reading back the APB2DIVRDY flag 4221 * 4222 * @param __RCC_APB2DIV__: specifies the APB2 division factor 4223 * This parameter can be one of the following values: 4224 * @arg RCC_APB2_DIV1: ck_hclk not divided (default after reset) 4225 * @arg RCC_APB2_DIV2: ck_hclk divided by 2 4226 * @arg RCC_APB2_DIV4: ck_hclk divided by 4 4227 * @arg RCC_APB2_DIV8: ck_hclk divided by 8 4228 * @arg RCC_APB2_DIV16: ck_hclk divided by 16 4229 */ 4230 #define __HAL_RCC_APB2_DIV(__RCC_APB2DIV__) \ 4231 do{ MODIFY_REG( RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV , __RCC_APB2DIV__ );\ 4232 } while(0) 4233 4234 /** @brief Macro to get the APB2 clock division factor. 4235 * @retval The APB2 clock division factor. The returned value can be one 4236 * of the following: 4237 * - RCC_APB2_DIV1: ck_hclk not divided (default after reset) 4238 * - RCC_APB2_DIV2: ck_hclk divided by 2 4239 * - RCC_APB2_DIV4: ck_hclk divided by 4 4240 * - RCC_APB2_DIV8: ck_hclk divided by 8 4241 * - RCC_APB2_DIV16: ck_hclk divided by 16 4242 */ 4243 #define __HAL_RCC_GET_APB2_DIV() ((uint32_t)(RCC->APB2DIVR & RCC_APB2DIVR_APB2DIV )) 4244 4245 4246 /** 4247 * @brief Macro to configure APB3 clock divider 4248 * @note Set and reset by software to control the APB3 clock division factor. 4249 * @note It is possible to change this division ratio on-the-fly. It impacts only the APB3 clock. 4250 4251 * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB3DIV update. 4252 * @note The application can check if the new division factor is taken into account by reading back the APB3DIVRDY flag 4253 * 4254 * @param __RCC_APB3DIV__: specifies the APB3 division factor 4255 * This parameter can be one of the following values: 4256 * @arg RCC_APB3_DIV1: ck_hclk not divided (default after reset) 4257 * @arg RCC_APB3_DIV2: ck_hclk divided by 2 4258 * @arg RCC_APB3_DIV4: ck_hclk divided by 4 4259 * @arg RCC_APB3_DIV8: ck_hclk divided by 8 4260 * @arg RCC_APB3_DIV16: ck_hclk divided by 16 4261 */ 4262 #define __HAL_RCC_APB3_DIV(__RCC_APB3DIV__) \ 4263 do{ MODIFY_REG( RCC->APB3DIVR, RCC_APB3DIVR_APB3DIV , __RCC_APB3DIV__ );\ 4264 } while(0) 4265 4266 /** @brief Macro to get the APB3 clock division factor. 4267 * @retval The APB3 clock division factor. The returned value can be one 4268 * of the following: 4269 * - RCC_APB3_DIV1: ck_hclk not divided (default after reset) 4270 * - RCC_APB3_DIV2: ck_hclk divided by 2 4271 * - RCC_APB3_DIV4: ck_hclk divided by 4 4272 * - RCC_APB3_DIV8: ck_hclk divided by 8 4273 * - RCC_APB3_DIV16: ck_hclk divided by 16 4274 */ 4275 #define __HAL_RCC_GET_APB3_DIV() ((uint32_t)(RCC->APB3DIVR & RCC_APB3DIVR_APB3DIV )) 4276 4277 4278 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR bits to enable 4279 * the selected interrupts). 4280 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 4281 * This parameter can be any combination of the following values: 4282 * @arg RCC_IT_LSIRDY: LSI ready interrupt 4283 * @arg RCC_IT_LSERDY: LSE ready interrupt 4284 * @arg RCC_IT_HSIRDY: HSI ready interrupt 4285 * @arg RCC_IT_HSERDY: HSE ready interrupt 4286 * @arg RCC_IT_CSIRDY: CSI ready interrupt 4287 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt 4288 * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt 4289 * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt 4290 * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt 4291 * @arg RCC_IT_LSECSS: LSE Clock security system interrupt 4292 * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt 4293 * @arg RCC_IT_ALL: All RCC interrupts 4294 */ 4295 #ifdef CORE_CM4 4296 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->MC_CIER, (__INTERRUPT__)) 4297 #endif /* CORE_CM4 */ 4298 #ifdef CORE_CA7 4299 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->MP_CIER, (__INTERRUPT__)) 4300 #endif /* CORE_CA7 */ 4301 4302 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 4303 * the selected interrupts). 4304 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 4305 * This parameter can be any combination of the following values: 4306 * @arg RCC_IT_LSIRDY: LSI ready interrupt 4307 * @arg RCC_IT_LSERDY: LSE ready interrupt 4308 * @arg RCC_IT_HSIRDY: HSI ready interrupt 4309 * @arg RCC_IT_HSERDY: HSE ready interrupt 4310 * @arg RCC_IT_CSIRDY: CSI ready interrupt 4311 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt 4312 * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt 4313 * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt 4314 * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt 4315 * @arg RCC_IT_LSECSS: LSE Clock security system interrupt 4316 * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt 4317 * @arg RCC_IT_ALL: All RCC interrupts 4318 */ 4319 #ifdef CORE_CM4 4320 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->MC_CIER, (__INTERRUPT__)) 4321 #endif /* CORE_CM4 */ 4322 #ifdef CORE_CA7 4323 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->MP_CIER, (__INTERRUPT__)) 4324 #endif /* CORE_CA7 */ 4325 4326 4327 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 4328 * bits to clear the selected interrupt pending bits. 4329 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 4330 * This parameter can be any combination of the following values: 4331 * @arg RCC_IT_LSIRDY: LSI ready interrupt 4332 * @arg RCC_IT_LSERDY: LSE ready interrupt 4333 * @arg RCC_IT_HSIRDY: HSI ready interrupt 4334 * @arg RCC_IT_HSERDY: HSE ready interrupt 4335 * @arg RCC_IT_CSIRDY: CSI ready interrupt 4336 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt 4337 * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt 4338 * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt 4339 * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt 4340 * @arg RCC_IT_LSECSS: LSE Clock security system interrupt 4341 * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt 4342 * @arg RCC_IT_ALL: All RCC interrupts 4343 */ 4344 #ifdef CORE_CM4 4345 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->MC_CIFR = (__INTERRUPT__)) 4346 #endif /* CORE_CM4 */ 4347 #ifdef CORE_CA7 4348 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->MP_CIFR = (__INTERRUPT__)) 4349 #endif /* CORE_CA7 */ 4350 4351 /** @brief Check the RCC's interrupt has occurred or not. 4352 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 4353 * This parameter can be one of the following values: 4354 * @arg RCC_IT_LSIRDY: LSI ready interrupt 4355 * @arg RCC_IT_LSERDY: LSE ready interrupt 4356 * @arg RCC_IT_HSIRDY: HSI ready interrupt 4357 * @arg RCC_IT_HSERDY: HSE ready interrupt 4358 * @arg RCC_IT_CSIRDY: CSI ready interrupt 4359 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt 4360 * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt 4361 * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt 4362 * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt 4363 * @arg RCC_IT_LSECSS: LSE Clock security system interrupt 4364 * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt 4365 * @arg RCC_IT_ALL: All RCC interrupts 4366 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4367 */ 4368 #ifdef CORE_CM4 4369 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->MC_CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4370 #endif /* CORE_CM4 */ 4371 #ifdef CORE_CA7 4372 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->MP_CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4373 #endif /* CORE_CA7 */ 4374 /** 4375 * @} 4376 */ 4377 /* Include RCC HAL Extension module */ 4378 #include "stm32mp1xx_hal_rcc_ex.h" 4379 4380 /* Exported functions --------------------------------------------------------*/ 4381 /** @addtogroup RCC_Exported_Functions RCC Exported Functions 4382 * @{ 4383 */ 4384 4385 /** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 4386 * @{ 4387 */ 4388 /* Initialization and de-initialization functions ******************************/ 4389 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4390 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4391 HAL_StatusTypeDef HAL_RCC_HSEConfig(uint32_t State); 4392 HAL_StatusTypeDef HAL_RCC_LSEConfig(uint32_t State); 4393 4394 HAL_StatusTypeDef RCC_PLL1_Config(RCC_PLLInitTypeDef *pll1); 4395 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct); 4396 HAL_StatusTypeDef HAL_RCC_LSEDriveConfig(uint32_t LseDriveValue); 4397 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4398 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 4399 4400 void HAL_RCC_WAKEUP_IRQHandler(void); 4401 void HAL_RCC_WAKEUP_Callback(void); 4402 void HAL_RCC_IRQHandler(void); 4403 void HAL_RCC_Callback(uint32_t Flags); 4404 void HAL_RCC_EnableHSECSS(void); 4405 4406 4407 /** 4408 * @} 4409 */ 4410 4411 /** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions 4412 * @{ 4413 */ 4414 /* Peripheral Control functions ************************************************/ 4415 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4416 /* Get frequency functions *****************************************************/ 4417 void HAL_RCC_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); 4418 void HAL_RCC_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); 4419 void HAL_RCC_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); 4420 void HAL_RCC_GetPLL4ClockFreq(PLL4_ClocksTypeDef *PLL4_Clocks); 4421 4422 uint32_t HAL_RCC_GetMPUSSFreq(void); 4423 uint32_t HAL_RCC_GetAXISSFreq(void); 4424 uint32_t HAL_RCC_GetMCUSSFreq(void); 4425 uint32_t HAL_RCC_GetACLKFreq(void); 4426 uint32_t HAL_RCC_GetHCLK1Freq(void); 4427 uint32_t HAL_RCC_GetHCLK2Freq(void); 4428 uint32_t HAL_RCC_GetHCLK3Freq(void); 4429 uint32_t HAL_RCC_GetHCLK4Freq(void); 4430 uint32_t HAL_RCC_GetHCLK5Freq(void); 4431 uint32_t HAL_RCC_GetHCLK6Freq(void); 4432 uint32_t HAL_RCC_GetMCUFreq(void); 4433 uint32_t HAL_RCC_GetFCLKFreq(void); 4434 uint32_t HAL_RCC_GetMLHCLKFreq(void); 4435 uint32_t HAL_RCC_GetPCLK1Freq(void); 4436 uint32_t HAL_RCC_GetPCLK2Freq(void); 4437 uint32_t HAL_RCC_GetPCLK3Freq(void); 4438 uint32_t HAL_RCC_GetPCLK4Freq(void); 4439 uint32_t HAL_RCC_GetPCLK5Freq(void); 4440 4441 uint32_t HAL_RCC_GetSystemCoreClockFreq(void); 4442 4443 uint32_t RCC_GetCKPERFreq(void); 4444 /** 4445 * @} 4446 */ 4447 4448 /** 4449 * @} 4450 */ 4451 4452 /* Private types -------------------------------------------------------------*/ 4453 /* Private variables ---------------------------------------------------------*/ 4454 /* Private constants ---------------------------------------------------------*/ 4455 /** @defgroup RCC_Private_Constants RCC Private Constants 4456 * @{ 4457 */ 4458 4459 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 4460 #define HSI_TIMEOUT_VALUE (100U) /* 100 ms */ 4461 #define CSI_TIMEOUT_VALUE (100U) /* 100 ms */ 4462 #define LSI_TIMEOUT_VALUE (100U) /* 100 ms */ 4463 #define PLL_TIMEOUT_VALUE (100U) /* 100 ms */ 4464 #define CLOCKSWITCH_TIMEOUT_VALUE (1000U) /* 1 s */ 4465 4466 /** 4467 * @} 4468 */ 4469 4470 /* Private macros ------------------------------------------------------------*/ 4471 /** @addtogroup RCC_Private_Macros RCC Private Macros 4472 * @{ 4473 */ 4474 4475 /** 4476 * @} 4477 */ 4478 4479 4480 /** 4481 * @} 4482 */ 4483 4484 /** 4485 * @} 4486 */ 4487 #ifdef __cplusplus 4488 } 4489 #endif 4490 4491 #endif /* __STM32MP1xx_HAL_RCC_H */ 4492 4493 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4494