1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32MP1xx_HAL_TIM_H 22 #define STM32MP1xx_HAL_TIM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 #include "stm32mp1xx_hal_dma.h" 31 32 /** @addtogroup STM32MP1xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup TIM 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup TIM_Exported_Types TIM Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief TIM Time base Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 51 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 52 53 uint32_t CounterMode; /*!< Specifies the counter mode. 54 This parameter can be a value of @ref TIM_Counter_Mode */ 55 56 uint32_t Period; /*!< Specifies the period value to be loaded into the active 57 Auto-Reload Register at the next update event. 58 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 59 60 uint32_t ClockDivision; /*!< Specifies the clock division. 61 This parameter can be a value of @ref TIM_ClockDivision */ 62 63 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 64 reaches zero, an update event is generated and counting restarts 65 from the RCR value (N). 66 This means in PWM mode that (N+1) corresponds to: 67 - the number of PWM periods in edge-aligned mode 68 - the number of half PWM period in center-aligned mode 69 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 70 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 71 72 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 73 This parameter can be a value of @ref TIM_AutoReloadPreload */ 74 } TIM_Base_InitTypeDef; 75 76 /** 77 * @brief TIM Output Compare Configuration Structure definition 78 */ 79 typedef struct 80 { 81 uint32_t OCMode; /*!< Specifies the TIM mode. 82 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 83 84 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 85 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 86 87 uint32_t OCPolarity; /*!< Specifies the output polarity. 88 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 89 90 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 91 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 92 @note This parameter is valid only for timer instances supporting break feature. */ 93 94 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 95 This parameter can be a value of @ref TIM_Output_Fast_State 96 @note This parameter is valid only in PWM1 and PWM2 mode. */ 97 98 99 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 100 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 101 @note This parameter is valid only for timer instances supporting break feature. */ 102 103 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 104 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 105 @note This parameter is valid only for timer instances supporting break feature. */ 106 } TIM_OC_InitTypeDef; 107 108 /** 109 * @brief TIM One Pulse Mode Configuration Structure definition 110 */ 111 typedef struct 112 { 113 uint32_t OCMode; /*!< Specifies the TIM mode. 114 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 115 116 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 117 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 118 119 uint32_t OCPolarity; /*!< Specifies the output polarity. 120 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 121 122 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 123 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 124 @note This parameter is valid only for timer instances supporting break feature. */ 125 126 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 127 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 128 @note This parameter is valid only for timer instances supporting break feature. */ 129 130 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 131 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 132 @note This parameter is valid only for timer instances supporting break feature. */ 133 134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 136 137 uint32_t ICSelection; /*!< Specifies the input. 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 139 140 uint32_t ICFilter; /*!< Specifies the input capture filter. 141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 142 } TIM_OnePulse_InitTypeDef; 143 144 /** 145 * @brief TIM Input Capture Configuration Structure definition 146 */ 147 typedef struct 148 { 149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 151 152 uint32_t ICSelection; /*!< Specifies the input. 153 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 154 155 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 156 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 157 158 uint32_t ICFilter; /*!< Specifies the input capture filter. 159 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 160 } TIM_IC_InitTypeDef; 161 162 /** 163 * @brief TIM Encoder Configuration Structure definition 164 */ 165 typedef struct 166 { 167 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 168 This parameter can be a value of @ref TIM_Encoder_Mode */ 169 170 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 171 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 172 173 uint32_t IC1Selection; /*!< Specifies the input. 174 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 175 176 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 177 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 178 179 uint32_t IC1Filter; /*!< Specifies the input capture filter. 180 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 181 182 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 183 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 184 185 uint32_t IC2Selection; /*!< Specifies the input. 186 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 187 188 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 190 191 uint32_t IC2Filter; /*!< Specifies the input capture filter. 192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 193 } TIM_Encoder_InitTypeDef; 194 195 /** 196 * @brief Clock Configuration Handle Structure definition 197 */ 198 typedef struct 199 { 200 uint32_t ClockSource; /*!< TIM clock sources 201 This parameter can be a value of @ref TIM_Clock_Source */ 202 uint32_t ClockPolarity; /*!< TIM clock polarity 203 This parameter can be a value of @ref TIM_Clock_Polarity */ 204 uint32_t ClockPrescaler; /*!< TIM clock prescaler 205 This parameter can be a value of @ref TIM_Clock_Prescaler */ 206 uint32_t ClockFilter; /*!< TIM clock filter 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 208 } TIM_ClockConfigTypeDef; 209 210 /** 211 * @brief TIM Clear Input Configuration Handle Structure definition 212 */ 213 typedef struct 214 { 215 uint32_t ClearInputState; /*!< TIM clear Input state 216 This parameter can be ENABLE or DISABLE */ 217 uint32_t ClearInputSource; /*!< TIM clear Input sources 218 This parameter can be a value of @ref TIM_ClearInput_Source */ 219 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 220 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 221 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 222 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ 223 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 224 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 225 } TIM_ClearInputConfigTypeDef; 226 227 /** 228 * @brief TIM Master configuration Structure definition 229 * @note Advanced timers provide TRGO2 internal line which is redirected 230 * to the ADC 231 */ 232 typedef struct 233 { 234 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 235 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 236 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 237 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 238 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 239 This parameter can be a value of @ref TIM_Master_Slave_Mode 240 @note When the Master/slave mode is enabled, the effect of 241 an event on the trigger input (TRGI) is delayed to allow a 242 perfect synchronization between the current timer and its 243 slaves (through TRGO). It is not mandatory in case of timer 244 synchronization mode. */ 245 } TIM_MasterConfigTypeDef; 246 247 /** 248 * @brief TIM Slave configuration Structure definition 249 */ 250 typedef struct 251 { 252 uint32_t SlaveMode; /*!< Slave mode selection 253 This parameter can be a value of @ref TIM_Slave_Mode */ 254 uint32_t InputTrigger; /*!< Input Trigger source 255 This parameter can be a value of @ref TIM_Trigger_Selection */ 256 uint32_t TriggerPolarity; /*!< Input Trigger polarity 257 This parameter can be a value of @ref TIM_Trigger_Polarity */ 258 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 259 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 260 uint32_t TriggerFilter; /*!< Input trigger filter 261 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 262 263 } TIM_SlaveConfigTypeDef; 264 265 /** 266 * @brief TIM Break input(s) and Dead time configuration Structure definition 267 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 268 * filter and polarity. 269 */ 270 typedef struct 271 { 272 uint32_t OffStateRunMode; /*!< TIM off state in run mode 273 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 274 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 275 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 276 uint32_t LockLevel; /*!< TIM Lock level 277 This parameter can be a value of @ref TIM_Lock_level */ 278 uint32_t DeadTime; /*!< TIM dead Time 279 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 280 uint32_t BreakState; /*!< TIM Break State 281 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 282 uint32_t BreakPolarity; /*!< TIM Break input polarity 283 This parameter can be a value of @ref TIM_Break_Polarity */ 284 uint32_t BreakFilter; /*!< Specifies the break input filter. 285 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 286 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. 287 This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ 288 uint32_t Break2State; /*!< TIM Break2 State 289 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 290 uint32_t Break2Polarity; /*!< TIM Break2 input polarity 291 This parameter can be a value of @ref TIM_Break2_Polarity */ 292 uint32_t Break2Filter; /*!< TIM break2 input filter. 293 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 294 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. 295 This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ 296 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 297 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 298 } TIM_BreakDeadTimeConfigTypeDef; 299 300 /** 301 * @brief HAL State structures definition 302 */ 303 typedef enum 304 { 305 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 306 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 307 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 308 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 309 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 310 } HAL_TIM_StateTypeDef; 311 312 /** 313 * @brief HAL Active channel structures definition 314 */ 315 typedef enum 316 { 317 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 318 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 319 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 320 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 321 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 322 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 323 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 324 } HAL_TIM_ActiveChannel; 325 326 /** 327 * @brief TIM Time Base Handle Structure definition 328 */ 329 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 330 typedef struct __TIM_HandleTypeDef 331 #else 332 typedef struct 333 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 334 { 335 TIM_TypeDef *Instance; /*!< Register base address */ 336 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 337 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 338 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 339 This array is accessed by a @ref DMA_Handle_index */ 340 HAL_LockTypeDef Lock; /*!< Locking object */ 341 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 342 343 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 344 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 345 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 346 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 347 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 348 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 349 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 350 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 351 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 352 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 353 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 354 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 355 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 356 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 357 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 358 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 359 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 360 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 361 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 362 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 363 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 364 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 365 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 366 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 367 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 368 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 369 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 370 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 371 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 372 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 373 } TIM_HandleTypeDef; 374 375 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 376 /** 377 * @brief HAL TIM Callback ID enumeration definition 378 */ 379 typedef enum 380 { 381 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 382 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 383 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 384 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 385 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 386 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 387 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 388 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 389 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 390 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 391 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 392 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 393 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 394 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 395 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 396 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 397 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 398 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 399 400 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 401 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 402 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 403 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 404 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 405 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 406 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 407 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 408 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 409 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 410 } HAL_TIM_CallbackIDTypeDef; 411 412 /** 413 * @brief HAL TIM Callback pointer definition 414 */ 415 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 416 417 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 418 419 /** 420 * @} 421 */ 422 /* End of exported types -----------------------------------------------------*/ 423 424 /* Exported constants --------------------------------------------------------*/ 425 /** @defgroup TIM_Exported_Constants TIM Exported Constants 426 * @{ 427 */ 428 429 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 430 * @{ 431 */ 432 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 433 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 434 /** 435 * @} 436 */ 437 438 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 439 * @{ 440 */ 441 #define TIM_DMABASE_CR1 0x00000000U 442 #define TIM_DMABASE_CR2 0x00000001U 443 #define TIM_DMABASE_SMCR 0x00000002U 444 #define TIM_DMABASE_DIER 0x00000003U 445 #define TIM_DMABASE_SR 0x00000004U 446 #define TIM_DMABASE_EGR 0x00000005U 447 #define TIM_DMABASE_CCMR1 0x00000006U 448 #define TIM_DMABASE_CCMR2 0x00000007U 449 #define TIM_DMABASE_CCER 0x00000008U 450 #define TIM_DMABASE_CNT 0x00000009U 451 #define TIM_DMABASE_PSC 0x0000000AU 452 #define TIM_DMABASE_ARR 0x0000000BU 453 #define TIM_DMABASE_RCR 0x0000000CU 454 #define TIM_DMABASE_CCR1 0x0000000DU 455 #define TIM_DMABASE_CCR2 0x0000000EU 456 #define TIM_DMABASE_CCR3 0x0000000FU 457 #define TIM_DMABASE_CCR4 0x00000010U 458 #define TIM_DMABASE_BDTR 0x00000011U 459 #define TIM_DMABASE_DCR 0x00000012U 460 #define TIM_DMABASE_DMAR 0x00000013U 461 #define TIM_DMABASE_CCMR3 0x00000015U 462 #define TIM_DMABASE_CCR5 0x00000016U 463 #define TIM_DMABASE_CCR6 0x00000017U 464 #define TIM_DMABASE_AF1 0x00000018U 465 #define TIM_DMABASE_AF2 0x00000019U 466 #define TIM_DMABASE_TISEL 0x00000020U 467 /** 468 * @} 469 */ 470 471 /** @defgroup TIM_Event_Source TIM Event Source 472 * @{ 473 */ 474 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 475 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 476 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 477 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 478 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 479 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 480 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 481 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 482 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 483 /** 484 * @} 485 */ 486 487 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 488 * @{ 489 */ 490 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 491 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 492 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 493 /** 494 * @} 495 */ 496 497 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 498 * @{ 499 */ 500 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 501 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 502 /** 503 * @} 504 */ 505 506 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 507 * @{ 508 */ 509 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 510 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 511 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 512 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup TIM_Counter_Mode TIM Counter Mode 518 * @{ 519 */ 520 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 521 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 522 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 523 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 524 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup TIM_ClockDivision TIM Clock Division 530 * @{ 531 */ 532 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 533 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 534 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 540 * @{ 541 */ 542 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 543 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 544 /** 545 * @} 546 */ 547 548 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 549 * @{ 550 */ 551 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 552 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 553 554 /** 555 * @} 556 */ 557 558 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 559 * @{ 560 */ 561 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 562 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 563 /** 564 * @} 565 */ 566 567 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 568 * @{ 569 */ 570 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 571 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 572 /** 573 * @} 574 */ 575 576 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 577 * @{ 578 */ 579 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 580 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 581 /** 582 * @} 583 */ 584 585 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 586 * @{ 587 */ 588 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 589 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 595 * @{ 596 */ 597 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 598 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 604 * @{ 605 */ 606 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 607 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 608 /** 609 * @} 610 */ 611 612 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 613 * @{ 614 */ 615 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 616 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 617 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 618 /** 619 * @} 620 */ 621 622 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 623 * @{ 624 */ 625 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 626 connected to IC1, IC2, IC3 or IC4, respectively */ 627 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 628 connected to IC2, IC1, IC4 or IC3, respectively */ 629 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 630 /** 631 * @} 632 */ 633 634 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 635 * @{ 636 */ 637 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 638 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 639 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 640 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 641 /** 642 * @} 643 */ 644 645 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 646 * @{ 647 */ 648 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 649 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 650 /** 651 * @} 652 */ 653 654 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 655 * @{ 656 */ 657 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 658 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 659 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 660 /** 661 * @} 662 */ 663 664 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 665 * @{ 666 */ 667 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 668 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 669 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 670 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 671 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 672 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 673 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 674 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 675 /** 676 * @} 677 */ 678 679 /** @defgroup TIM_Commutation_Source TIM Commutation Source 680 * @{ 681 */ 682 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 683 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 684 /** 685 * @} 686 */ 687 688 /** @defgroup TIM_DMA_sources TIM DMA Sources 689 * @{ 690 */ 691 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 692 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 693 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 694 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 695 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 696 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 697 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 698 /** 699 * @} 700 */ 701 702 /** @defgroup TIM_Flag_definition TIM Flag Definition 703 * @{ 704 */ 705 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 706 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 707 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 708 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 709 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 710 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 711 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 712 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 713 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 714 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 715 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 716 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 717 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 718 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 719 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 720 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 721 /** 722 * @} 723 */ 724 725 /** @defgroup TIM_Channel TIM Channel 726 * @{ 727 */ 728 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 729 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 730 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 731 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 732 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 733 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 734 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 735 /** 736 * @} 737 */ 738 739 /** @defgroup TIM_Clock_Source TIM Clock Source 740 * @{ 741 */ 742 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 743 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 744 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 745 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 746 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 747 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 748 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 749 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 750 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 751 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 752 /** 753 * @} 754 */ 755 756 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 757 * @{ 758 */ 759 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 760 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 761 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 762 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 763 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 764 /** 765 * @} 766 */ 767 768 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 769 * @{ 770 */ 771 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 772 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 773 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 774 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 775 /** 776 * @} 777 */ 778 779 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 780 * @{ 781 */ 782 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 783 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 784 /** 785 * @} 786 */ 787 788 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 789 * @{ 790 */ 791 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 792 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 793 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 794 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 795 /** 796 * @} 797 */ 798 799 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 800 * @{ 801 */ 802 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 803 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 804 /** 805 * @} 806 */ 807 808 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 809 * @{ 810 */ 811 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 812 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 813 /** 814 * @} 815 */ 816 /** @defgroup TIM_Lock_level TIM Lock level 817 * @{ 818 */ 819 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 820 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 821 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 822 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 823 /** 824 * @} 825 */ 826 827 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 828 * @{ 829 */ 830 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 831 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 832 /** 833 * @} 834 */ 835 836 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 837 * @{ 838 */ 839 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 840 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 841 /** 842 * @} 843 */ 844 845 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode 846 * @{ 847 */ 848 #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 849 #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 850 /** 851 * @} 852 */ 853 854 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 855 * @{ 856 */ 857 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 858 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 859 /** 860 * @} 861 */ 862 863 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 864 * @{ 865 */ 866 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 867 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 868 /** 869 * @} 870 */ 871 872 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode 873 * @{ 874 */ 875 #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ 876 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ 877 /** 878 * @} 879 */ 880 881 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 882 * @{ 883 */ 884 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 885 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 886 (if none of the break inputs BRK and BRK2 is active) */ 887 /** 888 * @} 889 */ 890 891 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 892 * @{ 893 */ 894 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 895 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ 896 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ 897 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ 898 /** 899 * @} 900 */ 901 902 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 903 * @{ 904 */ 905 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 906 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 907 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 908 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 909 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 910 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 911 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 912 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 913 /** 914 * @} 915 */ 916 917 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 918 * @{ 919 */ 920 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 921 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 922 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 923 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 924 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 925 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 926 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 927 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 928 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 929 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 930 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 931 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 932 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 933 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 934 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 935 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 936 /** 937 * @} 938 */ 939 940 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 941 * @{ 942 */ 943 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 944 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 945 /** 946 * @} 947 */ 948 949 /** @defgroup TIM_Slave_Mode TIM Slave mode 950 * @{ 951 */ 952 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 953 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 954 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 955 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 956 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 957 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 958 /** 959 * @} 960 */ 961 962 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 963 * @{ 964 */ 965 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 966 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 967 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 968 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 969 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 970 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 971 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 972 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 973 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 974 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 975 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 976 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 977 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 978 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 979 /** 980 * @} 981 */ 982 983 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 984 * @{ 985 */ 986 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 987 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 988 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 989 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 990 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 991 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 992 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 993 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 994 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 995 /** 996 * @} 997 */ 998 999 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1000 * @{ 1001 */ 1002 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1003 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1004 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1005 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1006 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1007 /** 1008 * @} 1009 */ 1010 1011 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1012 * @{ 1013 */ 1014 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1015 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1016 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1017 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1018 /** 1019 * @} 1020 */ 1021 1022 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1023 * @{ 1024 */ 1025 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1026 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1032 * @{ 1033 */ 1034 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1035 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1036 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1037 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1038 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1039 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1040 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1041 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1042 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1043 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1044 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1045 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1046 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1047 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1048 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1049 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1050 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1051 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1052 /** 1053 * @} 1054 */ 1055 1056 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1057 * @{ 1058 */ 1059 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1060 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1061 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1062 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1063 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1064 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1065 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1066 /** 1067 * @} 1068 */ 1069 1070 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1071 * @{ 1072 */ 1073 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1074 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1075 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1076 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1077 /** 1078 * @} 1079 */ 1080 1081 /** @defgroup TIM_Break_System TIM Break System 1082 * @{ 1083 */ 1084 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1085 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 1086 /** 1087 * @} 1088 */ 1089 1090 /** 1091 * @} 1092 */ 1093 /* End of exported constants -------------------------------------------------*/ 1094 1095 /* Exported macros -----------------------------------------------------------*/ 1096 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1097 * @{ 1098 */ 1099 1100 /** @brief Reset TIM handle state. 1101 * @param __HANDLE__ TIM handle. 1102 * @retval None 1103 */ 1104 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1105 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1106 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1107 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1108 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1109 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1110 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1111 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1112 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1113 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1114 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1115 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1116 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1117 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1118 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1119 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1120 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1121 } while(0) 1122 #else 1123 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 1124 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1125 1126 /** 1127 * @brief Enable the TIM peripheral. 1128 * @param __HANDLE__ TIM handle 1129 * @retval None 1130 */ 1131 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1132 1133 /** 1134 * @brief Enable the TIM main Output. 1135 * @param __HANDLE__ TIM handle 1136 * @retval None 1137 */ 1138 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1139 1140 /** 1141 * @brief Disable the TIM peripheral. 1142 * @param __HANDLE__ TIM handle 1143 * @retval None 1144 */ 1145 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1146 do { \ 1147 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1148 { \ 1149 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1150 { \ 1151 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1152 } \ 1153 } \ 1154 } while(0) 1155 1156 /** 1157 * @brief Disable the TIM main Output. 1158 * @param __HANDLE__ TIM handle 1159 * @retval None 1160 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 1161 */ 1162 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1163 do { \ 1164 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1165 { \ 1166 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1167 { \ 1168 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1169 } \ 1170 } \ 1171 } while(0) 1172 1173 /** 1174 * @brief Disable the TIM main Output. 1175 * @param __HANDLE__ TIM handle 1176 * @retval None 1177 * @note The Main Output Enable of a timer instance is disabled unconditionally 1178 */ 1179 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1180 1181 /** @brief Enable the specified TIM interrupt. 1182 * @param __HANDLE__ specifies the TIM Handle. 1183 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1184 * This parameter can be one of the following values: 1185 * @arg TIM_IT_UPDATE: Update interrupt 1186 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1187 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1188 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1189 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1190 * @arg TIM_IT_COM: Commutation interrupt 1191 * @arg TIM_IT_TRIGGER: Trigger interrupt 1192 * @arg TIM_IT_BREAK: Break interrupt 1193 * @retval None 1194 */ 1195 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1196 1197 /** @brief Disable the specified TIM interrupt. 1198 * @param __HANDLE__ specifies the TIM Handle. 1199 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1200 * This parameter can be one of the following values: 1201 * @arg TIM_IT_UPDATE: Update interrupt 1202 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1203 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1204 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1205 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1206 * @arg TIM_IT_COM: Commutation interrupt 1207 * @arg TIM_IT_TRIGGER: Trigger interrupt 1208 * @arg TIM_IT_BREAK: Break interrupt 1209 * @retval None 1210 */ 1211 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1212 1213 /** @brief Enable the specified DMA request. 1214 * @param __HANDLE__ specifies the TIM Handle. 1215 * @param __DMA__ specifies the TIM DMA request to enable. 1216 * This parameter can be one of the following values: 1217 * @arg TIM_DMA_UPDATE: Update DMA request 1218 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1219 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1220 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1221 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1222 * @arg TIM_DMA_COM: Commutation DMA request 1223 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1224 * @retval None 1225 */ 1226 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1227 1228 /** @brief Disable the specified DMA request. 1229 * @param __HANDLE__ specifies the TIM Handle. 1230 * @param __DMA__ specifies the TIM DMA request to disable. 1231 * This parameter can be one of the following values: 1232 * @arg TIM_DMA_UPDATE: Update DMA request 1233 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1234 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1235 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1236 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1237 * @arg TIM_DMA_COM: Commutation DMA request 1238 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1239 * @retval None 1240 */ 1241 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1242 1243 /** @brief Check whether the specified TIM interrupt flag is set or not. 1244 * @param __HANDLE__ specifies the TIM Handle. 1245 * @param __FLAG__ specifies the TIM interrupt flag to check. 1246 * This parameter can be one of the following values: 1247 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1248 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1249 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1250 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1251 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1252 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1253 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1254 * @arg TIM_FLAG_COM: Commutation interrupt flag 1255 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1256 * @arg TIM_FLAG_BREAK: Break interrupt flag 1257 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1258 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1259 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1260 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1261 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1262 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1263 * @retval The new state of __FLAG__ (TRUE or FALSE). 1264 */ 1265 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1266 1267 /** @brief Clear the specified TIM interrupt flag. 1268 * @param __HANDLE__ specifies the TIM Handle. 1269 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1270 * This parameter can be one of the following values: 1271 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1272 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1273 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1274 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1275 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1276 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1277 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1278 * @arg TIM_FLAG_COM: Commutation interrupt flag 1279 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1280 * @arg TIM_FLAG_BREAK: Break interrupt flag 1281 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1282 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1283 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1284 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1285 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1286 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1287 * @retval The new state of __FLAG__ (TRUE or FALSE). 1288 */ 1289 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1290 1291 /** 1292 * @brief Check whether the specified TIM interrupt source is enabled or not. 1293 * @param __HANDLE__ TIM handle 1294 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1295 * This parameter can be one of the following values: 1296 * @arg TIM_IT_UPDATE: Update interrupt 1297 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1298 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1299 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1300 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1301 * @arg TIM_IT_COM: Commutation interrupt 1302 * @arg TIM_IT_TRIGGER: Trigger interrupt 1303 * @arg TIM_IT_BREAK: Break interrupt 1304 * @retval The state of TIM_IT (SET or RESET). 1305 */ 1306 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1307 == (__INTERRUPT__)) ? SET : RESET) 1308 1309 /** @brief Clear the TIM interrupt pending bits. 1310 * @param __HANDLE__ TIM handle 1311 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1312 * This parameter can be one of the following values: 1313 * @arg TIM_IT_UPDATE: Update interrupt 1314 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1315 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1316 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1317 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1318 * @arg TIM_IT_COM: Commutation interrupt 1319 * @arg TIM_IT_TRIGGER: Trigger interrupt 1320 * @arg TIM_IT_BREAK: Break interrupt 1321 * @retval None 1322 */ 1323 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1324 1325 /** 1326 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1327 * @param __HANDLE__ TIM handle. 1328 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1329 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1330 mode. 1331 */ 1332 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1333 1334 /** 1335 * @brief Set the TIM Prescaler on runtime. 1336 * @param __HANDLE__ TIM handle. 1337 * @param __PRESC__ specifies the Prescaler new value. 1338 * @retval None 1339 */ 1340 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1341 1342 /** 1343 * @brief Set the TIM Counter Register value on runtime. 1344 * @param __HANDLE__ TIM handle. 1345 * @param __COUNTER__ specifies the Counter register new value. 1346 * @retval None 1347 */ 1348 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1349 1350 /** 1351 * @brief Get the TIM Counter Register value on runtime. 1352 * @param __HANDLE__ TIM handle. 1353 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1354 */ 1355 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1356 1357 /** 1358 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1359 * @param __HANDLE__ TIM handle. 1360 * @param __AUTORELOAD__ specifies the Counter register new value. 1361 * @retval None 1362 */ 1363 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1364 do{ \ 1365 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1366 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1367 } while(0) 1368 1369 /** 1370 * @brief Get the TIM Autoreload Register value on runtime. 1371 * @param __HANDLE__ TIM handle. 1372 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1373 */ 1374 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1375 1376 /** 1377 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1378 * @param __HANDLE__ TIM handle. 1379 * @param __CKD__ specifies the clock division value. 1380 * This parameter can be one of the following value: 1381 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1382 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1383 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1384 * @retval None 1385 */ 1386 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1387 do{ \ 1388 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1389 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1390 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1391 } while(0) 1392 1393 /** 1394 * @brief Get the TIM Clock Division value on runtime. 1395 * @param __HANDLE__ TIM handle. 1396 * @retval The clock division can be one of the following values: 1397 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1398 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1399 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1400 */ 1401 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1402 1403 /** 1404 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 1405 * @param __HANDLE__ TIM handle. 1406 * @param __CHANNEL__ TIM Channels to be configured. 1407 * This parameter can be one of the following values: 1408 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1409 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1410 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1411 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1412 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1413 * This parameter can be one of the following values: 1414 * @arg TIM_ICPSC_DIV1: no prescaler 1415 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1416 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1417 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1418 * @retval None 1419 */ 1420 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1421 do{ \ 1422 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1423 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1424 } while(0) 1425 1426 /** 1427 * @brief Get the TIM Input Capture prescaler on runtime. 1428 * @param __HANDLE__ TIM handle. 1429 * @param __CHANNEL__ TIM Channels to be configured. 1430 * This parameter can be one of the following values: 1431 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1432 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1433 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1434 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1435 * @retval The input capture prescaler can be one of the following values: 1436 * @arg TIM_ICPSC_DIV1: no prescaler 1437 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1438 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1439 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1440 */ 1441 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1442 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1443 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1444 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1445 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1446 1447 /** 1448 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1449 * @param __HANDLE__ TIM handle. 1450 * @param __CHANNEL__ TIM Channels to be configured. 1451 * This parameter can be one of the following values: 1452 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1453 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1454 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1455 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1456 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1457 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1458 * @param __COMPARE__ specifies the Capture Compare register new value. 1459 * @retval None 1460 */ 1461 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1462 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1463 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1464 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1465 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1466 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1467 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1468 1469 /** 1470 * @brief Get the TIM Capture Compare Register value on runtime. 1471 * @param __HANDLE__ TIM handle. 1472 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1473 * This parameter can be one of the following values: 1474 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1475 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1476 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1477 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1478 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1479 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1480 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1481 */ 1482 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1483 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1484 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1485 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1486 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1487 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1488 ((__HANDLE__)->Instance->CCR6)) 1489 1490 /** 1491 * @brief Set the TIM Output compare preload. 1492 * @param __HANDLE__ TIM handle. 1493 * @param __CHANNEL__ TIM Channels to be configured. 1494 * This parameter can be one of the following values: 1495 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1496 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1497 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1498 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1499 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1500 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1501 * @retval None 1502 */ 1503 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1504 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1505 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1506 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1507 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1508 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1509 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1510 1511 /** 1512 * @brief Reset the TIM Output compare preload. 1513 * @param __HANDLE__ TIM handle. 1514 * @param __CHANNEL__ TIM Channels to be configured. 1515 * This parameter can be one of the following values: 1516 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1517 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1518 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1519 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1520 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1521 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1522 * @retval None 1523 */ 1524 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1525 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1526 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1527 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1528 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1529 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1530 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1531 1532 /** 1533 * @brief Enable fast mode for a given channel. 1534 * @param __HANDLE__ TIM handle. 1535 * @param __CHANNEL__ TIM Channels to be configured. 1536 * This parameter can be one of the following values: 1537 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1538 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1539 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1540 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1541 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1542 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1543 * @note When fast mode is enabled an active edge on the trigger input acts 1544 * like a compare match on CCx output. Delay to sample the trigger 1545 * input and to activate CCx output is reduced to 3 clock cycles. 1546 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1547 * @retval None 1548 */ 1549 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1550 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1551 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1552 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1553 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1554 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1555 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1556 1557 /** 1558 * @brief Disable fast mode for a given channel. 1559 * @param __HANDLE__ TIM handle. 1560 * @param __CHANNEL__ TIM Channels to be configured. 1561 * This parameter can be one of the following values: 1562 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1563 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1564 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1565 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1566 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1567 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1568 * @note When fast mode is disabled CCx output behaves normally depending 1569 * on counter and CCRx values even when the trigger is ON. The minimum 1570 * delay to activate CCx output when an active edge occurs on the 1571 * trigger input is 5 clock cycles. 1572 * @retval None 1573 */ 1574 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1575 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1576 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1577 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1578 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1579 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1580 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1581 1582 /** 1583 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1584 * @param __HANDLE__ TIM handle. 1585 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1586 * overflow/underflow generates an update interrupt or DMA request (if 1587 * enabled) 1588 * @retval None 1589 */ 1590 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1591 1592 /** 1593 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1594 * @param __HANDLE__ TIM handle. 1595 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1596 * following events generate an update interrupt or DMA request (if 1597 * enabled): 1598 * _ Counter overflow underflow 1599 * _ Setting the UG bit 1600 * _ Update generation through the slave mode controller 1601 * @retval None 1602 */ 1603 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1604 1605 /** 1606 * @brief Set the TIM Capture x input polarity on runtime. 1607 * @param __HANDLE__ TIM handle. 1608 * @param __CHANNEL__ TIM Channels to be configured. 1609 * This parameter can be one of the following values: 1610 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1611 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1612 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1613 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1614 * @param __POLARITY__ Polarity for TIx source 1615 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1616 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1617 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1618 * @retval None 1619 */ 1620 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1621 do{ \ 1622 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1623 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1624 }while(0) 1625 1626 /** 1627 * @} 1628 */ 1629 /* End of exported macros ----------------------------------------------------*/ 1630 1631 /* Private constants ---------------------------------------------------------*/ 1632 /** @defgroup TIM_Private_Constants TIM Private Constants 1633 * @{ 1634 */ 1635 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1636 channels have been disabled */ 1637 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1638 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1639 /** 1640 * @} 1641 */ 1642 /* End of private constants --------------------------------------------------*/ 1643 1644 /* Private macros ------------------------------------------------------------*/ 1645 /** @defgroup TIM_Private_Macros TIM Private Macros 1646 * @{ 1647 */ 1648 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1649 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1650 1651 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1652 ((__BASE__) == TIM_DMABASE_CR2) || \ 1653 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1654 ((__BASE__) == TIM_DMABASE_DIER) || \ 1655 ((__BASE__) == TIM_DMABASE_SR) || \ 1656 ((__BASE__) == TIM_DMABASE_EGR) || \ 1657 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1658 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1659 ((__BASE__) == TIM_DMABASE_CCER) || \ 1660 ((__BASE__) == TIM_DMABASE_CNT) || \ 1661 ((__BASE__) == TIM_DMABASE_PSC) || \ 1662 ((__BASE__) == TIM_DMABASE_ARR) || \ 1663 ((__BASE__) == TIM_DMABASE_RCR) || \ 1664 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1665 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1666 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1667 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1668 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1669 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1670 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1671 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1672 ((__BASE__) == TIM_DMABASE_TISEL)) 1673 1674 1675 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1676 1677 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1678 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1679 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1680 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1681 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1682 1683 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1684 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1685 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1686 1687 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1688 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1689 1690 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1691 ((__STATE__) == TIM_OCFAST_ENABLE)) 1692 1693 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1694 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1695 1696 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1697 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1698 1699 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1700 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1701 1702 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1703 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1704 1705 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1706 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1707 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1708 1709 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1710 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1711 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1712 1713 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1714 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1715 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1716 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1717 1718 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1719 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1720 1721 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1722 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1723 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1724 1725 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1726 1727 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1728 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1729 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1730 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1731 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1732 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1733 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1734 1735 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1736 ((__CHANNEL__) == TIM_CHANNEL_2)) 1737 1738 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1739 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1740 ((__CHANNEL__) == TIM_CHANNEL_3)) 1741 1742 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1743 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1744 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1745 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1746 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1747 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1748 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1749 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1750 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1751 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 1752 1753 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1754 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1755 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1756 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1757 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1758 1759 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1760 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1761 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1762 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1763 1764 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1765 1766 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1767 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1768 1769 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1770 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1771 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1772 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1773 1774 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1775 1776 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1777 ((__STATE__) == TIM_OSSR_DISABLE)) 1778 1779 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1780 ((__STATE__) == TIM_OSSI_DISABLE)) 1781 1782 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1783 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1784 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1785 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1786 1787 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1788 1789 1790 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1791 ((__STATE__) == TIM_BREAK_DISABLE)) 1792 1793 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1794 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1795 1796 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ 1797 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) 1798 1799 1800 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 1801 ((__STATE__) == TIM_BREAK2_DISABLE)) 1802 1803 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 1804 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 1805 1806 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ 1807 ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) 1808 1809 1810 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1811 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1812 1813 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 1814 1815 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1816 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1817 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1818 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1819 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1820 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1821 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1822 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1823 1824 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 1825 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 1826 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 1827 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 1828 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 1829 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 1830 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1831 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1832 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 1833 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 1834 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 1835 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 1836 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 1837 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 1838 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 1839 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 1840 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 1841 1842 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1843 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1844 1845 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1846 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1847 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1848 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1849 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 1850 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1851 1852 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1853 ((__MODE__) == TIM_OCMODE_PWM2) || \ 1854 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 1855 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 1856 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 1857 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 1858 1859 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1860 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1861 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1862 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1863 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1864 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 1865 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 1866 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 1867 1868 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1869 ((__SELECTION__) == TIM_TS_ITR1) || \ 1870 ((__SELECTION__) == TIM_TS_ITR2) || \ 1871 ((__SELECTION__) == TIM_TS_ITR3) || \ 1872 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1873 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1874 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1875 ((__SELECTION__) == TIM_TS_ETRF)) 1876 1877 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1878 ((__SELECTION__) == TIM_TS_ITR1) || \ 1879 ((__SELECTION__) == TIM_TS_ITR2) || \ 1880 ((__SELECTION__) == TIM_TS_ITR3) || \ 1881 ((__SELECTION__) == TIM_TS_NONE)) 1882 1883 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1884 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1885 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1886 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1887 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1888 1889 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1890 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1891 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1892 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1893 1894 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1895 1896 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1897 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1898 1899 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1900 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1901 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1902 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 1903 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 1904 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 1905 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 1906 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 1907 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 1908 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 1909 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 1910 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 1911 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 1912 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 1913 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 1914 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 1915 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 1916 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 1917 1918 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1919 1920 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 1921 1922 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 1923 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 1924 1925 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 1926 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1927 1928 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1929 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1930 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1931 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1932 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1933 1934 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1935 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 1936 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 1937 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 1938 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 1939 1940 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1941 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1942 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1943 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1944 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 1945 1946 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1947 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1948 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1949 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1950 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 1951 1952 /** 1953 * @} 1954 */ 1955 /* End of private macros -----------------------------------------------------*/ 1956 1957 /* Include TIM HAL Extended module */ 1958 #include "stm32mp1xx_hal_tim_ex.h" 1959 1960 /* Exported functions --------------------------------------------------------*/ 1961 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 1962 * @{ 1963 */ 1964 1965 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 1966 * @brief Time Base functions 1967 * @{ 1968 */ 1969 /* Time Base functions ********************************************************/ 1970 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1971 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1972 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 1973 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 1974 /* Blocking mode: Polling */ 1975 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 1976 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 1977 /* Non-Blocking mode: Interrupt */ 1978 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 1979 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 1980 /* Non-Blocking mode: DMA */ 1981 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 1982 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 1983 /** 1984 * @} 1985 */ 1986 1987 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 1988 * @brief TIM Output Compare functions 1989 * @{ 1990 */ 1991 /* Timer Output Compare functions *********************************************/ 1992 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 1993 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 1994 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 1995 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 1996 /* Blocking mode: Polling */ 1997 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1998 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1999 /* Non-Blocking mode: Interrupt */ 2000 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2001 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2002 /* Non-Blocking mode: DMA */ 2003 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2004 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2005 /** 2006 * @} 2007 */ 2008 2009 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2010 * @brief TIM PWM functions 2011 * @{ 2012 */ 2013 /* Timer PWM functions ********************************************************/ 2014 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2015 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2016 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2017 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2018 /* Blocking mode: Polling */ 2019 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2020 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2021 /* Non-Blocking mode: Interrupt */ 2022 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2023 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2024 /* Non-Blocking mode: DMA */ 2025 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2026 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2027 /** 2028 * @} 2029 */ 2030 2031 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2032 * @brief TIM Input Capture functions 2033 * @{ 2034 */ 2035 /* Timer Input Capture functions **********************************************/ 2036 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2037 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2038 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2039 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2040 /* Blocking mode: Polling */ 2041 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2042 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2043 /* Non-Blocking mode: Interrupt */ 2044 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2045 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2046 /* Non-Blocking mode: DMA */ 2047 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2048 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2049 /** 2050 * @} 2051 */ 2052 2053 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2054 * @brief TIM One Pulse functions 2055 * @{ 2056 */ 2057 /* Timer One Pulse functions **************************************************/ 2058 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2059 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2060 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2061 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2062 /* Blocking mode: Polling */ 2063 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2064 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2065 /* Non-Blocking mode: Interrupt */ 2066 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2067 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2068 /** 2069 * @} 2070 */ 2071 2072 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2073 * @brief TIM Encoder functions 2074 * @{ 2075 */ 2076 /* Timer Encoder functions ****************************************************/ 2077 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2078 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2079 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2080 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2081 /* Blocking mode: Polling */ 2082 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2083 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2084 /* Non-Blocking mode: Interrupt */ 2085 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2086 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2087 /* Non-Blocking mode: DMA */ 2088 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2089 uint32_t *pData2, uint16_t Length); 2090 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2091 /** 2092 * @} 2093 */ 2094 2095 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2096 * @brief IRQ handler management 2097 * @{ 2098 */ 2099 /* Interrupt Handler functions ***********************************************/ 2100 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2101 /** 2102 * @} 2103 */ 2104 2105 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2106 * @brief Peripheral Control functions 2107 * @{ 2108 */ 2109 /* Control functions *********************************************************/ 2110 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2111 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2112 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2113 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2114 uint32_t OutputChannel, uint32_t InputChannel); 2115 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 2116 uint32_t Channel); 2117 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2118 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2119 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2120 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2121 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2122 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2123 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2124 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2125 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2126 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2127 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2128 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2129 /** 2130 * @} 2131 */ 2132 2133 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2134 * @brief TIM Callbacks functions 2135 * @{ 2136 */ 2137 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2138 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2139 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2140 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2141 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2142 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2143 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2144 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2145 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2146 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2147 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2148 2149 /* Callbacks Register/UnRegister functions ***********************************/ 2150 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2151 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2152 pTIM_CallbackTypeDef pCallback); 2153 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2154 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2155 2156 /** 2157 * @} 2158 */ 2159 2160 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2161 * @brief Peripheral State functions 2162 * @{ 2163 */ 2164 /* Peripheral State functions ************************************************/ 2165 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2166 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2167 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2168 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2169 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2170 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2171 /** 2172 * @} 2173 */ 2174 2175 /** 2176 * @} 2177 */ 2178 /* End of exported functions -------------------------------------------------*/ 2179 2180 /* Private functions----------------------------------------------------------*/ 2181 /** @defgroup TIM_Private_Functions TIM Private Functions 2182 * @{ 2183 */ 2184 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2185 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2186 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2187 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2188 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2189 2190 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 2191 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2192 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2193 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2194 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2195 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2196 2197 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2198 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2199 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2200 2201 /** 2202 * @} 2203 */ 2204 /* End of private functions --------------------------------------------------*/ 2205 2206 /** 2207 * @} 2208 */ 2209 2210 /** 2211 * @} 2212 */ 2213 2214 #ifdef __cplusplus 2215 } 2216 #endif 2217 2218 #endif /* STM32MP1xx_HAL_TIM_H */ 2219 2220 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2221