1 /** 2 * drivers/usb/host/sunxi-hci.h 3 * (C) Copyright 2010-2015 4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5 * yangnaitian, 2011-5-24, create this file 6 * 7 * Include file for SUNXI HCI Host Controller Driver 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 */ 15 16 #ifndef __SUNXI_HCI_SUNXI_H__ 17 #define __SUNXI_HCI_SUNXI_H__ 18 19 #include <linux/delay.h> 20 #include <linux/types.h> 21 22 #include <linux/io.h> 23 #include <linux/irq.h> 24 #include <linux/of_gpio.h> 25 #include <sunxi-gpio.h> 26 27 #include <linux/pm_wakeirq.h> 28 #include <linux/regulator/consumer.h> 29 30 extern int usb_disabled(void); 31 32 #define DMSG_ERR(format, args...) pr_err("hci: "format, ##args) 33 #define DMSG_PRINT(format, args...) pr_warn(format, ##args) 34 35 #define HCI_USBC_NO "hci_ctrl_no" 36 37 #if defined(CONFIG_ARCH_SUN8IW6) 38 #define HCI0_USBC_NO 1 39 #define HCI1_USBC_NO 2 40 #define HCI2_USBC_NO 3 41 #define HCI3_USBC_NO 4 42 #else 43 #define HCI0_USBC_NO 0 44 #define HCI1_USBC_NO 1 45 #define HCI2_USBC_NO 2 46 #define HCI3_USBC_NO 3 47 #endif 48 49 #define STANDBY_TIMEOUT 30000 50 51 /* 52 * Support Low-power mode USB standby. 53 */ 54 #if IS_ENABLED(CONFIG_ARCH_SUN8IW15) || IS_ENABLED(CONFIG_ARCH_SUN50IW9) \ 55 || IS_ENABLED(CONFIG_ARCH_SUN50IW10) 56 #define SUNXI_USB_STANDBY_LOW_POW_MODE 1 57 #endif 58 59 #if IS_ENABLED(CONFIG_ARCH_SUN50IW9) || IS_ENABLED(CONFIG_ARCH_SUN50IW10) 60 #define SUNXI_USB_STANDBY_NEW_MODE 1 61 #endif 62 63 #if 0 64 #define DMSG_DEBUG DMSG_PRINT 65 #else 66 #define DMSG_DEBUG(...) 67 #endif 68 69 #if 1 70 #define DMSG_INFO DMSG_PRINT 71 #else 72 #define DMSG_INFO(...) 73 #endif 74 75 #if 1 76 #define DMSG_PANIC DMSG_ERR 77 #else 78 #define DMSG_PANIC(...) 79 #endif 80 81 #define USBC_Readb(reg) readb(reg) 82 #define USBC_Readw(reg) readw(reg) 83 #define USBC_Readl(reg) readl(reg) 84 85 #define USBC_Writeb(value, reg) writeb(value, reg) 86 #define USBC_Writew(value, reg) writew(value, reg) 87 #define USBC_Writel(value, reg) writel(value, reg) 88 89 #define USBC_REG_test_bit_b(bp, reg) (USBC_Readb(reg) & (1 << (bp))) 90 #define USBC_REG_test_bit_w(bp, reg) (USBC_Readw(reg) & (1 << (bp))) 91 #define USBC_REG_test_bit_l(bp, reg) (USBC_Readl(reg) & (1 << (bp))) 92 93 #define USBC_REG_set_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) | (1 << (bp))), (reg))) 94 #define USBC_REG_set_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) | (1 << (bp))), (reg))) 95 #define USBC_REG_set_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) | (1 << (bp))), (reg))) 96 97 #define USBC_REG_clear_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) & (~(1 << (bp)))), (reg))) 98 #define USBC_REG_clear_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) & (~(1 << (bp)))), (reg))) 99 #define USBC_REG_clear_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) & (~(1 << (bp)))), (reg))) 100 101 #define SUNXI_USB_EHCI_BASE_OFFSET 0x00 102 #define SUNXI_USB_OHCI_BASE_OFFSET 0x400 103 #define SUNXI_USB_EHCI_LEN 0x58 104 #define SUNXI_USB_OHCI_LEN 0x58 105 106 #define SUNXI_USB_EHCI_TIME_INT 0x30 107 #define SUNXI_USB_EHCI_STANDBY_IRQ_STATUS 1 108 #define SUNXI_USB_EHCI_STANDBY_IRQ 2 109 110 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800 111 #define SUNXI_HCI_CTRL_3 0X808 112 #define SUNXI_HCI_PHY_CTRL 0x810 113 #define SUNXI_HCI_PHY_TUNE 0x818 114 #define SUNXI_HCI_UTMI_PHY_STATUS 0x824 115 #define SUNXI_HCI_CTRL_3_REMOTE_WAKEUP 3 116 #define SUNXI_HCI_RC16M_CLK_ENBALE 2 117 #if defined(CONFIG_ARCH_SUN8IW12) || defined(CONFIG_ARCH_SUN50IW6) \ 118 || defined(CONFIG_ARCH_SUN50IW3) || defined(CONFIG_ARCH_SUN8IW15) \ 119 || defined(CONFIG_ARCH_SUN50IW8) || defined(CONFIG_ARCH_SUN8IW18) \ 120 || defined(CONFIG_ARCH_SUN8IW16) || defined(CONFIG_ARCH_SUN50IW9) \ 121 || defined(CONFIG_ARCH_SUN50IW10) || defined(CONFIG_ARCH_SUN8IW19) \ 122 || defined(CONFIG_ARCH_SUN50IW11) || defined(CONFIG_ARCH_SUN8IW20)\ 123 || defined(CONFIG_ARCH_SUN20IW1) || defined(CONFIG_ARCH_SUN50IW12) 124 #define SUNXI_HCI_PHY_CTRL_SIDDQ 3 125 #else 126 #define SUNXI_HCI_PHY_CTRL_SIDDQ 1 127 #endif 128 129 #define SUNXI_OTG_PHY_CTRL 0x410 130 #define SUNXI_OTG_PHY_CFG 0x420 131 #define SUNXI_OTG_PHY_STATUS 0x424 132 #define SUNXI_USBC_REG_INTUSBE 0x0050 133 134 #define EHCI_CAP_OFFSET (0x00) 135 #define EHCI_CAP_LEN (0x10) 136 137 #define EHCI_CAP_CAPLEN (EHCI_CAP_OFFSET + 0x00) 138 #define EHCI_CAP_HCIVER (EHCI_CAP_OFFSET + 0x00) 139 #define EHCI_CAP_HCSPAR (EHCI_CAP_OFFSET + 0x04) 140 #define EHCI_CAP_HCCPAR (EHCI_CAP_OFFSET + 0x08) 141 #define EHCI_CAP_COMPRD (EHCI_CAP_OFFSET + 0x0c) 142 143 144 #define EHCI_OPR_OFFSET (EHCI_CAP_OFFSET + EHCI_CAP_LEN) 145 146 #define EHCI_OPR_USBCMD (EHCI_OPR_OFFSET + 0x00) 147 #define EHCI_OPR_USBSTS (EHCI_OPR_OFFSET + 0x04) 148 #define EHCI_OPR_USBINTR (EHCI_OPR_OFFSET + 0x08) 149 #define EHCI_OPR_FRINDEX (EHCI_OPR_OFFSET + 0x0c) 150 #define EHCI_OPR_CRTLDSS (EHCI_OPR_OFFSET + 0x10) 151 #define EHCI_OPR_PDLIST (EHCI_OPR_OFFSET + 0x14) 152 #define EHCI_OPR_ASLIST (EHCI_OPR_OFFSET + 0x18) 153 #define EHCI_OPR_CFGFLAG (EHCI_OPR_OFFSET + 0x40) 154 #define EHCI_OPR_PORTSC (EHCI_OPR_OFFSET + 0x44) 155 156 /** 157 * PORT Control and Status Register 158 * port_no is 0 based, 0, 1, 2, ..... 159 * 160 * Reg EHCI_OPR_PORTSC 161 */ 162 163 /* Port Test Control bits */ 164 #define EHCI_PORTSC_PTC_MASK (0xf<<16) 165 #define EHCI_PORTSC_PTC_DIS (0x0<<16) 166 #define EHCI_PORTSC_PTC_J (0x1<<16) 167 #define EHCI_PORTSC_PTC_K (0x2<<16) 168 #define EHCI_PORTSC_PTC_SE0NAK (0x3<<16) 169 #define EHCI_PORTSC_PTC_PACKET (0x4<<16) 170 #define EHCI_PORTSC_PTC_FORCE (0x5<<16) 171 172 #define EHCI_PORTSC_OWNER (0x1<<13) 173 #define EHCI_PORTSC_POWER (0x1<<12) 174 175 #define EHCI_PORTSC_LS_MASK (0x3<<10) 176 #define EHCI_PORTSC_LS_SE0 (0x0<<10) 177 #define EHCI_PORTSC_LS_J (0x2<<10) 178 #define EHCI_PORTSC_LS_K (0x1<<10) 179 #define EHCI_PORTSC_LS_UDF (0x3<<10) 180 181 #define EHCI_PORTSC_RESET (0x1<<8) 182 #define EHCI_PORTSC_SUSPEND (0x1<<7) 183 #define EHCI_PORTSC_RESUME (0x1<<6) 184 #define EHCI_PORTSC_OCC (0x1<<5) 185 #define EHCI_PORTSC_OC (0x1<<4) 186 #define EHCI_PORTSC_PEC (0x1<<3) 187 #define EHCI_PORTSC_PE (0x1<<2) 188 #define EHCI_PORTSC_CSC (0x1<<1) 189 #define EHCI_PORTSC_CCS (0x1<<0) 190 191 #define EHCI_PORTSC_CHANGE (EHCI_PORTSC_OCC | EHCI_PORTSC_PEC | EHCI_PORTSC_CSC) 192 193 #define SUNXI_USB_HCI_DEBUG 194 195 #define KEY_USB_WAKEUP_SUSPEND "usb_wakeup_suspend" 196 #define KEY_USB_HSIC_USBED "usb_hsic_used" 197 #define KEY_USB_HSIC_CTRL "usb_hsic_ctrl" 198 #define KEY_USB_HSIC_RDY_GPIO "usb_hsic_rdy_gpio" 199 #define KEY_USB_HSIC_REGULATOR_IO "usb_hsic_regulator_io" 200 #define KEY_WAKEUP_SOURCE "wakeup-source" 201 #define KEY_USB_PORT_TYPE "usb_port_type" 202 203 /* xHCI */ 204 #define XHCI_RESOURCES_NUM 2 205 #define XHCI_REGS_START 0x0 206 #define XHCI_REGS_END 0x7fff 207 208 /* xHCI Operational Registers */ 209 #define XHCI_OP_REGS_HCUSBCMD 0X0020 210 #define XHCI_OP_REGS_HCUSBSTS 0X0024 211 #define XHCI_OP_REGS_HCPORT1SC 0X0420 212 #define XHCI_OP_REGS_HCPORT1PMSC 0X0424 213 214 #define SUNXI_GLOBALS_REGS_START 0xc100 215 #define SUNXI_GLOBALS_REGS_END 0xc6ff 216 217 /* Global Registers */ 218 #define SUNXI_GLOBALS_REGS_GCTL 0xc110 219 #define SUNXI_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 220 #define SUNXI_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 221 222 /* Interface Status and Control Register */ 223 #define SUNXI_APP 0x10000 224 #define SUNXI_PIPE_CLOCK_CONTROL 0x10014 225 #define SUNXI_PHY_TUNE_LOW 0x10018 226 #define SUNXI_PHY_TUNE_HIGH 0x1001c 227 #define SUNXI_PHY_EXTERNAL_CONTROL 0x10020 228 229 /* Bit fields */ 230 231 /* Global Configuration Register */ 232 #define SUNXI_GCTL_PRTCAPDIR(n) ((n) << 12) 233 #define SUNXI_GCTL_PRTCAP_HOST 1 234 #define SUNXI_GCTL_PRTCAP_DEVICE 2 235 #define SUNXI_GCTL_PRTCAP_OTG 3 236 #define SUNXI_GCTL_SOFITPSYNC (0x01 << 10) 237 #define SUNXI_GCTL_CORESOFTRESET (1 << 11) 238 239 /* Global USB2 PHY Configuration Register n */ 240 #define SUNXI_USB2PHYCFG_SUSPHY (0x01 << 6) 241 #define SUNXI_USB2PHYCFG_PHYSOFTRST (1 << 31) 242 243 /* Global USB3 PIPE Control Register */ 244 #define SUNXI_USB3PIPECTL_PHYSOFTRST (1 << 31) 245 246 /* USB2.0 Interface Status and Control Register */ 247 #define SUNXI_APP_FOCE_VBUS (0x03 << 12) 248 249 /* PIPE Clock Control Register */ 250 #define SUNXI_PPC_PIPE_CLK_OPEN (0x01 << 6) 251 252 /* PHY External Control Register */ 253 #define SUNXI_PEC_EXTERN_VBUS (0x03 << 1) 254 #define SUNXI_PEC_SSC_EN (0x01 << 24) 255 #define SUNXI_PEC_REF_SSP_EN (0x01 << 26) 256 257 /* PHY Tune High Register */ 258 #define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) 259 #define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) 260 #define SUNXI_TX_SWING_FULL(n) ((n) << 6) 261 #define SUNXI_LOS_BIAS(n) ((n) << 3) 262 #define SUNXI_TXVBOOSTLVL(n) ((n) << 0) 263 264 /* HCI UTMI PHY TUNE */ 265 #define SUNXI_TX_VREF_TUNE_OFFSET 8 266 #define SUNXI_TX_RISE_TUNE_OFFSET 4 267 #define SUNXI_TX_RES_TUNE_OFFSET 2 268 #define SUNXI_TX_PREEMPAMP_TUNE_OFFSET 0 269 #define SUNXI_TX_VREF_TUNE (0xf << SUNXI_TX_VREF_TUNE_OFFSET) 270 #define SUNXI_TX_RISE_TUNE (0x3 << SUNXI_TX_RISE_TUNE_OFFSET) 271 #define SUNXI_TX_RES_TUNE (0x3 << SUNXI_TX_RES_TUNE_OFFSET) 272 #define SUNXI_TX_PREEMPAMP_TUNE (0x3 << SUNXI_TX_PREEMPAMP_TUNE_OFFSET) 273 274 /* PHYS EFUSE offest */ 275 #define EFUSE_OFFSET 0x18 //esuse offset 276 #define SUNXI_HCI_PHY_EFUSE_ADJUST 0x10000 //bit16 277 #define SUNXI_HCI_PHY_EFUSE_MODE 0x20000 //bit17 278 #define SUNXI_HCI_PHY_EFUSE_RES 0x3C0000 //bit18-21 279 #define SUNXI_HCI_PHY_EFUSE_COM 0x1C00000 //bit22-24 280 #define SUNXI_HCI_PHY_EFUSE_USB0TX 0x1C00000 //bit22-24 281 #define SUNXI_HCI_PHY_EFUSE_USB1TX 0xE000000 //bit25-27 282 283 #if defined(CONFIG_FPGA_V4_PLATFORM) || defined(CONFIG_FPGA_V7_PLATFORM) 284 #define SUNXI_USB_FPGA 285 #endif 286 287 enum sunxi_usbc_type { 288 SUNXI_USB_UNKNOWN = 0, 289 SUNXI_USB_EHCI, 290 SUNXI_USB_OHCI, 291 SUNXI_USB_XHCI, 292 SUNXI_USB_PHY, 293 SUNXI_USB_ALL, 294 }; 295 296 enum usb_drv_vbus_type { 297 USB_DRV_VBUS_TYPE_NULL = 0, 298 USB_DRV_VBUS_TYPE_GIPO, 299 USB_DRV_VBUS_TYPE_AXP, 300 }; 301 302 /* 0: device only; 1: host only; 2: otg */ 303 enum usb_port_type { 304 USB_PORT_TYPE_DEVICE = 0, 305 USB_PORT_TYPE_HOST, 306 USB_PORT_TYPE_OTG, 307 }; 308 309 enum usb_wakeup_source_type { 310 SUPER_STANDBY = 0, 311 USB_STANDBY, 312 }; 313 314 struct sunxi_hci_hcd { 315 __u32 usbc_no; /* usb controller number */ 316 __u32 irq_no; /* interrupt number */ 317 char hci_name[32]; /* hci name */ 318 319 struct resource *usb_base_res; /* USB resources */ 320 struct resource *usb_base_req; /* USB resources */ 321 void __iomem *usb_vbase; /* USB base address */ 322 323 void __iomem *otg_vbase; /* USB base address */ 324 325 void __iomem *ehci_base; 326 __u32 ehci_reg_length; 327 void __iomem *ohci_base; 328 __u32 ohci_reg_length; 329 330 #if IS_ENABLED(CONFIG_ARCH_SUN50IW10) 331 /* for usb standby*/ 332 void __iomem *prcm; 333 334 /* for keep common circuit configuration */ 335 void __iomem *usb_common_phy_config; 336 void __iomem *usb_ccmu_config; 337 338 #define SUNXI_CCMU_SCLK_GATING_USBPHY1_OFFSET (1UL << 29) 339 #define SUNXI_CCMU_USBPHY1_RST_OFFSET (1UL << 30) 340 #define SUNXI_CCMU_SCLK_GATING_OHCI1_OFFSET (1UL << 31) 341 342 #define SUNXI_CCMU_USBEHCI1_GATING_OFFSET (1UL << 5) 343 #define SUNXI_CCMU_USBEHCI1_RST_OFFSET (1UL << 21) 344 #endif 345 346 struct resource *sram_base_res; /* SRAM resources */ 347 struct resource *sram_base_req; /* SRAM resources */ 348 void __iomem *sram_vbase; /* SRAM base address */ 349 __u32 sram_reg_start; 350 __u32 sram_reg_length; 351 352 struct resource *clock_base_res; /* clock resources */ 353 struct resource *clock_base_req; /* clock resources */ 354 void __iomem *clock_vbase; /* clock base address */ 355 __u32 clock_reg_start; 356 __u32 clock_reg_length; 357 358 struct resource *gpio_base_res; /* gpio resources */ 359 struct resource *gpio_base_req; /* gpio resources */ 360 void __iomem *gpio_vbase; /* gpio base address */ 361 __u32 gpio_reg_start; 362 __u32 gpio_reg_length; 363 364 struct resource *sdram_base_res; /* sdram resources */ 365 struct resource *sdram_base_req; /* sdram resources */ 366 void __iomem *sdram_vbase; /* sdram base address */ 367 __u32 sdram_reg_start; 368 __u32 sdram_reg_length; 369 370 struct platform_device *pdev; 371 struct usb_hcd *hcd; 372 373 struct clk *clk_bus_hci; 374 struct clk *clk_ohci; 375 struct clk *clk_phy; 376 377 /* legacy, fix me */ 378 struct clk *mod_usb; /* mod_usb otg clock handle */ 379 struct clk *hsic_usbphy; /* hsic clock handle */ 380 struct clk *pll_hsic; /* pll_hsic clock handle */ 381 struct clk *clk_usbhsic12m; /* pll_hsic clock handle */ 382 struct clk *clk_usbohci12m; /* clk_usbohci12m clock handle */ 383 struct clk *clk_hoscx2; /* clk_hoscx2 clock handle */ 384 struct clk *clk_hosc; /* clk_hosc clock handle */ 385 struct clk *clk_losc; /* clk_losc clock handle */ 386 387 struct reset_control *reset_hci; 388 struct reset_control *reset_phy; 389 390 __u32 clk_is_open; /* is usb clock open */ 391 392 struct gpio_config drv_vbus_gpio_set; 393 394 const char *regulator_io; 395 const char *used_status; 396 int regulator_value; 397 struct regulator *regulator_io_hdle; 398 enum usb_drv_vbus_type drv_vbus_type; 399 const char *drv_vbus_name; 400 const char *det_vbus_name; 401 u32 usb_restrict_valid; 402 __u8 power_flag; /* flag. power on or not */ 403 struct regulator *supply; 404 struct regulator *hci_regulator; /* hci regulator: VCC_USB */ 405 406 int used; /* flag. in use or not */ 407 __u8 probe; /* hc initialize */ 408 __u8 no_suspend; /* when usb is being enable, stop system suspend */ 409 enum usb_port_type port_type; /* usb port type */ 410 int wakeup_suspend; /* flag. not suspend */ 411 412 int wakeup_source_flag; 413 414 /* HSIC device susport */ 415 u32 hsic_flag; /* flag. hsic usbed */ 416 const char *hsic_regulator_io; 417 struct regulator *hsic_regulator_io_hdle; 418 419 /* Marvell 4G HSIC ctrl */ 420 struct gpio_config usb_host_hsic_rdy; 421 u32 usb_host_hsic_rdy_valid; 422 u32 hsic_ctrl_flag; /* flag. hsic ctrl */ 423 u32 hsic_enable_flag; /* flag. hsic enable */ 424 425 /* SMSC usb3503 HSIC HUB ctrl */ 426 u32 usb_hsic_usb3503_flag; 427 428 struct gpio_config usb_hsic_hub_connect; 429 u32 usb_hsic_hub_connect_valid; 430 431 struct gpio_config usb_hsic_int_n; 432 u32 usb_hsic_int_n_valid; 433 434 struct gpio_config usb_hsic_reset_n; 435 u32 usb_hsic_reset_n_valid; 436 437 438 int (*open_clock)(struct sunxi_hci_hcd *sunxi_hci, u32 ohci); 439 int (*close_clock)(struct sunxi_hci_hcd *sunxi_hci, u32 ohci); 440 void (*set_power)(struct sunxi_hci_hcd *sunxi_hci, int is_on); 441 void (*port_configure)(struct sunxi_hci_hcd *sunxi_hci, u32 enable); 442 void (*usb_passby)(struct sunxi_hci_hcd *sunxi_hci, u32 enable); 443 void (*hci_phy_ctrl)(struct sunxi_hci_hcd *sunxi_hci, u32 enable); 444 445 /* xhci */ 446 struct resource xhci_resources[XHCI_RESOURCES_NUM]; 447 spinlock_t lock; 448 struct device *dev; 449 void *mem; 450 void __iomem *regs; 451 size_t regs_size; 452 void __iomem *xhci_base; 453 __u32 xhci_reg_length; 454 455 /* resume work */ 456 struct work_struct resume_work; 457 struct completion standby_complete; 458 }; 459 460 int sunxi_hci_standby_completion(int usbc_type); 461 int init_sunxi_hci(struct platform_device *pdev, int usbc_type); 462 int exit_sunxi_hci(struct sunxi_hci_hcd *sunxi_hci); 463 int sunxi_get_hci_num(struct platform_device *pdev); 464 void sunxi_set_host_hisc_rdy(struct sunxi_hci_hcd *sunxi_hci, int is_on); 465 void sunxi_set_host_vbus(struct sunxi_hci_hcd *sunxi_hci, int is_on); 466 int usb_phyx_tp_write(struct sunxi_hci_hcd *sunxi_hci, 467 int addr, int data, int len); 468 int usb_phyx_write(struct sunxi_hci_hcd *sunxi_hci, int data); 469 int usb_phyx_read(struct sunxi_hci_hcd *sunxi_hci); 470 int usb_phyx_tp_read(struct sunxi_hci_hcd *sunxi_hci, int addr, int len); 471 int sunxi_usb_enable_xhci(void); 472 int sunxi_usb_disable_xhci(void); 473 void enter_usb_standby(struct sunxi_hci_hcd *sunxi_hci); 474 void exit_usb_standby(struct sunxi_hci_hcd *sunxi_hci); 475 #if IS_ENABLED(SUNXI_USB_STANDBY_LOW_POW_MODE) 476 void sunxi_hci_set_siddq(struct sunxi_hci_hcd *sunxi_hci, int is_on); 477 void sunxi_hci_set_wakeup_ctrl(struct sunxi_hci_hcd *sunxi_hci, int is_on); 478 void sunxi_hci_set_rc_clk(struct sunxi_hci_hcd *sunxi_hci, int is_on); 479 void sunxi_hci_set_standby_irq(struct sunxi_hci_hcd *sunxi_hci, int is_on); 480 void sunxi_hci_clean_standby_irq(struct sunxi_hci_hcd *sunxi_hci); 481 #endif 482 483 #if IS_ENABLED(CONFIG_ARCH_SUN50IW10) 484 void sunxi_hci_common_set_rc_clk(struct sunxi_hci_hcd *sunxi_hci, 485 int is_on); 486 void sunxi_hci_common_switch_clk(struct sunxi_hci_hcd *sunxi_hci, 487 int is_on); 488 void sunxi_hci_common_set_rcgating(struct sunxi_hci_hcd *sunxi_hci, 489 int is_on); 490 void sunxi_hci_set_rcgating(struct sunxi_hci_hcd *sunxi_hci, 491 int is_on); 492 void sunxi_hci_switch_clk(struct sunxi_hci_hcd *sunxi_hci, 493 int is_on); 494 #endif 495 #endif /* __SUNXI_HCI_SUNXI_H__ */ 496