1 /* 2 * (C) Copyright 2007-2013 3 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com> 4 * Aaron.Maoye <leafy.myeh@reuuimllatech.com> 5 * 6 * Some macro and struct of Allwinner UART controller. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * 2013.6.6 Mintow <duanmintao@allwinnertech.com> 14 * Adapt to support sun8i/sun9i of Allwinner. 15 */ 16 17 #ifndef _SUNXI_UART_H_ 18 #define _SUNXI_UART_H_ 19 20 #include <linux/regulator/consumer.h> 21 #include <linux/dmaengine.h> 22 #include <linux/reset.h> 23 //include <linux/serial_core.h> 24 25 /* SUNXI UART PORT definition*/ 26 #define PORT_MAX_USED PORT_LINFLEXUART /* see include/uapi/linux/serial_core.h */ 27 #define PORT_SUNXI (PORT_MAX_USED + 1) 28 29 struct sw_uart_pdata { 30 unsigned int used; 31 unsigned int io_num; 32 unsigned int port_no; 33 char regulator_id[16]; 34 struct regulator *regulator; 35 }; 36 37 #if IS_ENABLED(CONFIG_SERIAL_SUNXI_DMA) 38 struct sw_uart_dma { 39 u32 use_dma; /* 1:used */ 40 41 /* receive and transfer buffer */ 42 char *rx_buffer; /* visual memory */ 43 char *tx_buffer; 44 dma_addr_t rx_phy_addr; /* physical memory */ 45 dma_addr_t tx_phy_addr; 46 u32 rb_size; /* buffer size */ 47 u32 tb_size; 48 49 /* regard the rx buffer as a circular buffer */ 50 u32 rb_head; 51 u32 rb_tail; 52 u32 rx_size; 53 54 dma_cookie_t rx_cookie; 55 56 char tx_dma_inited; /* 1:dma tx channel has been init */ 57 char rx_dma_inited; /* 1:dma rx channel has been init */ 58 char tx_dma_used; /* 1:dma tx is working */ 59 char rx_dma_used; /* 1:dma rx is working */ 60 61 /* timer to poll activity on rx dma */ 62 char use_timer; 63 int rx_timeout; 64 65 struct dma_chan *dma_chan_rx, *dma_chan_tx; 66 struct scatterlist rx_sgl, tx_sgl; 67 unsigned int rx_bytes, tx_bytes; 68 }; 69 #endif 70 71 struct sw_uart_port { 72 struct uart_port port; 73 char name[16]; 74 struct clk *mclk; 75 struct clk *sclk; 76 struct clk *pclk; 77 struct reset_control *reset; 78 unsigned char id; 79 unsigned char ier; 80 unsigned char lcr; 81 unsigned char mcr; 82 unsigned char fcr; 83 unsigned char dll; 84 unsigned char dlh; 85 unsigned char rs485; 86 unsigned char msr_saved_flags; 87 unsigned int lsr_break_flag; 88 struct sw_uart_pdata *pdata; 89 #if IS_ENABLED(CONFIG_SERIAL_SUNXI_DMA) 90 struct sw_uart_dma *dma; 91 struct hrtimer rx_hrtimer; 92 u32 rx_last_pos; 93 #define SUNXI_UART_DRQ_RX(ch) (DRQSRC_UART0_RX + ch) 94 #define SUNXI_UART_DRQ_TX(ch) (DRQDST_UART0_TX + ch) 95 #endif 96 97 /* for debug */ 98 #define MAX_DUMP_SIZE 1024 99 unsigned int dump_len; 100 char *dump_buff; 101 struct proc_dir_entry *proc_root; 102 struct proc_dir_entry *proc_info; 103 104 struct pinctrl *pctrl; 105 struct serial_rs485 rs485conf; 106 bool card_print; 107 bool throttled; 108 }; 109 110 /* register offset define */ 111 #define SUNXI_UART_RBR (0x00) /* receive buffer register */ 112 #define SUNXI_UART_THR (0x00) /* transmit holding register */ 113 #define SUNXI_UART_DLL (0x00) /* divisor latch low register */ 114 #define SUNXI_UART_DLH (0x04) /* diviso latch high register */ 115 #define SUNXI_UART_IER (0x04) /* interrupt enable register */ 116 #define SUNXI_UART_IIR (0x08) /* interrupt identity register */ 117 #define SUNXI_UART_FCR (0x08) /* FIFO control register */ 118 #define SUNXI_UART_LCR (0x0c) /* line control register */ 119 #define SUNXI_UART_MCR (0x10) /* modem control register */ 120 #define SUNXI_UART_LSR (0x14) /* line status register */ 121 #define SUNXI_UART_MSR (0x18) /* modem status register */ 122 #define SUNXI_UART_SCH (0x1c) /* scratch register */ 123 #define SUNXI_UART_USR (0x7c) /* status register */ 124 #define SUNXI_UART_TFL (0x80) /* transmit FIFO level */ 125 #define SUNXI_UART_RFL (0x84) /* RFL */ 126 #define SUNXI_UART_HALT (0xa4) /* halt tx register */ 127 #define SUNXI_UART_RS485 (0xc0) /* RS485 control and status register */ 128 129 /* register bit field define */ 130 /* Interrupt Enable Register */ 131 #define SUNXI_UART_IER_PTIME (BIT(7)) 132 #define SUNXI_UART_IER_RS485 (BIT(4)) 133 #define SUNXI_UART_IER_MSI (BIT(3)) 134 #define SUNXI_UART_IER_RLSI (BIT(2)) 135 #define SUNXI_UART_IER_THRI (BIT(1)) 136 #define SUNXI_UART_IER_RDI (BIT(0)) 137 /* Interrupt ID Register */ 138 #define SUNXI_UART_IIR_FEFLAG_MASK (BIT(6)|BIT(7)) 139 #define SUNXI_UART_IIR_IID_MASK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 140 #define SUNXI_UART_IIR_IID_MSTA (0) 141 #define SUNXI_UART_IIR_IID_NOIRQ (1) 142 #define SUNXI_UART_IIR_IID_THREMP (2) 143 #define SUNXI_UART_IIR_IID_RXDVAL (4) 144 #define SUNXI_UART_IIR_IID_LINESTA (6) 145 #define SUNXI_UART_IIR_IID_BUSBSY (7) 146 #define SUNXI_UART_IIR_IID_CHARTO (12) 147 /* FIFO Control Register */ 148 #define SUNXI_UART_FCR_RXTRG_MASK (BIT(6)|BIT(7)) 149 #define SUNXI_UART_FCR_RXTRG_1CH (0 << 6) 150 #define SUNXI_UART_FCR_RXTRG_1_4 (1 << 6) 151 #define SUNXI_UART_FCR_RXTRG_1_2 (2 << 6) 152 #define SUNXI_UART_FCR_RXTRG_FULL (3 << 6) 153 #define SUNXI_UART_FCR_TXTRG_MASK (BIT(4)|BIT(5)) 154 #define SUNXI_UART_FCR_TXTRG_EMP (0 << 4) 155 #define SUNXI_UART_FCR_TXTRG_2CH (1 << 4) 156 #define SUNXI_UART_FCR_TXTRG_1_4 (2 << 4) 157 #define SUNXI_UART_FCR_TXTRG_1_2 (3 << 4) 158 #define SUNXI_UART_FCR_TXFIFO_RST (BIT(2)) 159 #define SUNXI_UART_FCR_RXFIFO_RST (BIT(1)) 160 #define SUNXI_UART_FCR_FIFO_EN (BIT(0)) 161 /* Line Control Register */ 162 #define SUNXI_UART_LCR_DLAB (BIT(7)) 163 #define SUNXI_UART_LCR_SBC (BIT(6)) 164 #define SUNXI_UART_LCR_PARITY_MASK (BIT(5)|BIT(4)) 165 #define SUNXI_UART_LCR_EPAR (1 << 4) 166 #define SUNXI_UART_LCR_OPAR (0 << 4) 167 #define SUNXI_UART_LCR_PARITY (BIT(3)) 168 #define SUNXI_UART_LCR_STOP (BIT(2)) 169 #define SUNXI_UART_LCR_DLEN_MASK (BIT(1)|BIT(0)) 170 #define SUNXI_UART_LCR_WLEN5 (0) 171 #define SUNXI_UART_LCR_WLEN6 (1) 172 #define SUNXI_UART_LCR_WLEN7 (2) 173 #define SUNXI_UART_LCR_WLEN8 (3) 174 /* Modem Control Register */ 175 #define SUNXI_UART_MCR_MODE_MASK (BIT(7)|BIT(6)) 176 #define SUNXI_UART_MCR_MODE_RS485 (2 << 6) 177 #define SUNXI_UART_MCR_MODE_SIRE (1 << 6) 178 #define SUNXI_UART_MCR_MODE_UART (0 << 6) 179 #define SUNXI_UART_MCR_AFE (BIT(5)) 180 #define SUNXI_UART_MCR_LOOP (BIT(4)) 181 #define SUNXI_UART_MCR_RTS (BIT(1)) 182 #define SUNXI_UART_MCR_DTR (BIT(0)) 183 /* Line Status Rigster */ 184 #define SUNXI_UART_LSR_RXFIFOE (BIT(7)) 185 #define SUNXI_UART_LSR_TEMT (BIT(6)) 186 #define SUNXI_UART_LSR_THRE (BIT(5)) 187 #define SUNXI_UART_LSR_BI (BIT(4)) 188 #define SUNXI_UART_LSR_FE (BIT(3)) 189 #define SUNXI_UART_LSR_PE (BIT(2)) 190 #define SUNXI_UART_LSR_OE (BIT(1)) 191 #define SUNXI_UART_LSR_DR (BIT(0)) 192 #define SUNXI_UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ 193 /* Modem Status Register */ 194 #define SUNXI_UART_MSR_DCD (BIT(7)) 195 #define SUNXI_UART_MSR_RI (BIT(6)) 196 #define SUNXI_UART_MSR_DSR (BIT(5)) 197 #define SUNXI_UART_MSR_CTS (BIT(4)) 198 #define SUNXI_UART_MSR_DDCD (BIT(3)) 199 #define SUNXI_UART_MSR_TERI (BIT(2)) 200 #define SUNXI_UART_MSR_DDSR (BIT(1)) 201 #define SUNXI_UART_MSR_DCTS (BIT(0)) 202 #define SUNXI_UART_MSR_ANY_DELTA 0x0F 203 #define MSR_SAVE_FLAGS SUNXI_UART_MSR_ANY_DELTA 204 /* Status Register */ 205 #define SUNXI_UART_USR_RFF (BIT(4)) 206 #define SUNXI_UART_USR_RFNE (BIT(3)) 207 #define SUNXI_UART_USR_TFE (BIT(2)) 208 #define SUNXI_UART_USR_TFNF (BIT(1)) 209 #define SUNXI_UART_USR_BUSY (BIT(0)) 210 /* Halt Register */ 211 #define SUNXI_UART_HALT_PTE (BIT(7)) 212 #define SUNXI_UART_HALT_LCRUP (BIT(2)) 213 #define SUNXI_UART_HALT_FORCECFG (BIT(1)) 214 #define SUNXI_UART_HALT_HTX (BIT(0)) 215 /* RS485 Control and Status Register */ 216 #define SUNXI_UART_RS485_RXBFA (BIT(3)) 217 #define SUNXI_UART_RS485_RXAFA (BIT(2)) 218 219 /* The global infor of UART channel. */ 220 221 #if IS_ENABLED(CONFIG_ARCH_SUN50IW10) 222 #define SUNXI_UART_NUM 8 223 #endif 224 225 #if IS_ENABLED(CONFIG_ARCH_SUN8IW15) 226 #define SUNXI_UART_NUM 5 227 #endif 228 229 #if IS_ENABLED(CONFIG_ARCH_SUN8IW20) || IS_ENABLED(CONFIG_ARCH_SUN20IW1) || IS_ENABLED(CONFIG_ARCH_SUN50IW9) 230 #define SUNXI_UART_NUM 6 231 #endif 232 233 #ifndef SUNXI_UART_NUM 234 #define SUNXI_UART_NUM 1 235 #endif 236 237 /* In 50/39 FPGA, two UART is available, but they share one IRQ. 238 So we define the number of UART port as 1. */ 239 #if !IS_ENABLED(CONFIG_AW_IC_BOARD) 240 #undef SUNXI_UART_NUM 241 #define SUNXI_UART_NUM 1 242 #endif 243 244 #define SUNXI_UART_FIFO_SIZE 64 245 246 #define SUNXI_UART_DEV_NAME "uart" 247 248 struct platform_device *sw_uart_get_pdev(int uart_id); 249 250 #endif /* end of _SUNXI_UART_H_ */ 251